Merge branch 'generalizations'
this merges common c and header files of different architectures, adds a dispatch mechanism and yaml descriptions of interrupt handlers from which the whole interrupt table setup c code is generated.
This commit is contained in:
chrysn
commit
a01e5c201b
18
Makefile
18
Makefile
@ -39,7 +39,19 @@ all: build
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build: lib examples
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build: lib examples
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lib:
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generatedheaders:
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@printf " UPDATING HEADERS\n"
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$(Q)for yamlfile in `find -name 'irq.yaml'`; do \
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./scripts/irq2nvic_h $$yamlfile ; \
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done
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cleanheaders:
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@printf " CLEANING HEADERS\n"
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$(Q)for yamlfile in `find -name 'irq.yaml'`; do \
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./scripts/irq2nvic_h --remove $$yamlfile ; \
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done
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lib: generatedheaders
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$(Q)for i in $(addprefix $@/,$(TARGETS)); do \
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$(Q)for i in $(addprefix $@/,$(TARGETS)); do \
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if [ -d $$i ]; then \
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if [ -d $$i ]; then \
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printf " BUILD $$i\n"; \
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printf " BUILD $$i\n"; \
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@ -71,7 +83,7 @@ install: lib
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doc:
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doc:
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$(Q)$(MAKE) -C doc doc
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$(Q)$(MAKE) -C doc doc
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clean:
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clean: cleanheaders
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$(Q)for i in $(addprefix lib/,$(TARGETS)) \
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$(Q)for i in $(addprefix lib/,$(TARGETS)) \
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$(addsuffix /*/*,$(addprefix examples/,$(TARGETS))); do \
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$(addsuffix /*/*,$(addprefix examples/,$(TARGETS))); do \
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if [ -d $$i ]; then \
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if [ -d $$i ]; then \
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@ -82,5 +94,5 @@ clean:
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@printf " CLEAN doxygen\n"
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@printf " CLEAN doxygen\n"
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$(Q)$(MAKE) -C doc clean
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$(Q)$(MAKE) -C doc clean
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.PHONY: build lib examples install doc clean
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.PHONY: build lib examples install doc clean generatedheaders cleanheaders
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@ -37,7 +37,7 @@ endif
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endif
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endif
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CFLAGS += -O0 -g3 -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \
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CFLAGS += -O0 -g3 -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \
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-mcpu=cortex-m3 -mthumb -MD
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-mcpu=cortex-m3 -mthumb -MD -DLM3S
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LDSCRIPT ?= $(BINARY).ld
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LDSCRIPT ?= $(BINARY).ld
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LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \
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LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \
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-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections
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-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections
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@ -37,7 +37,7 @@ endif
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endif
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endif
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CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \
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CFLAGS += -Os -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \
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-mcpu=cortex-m3 -mthumb -MD
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-mcpu=cortex-m3 -mthumb -MD -DLPC13XX
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LDSCRIPT ?= $(BINARY).ld
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LDSCRIPT ?= $(BINARY).ld
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LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \
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LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \
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-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections
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-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections
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@ -37,7 +37,7 @@ endif
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endif
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endif
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CFLAGS += -O0 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \
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CFLAGS += -O0 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \
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-mcpu=cortex-m3 -mthumb -MD
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-mcpu=cortex-m3 -mthumb -MD -DLPC17XX
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LDSCRIPT ?= $(BINARY).ld
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LDSCRIPT ?= $(BINARY).ld
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LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \
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LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \
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-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections
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-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections
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@ -41,7 +41,7 @@ endif
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CFLAGS += -O2 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \
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CFLAGS += -O2 -g -Wall -Wextra -I$(TOOLCHAIN_DIR)/include -fno-common \
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-mcpu=cortex-m4 -mthumb -MD \
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-mcpu=cortex-m4 -mthumb -MD \
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-mfloat-abi=hard -mfpu=fpv4-sp-d16
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-mfloat-abi=hard -mfpu=fpv4-sp-d16 -DLPC43XX
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LDSCRIPT ?= $(BINARY).ld
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LDSCRIPT ?= $(BINARY).ld
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LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \
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LDFLAGS += -L$(TOOLCHAIN_DIR)/lib \
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-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections -Xlinker -Map=$(BINARY).map
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-T$(LDSCRIPT) -nostartfiles -Wl,--gc-sections -Xlinker -Map=$(BINARY).map
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@ -20,8 +20,8 @@
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#include <libopencm3/lpc43xx/gpio.h>
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#include <libopencm3/lpc43xx/gpio.h>
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#include <libopencm3/lpc43xx/scu.h>
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#include <libopencm3/lpc43xx/scu.h>
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#include <libopencm3/lpc43xx/cgu.h>
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#include <libopencm3/lpc43xx/cgu.h>
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#include <libopencm3/lpc43xx/nvic.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/lpc43xx/systick.h>
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#include <libopencm3/cm3/systick.h>
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#include <libopencm3/cm3/scs.h>
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#include <libopencm3/cm3/scs.h>
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#include "../jellybean_conf.h"
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#include "../jellybean_conf.h"
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@ -21,8 +21,8 @@
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/flash.h>
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#include <libopencm3/stm32/f1/flash.h>
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/nvic.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/stm32/systick.h>
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#include <libopencm3/cm3/systick.h>
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#include <libopencm3/stm32/can.h>
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#include <libopencm3/stm32/can.h>
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struct can_tx_msg {
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struct can_tx_msg {
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@ -21,7 +21,7 @@
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/f1/flash.h>
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#include <libopencm3/stm32/f1/flash.h>
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#include <libopencm3/stm32/f1/scb.h>
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#include <libopencm3/cm3/scb.h>
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#include <libopencm3/usb/usbd.h>
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#include <libopencm3/usb/usbd.h>
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#include <libopencm3/usb/dfu.h>
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#include <libopencm3/usb/dfu.h>
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@ -21,7 +21,7 @@
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#include <stdlib.h>
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#include <stdlib.h>
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/systick.h>
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#include <libopencm3/cm3/systick.h>
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#include <libopencm3/stm32/spi.h>
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#include <libopencm3/stm32/spi.h>
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#include <libopencm3/stm32/otg_fs.h>
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#include <libopencm3/stm32/otg_fs.h>
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#include <libopencm3/usb/usbd.h>
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#include <libopencm3/usb/usbd.h>
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@ -32,7 +32,7 @@
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#define INCLUDE_DFU_INTERFACE
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#define INCLUDE_DFU_INTERFACE
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#ifdef INCLUDE_DFU_INTERFACE
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#ifdef INCLUDE_DFU_INTERFACE
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#include <libopencm3/stm32/f1/scb.h>
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#include <libopencm3/cm3/scb.h>
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#include <libopencm3/usb/dfu.h>
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#include <libopencm3/usb/dfu.h>
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#endif
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#endif
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@ -25,7 +25,7 @@
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#include <libopencm3/stm32/f1/adc.h>
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#include <libopencm3/stm32/f1/adc.h>
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#include <libopencm3/stm32/usart.h>
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#include <libopencm3/stm32/usart.h>
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#include <libopencm3/stm32/timer.h>
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#include <libopencm3/stm32/timer.h>
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#include <libopencm3/stm32/nvic.h>
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#include <libopencm3/cm3/nvic.h>
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volatile u16 temperature = 0;
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volatile u16 temperature = 0;
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@ -25,7 +25,7 @@
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#include <libopencm3/stm32/f1/adc.h>
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#include <libopencm3/stm32/f1/adc.h>
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#include <libopencm3/stm32/usart.h>
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#include <libopencm3/stm32/usart.h>
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#include <libopencm3/stm32/timer.h>
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#include <libopencm3/stm32/timer.h>
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#include <libopencm3/stm32/nvic.h>
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#include <libopencm3/cm3/nvic.h>
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volatile u16 temperature = 0;
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volatile u16 temperature = 0;
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volatile u16 v_refint = 0;
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volatile u16 v_refint = 0;
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@ -21,7 +21,7 @@
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/usart.h>
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#include <libopencm3/stm32/usart.h>
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#include <libopencm3/stm32/f1/dma.h>
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#include <libopencm3/stm32/f1/dma.h>
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#include <libopencm3/stm32/nvic.h>
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#include <libopencm3/cm3/nvic.h>
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void clock_setup(void)
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void clock_setup(void)
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{
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{
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@ -20,7 +20,7 @@
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/f1/gpio.h>
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#include <libopencm3/stm32/usart.h>
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#include <libopencm3/stm32/usart.h>
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#include <libopencm3/stm32/nvic.h>
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#include <libopencm3/cm3/nvic.h>
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|
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void clock_setup(void)
|
void clock_setup(void)
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{
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{
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@ -21,8 +21,8 @@
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/rcc.h>
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#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
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||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
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#include <libopencm3/stm32/nvic.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/stm32/systick.h>
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#include <libopencm3/cm3/systick.h>
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#include <stdio.h>
|
#include <stdio.h>
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#include <errno.h>
|
#include <errno.h>
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|
|
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@ -21,7 +21,7 @@
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|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
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||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
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||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
|
|
||||||
|
|||||||
@ -21,8 +21,8 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/flash.h>
|
#include <libopencm3/stm32/f1/flash.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/systick.h>
|
#include <libopencm3/cm3/systick.h>
|
||||||
#include <libopencm3/stm32/can.h>
|
#include <libopencm3/stm32/can.h>
|
||||||
|
|
||||||
struct can_tx_msg {
|
struct can_tx_msg {
|
||||||
|
|||||||
@ -21,8 +21,8 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/flash.h>
|
#include <libopencm3/stm32/f1/flash.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/systick.h>
|
#include <libopencm3/cm3/systick.h>
|
||||||
|
|
||||||
u32 temp32;
|
u32 temp32;
|
||||||
|
|
||||||
|
|||||||
@ -20,7 +20,7 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
|
|
||||||
void clock_setup(void)
|
void clock_setup(void)
|
||||||
{
|
{
|
||||||
|
|||||||
@ -22,7 +22,7 @@
|
|||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
|
||||||
#include <libopencm3/stm32/timer.h>
|
#include <libopencm3/stm32/timer.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/spi.h>
|
#include <libopencm3/stm32/spi.h>
|
||||||
#include "./dogm128.h"
|
#include "./dogm128.h"
|
||||||
|
|
||||||
|
|||||||
@ -22,7 +22,7 @@
|
|||||||
#include <libopencm3/stm32/f1/rtc.h>
|
#include <libopencm3/stm32/f1/rtc.h>
|
||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
|
||||||
#include <libopencm3/stm32/pwr.h>
|
#include <libopencm3/stm32/pwr.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
|
|
||||||
void clock_setup(void)
|
void clock_setup(void)
|
||||||
{
|
{
|
||||||
|
|||||||
@ -20,8 +20,8 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/flash.h>
|
#include <libopencm3/stm32/f1/flash.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/systick.h>
|
#include <libopencm3/cm3/systick.h>
|
||||||
|
|
||||||
u32 temp32;
|
u32 temp32;
|
||||||
|
|
||||||
|
|||||||
@ -21,7 +21,7 @@
|
|||||||
#include <libopencm3/stm32/f1/flash.h>
|
#include <libopencm3/stm32/f1/flash.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/timer.h>
|
#include <libopencm3/stm32/timer.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
|
|
||||||
void gpio_setup(void)
|
void gpio_setup(void)
|
||||||
{
|
{
|
||||||
|
|||||||
@ -21,7 +21,7 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/f1/flash.h>
|
#include <libopencm3/stm32/f1/flash.h>
|
||||||
#include <libopencm3/stm32/f1/scb.h>
|
#include <libopencm3/cm3/scb.h>
|
||||||
#include <libopencm3/usb/usbd.h>
|
#include <libopencm3/usb/usbd.h>
|
||||||
#include <libopencm3/usb/dfu.h>
|
#include <libopencm3/usb/dfu.h>
|
||||||
|
|
||||||
|
|||||||
@ -20,7 +20,7 @@
|
|||||||
#include <stdlib.h>
|
#include <stdlib.h>
|
||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/systick.h>
|
#include <libopencm3/cm3/systick.h>
|
||||||
#include <libopencm3/usb/usbd.h>
|
#include <libopencm3/usb/usbd.h>
|
||||||
#include <libopencm3/usb/hid.h>
|
#include <libopencm3/usb/hid.h>
|
||||||
|
|
||||||
@ -28,7 +28,7 @@
|
|||||||
#define INCLUDE_DFU_INTERFACE
|
#define INCLUDE_DFU_INTERFACE
|
||||||
|
|
||||||
#ifdef INCLUDE_DFU_INTERFACE
|
#ifdef INCLUDE_DFU_INTERFACE
|
||||||
#include <libopencm3/stm32/f1/scb.h>
|
#include <libopencm3/cm3/scb.h>
|
||||||
#include <libopencm3/usb/dfu.h>
|
#include <libopencm3/usb/dfu.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|||||||
@ -20,7 +20,7 @@
|
|||||||
|
|
||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/exti.h>
|
#include <libopencm3/stm32/exti.h>
|
||||||
|
|
||||||
u16 exti_line_state;
|
u16 exti_line_state;
|
||||||
|
|||||||
@ -20,7 +20,7 @@
|
|||||||
|
|
||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/exti.h>
|
#include <libopencm3/stm32/exti.h>
|
||||||
|
|
||||||
u16 exti_line_state;
|
u16 exti_line_state;
|
||||||
|
|||||||
@ -20,7 +20,7 @@
|
|||||||
|
|
||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/exti.h>
|
#include <libopencm3/stm32/exti.h>
|
||||||
|
|
||||||
#define FALLING 0
|
#define FALLING 0
|
||||||
|
|||||||
@ -20,7 +20,7 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/timer.h>
|
#include <libopencm3/stm32/timer.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/exti.h>
|
#include <libopencm3/stm32/exti.h>
|
||||||
|
|
||||||
#define FALLING 0
|
#define FALLING 0
|
||||||
|
|||||||
@ -20,7 +20,7 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/timer.h>
|
#include <libopencm3/stm32/timer.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/exti.h>
|
#include <libopencm3/stm32/exti.h>
|
||||||
|
|
||||||
u16 frequency_sequence[18] = {
|
u16 frequency_sequence[18] = {
|
||||||
|
|||||||
@ -20,7 +20,7 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
|
|
||||||
void clock_setup(void)
|
void clock_setup(void)
|
||||||
{
|
{
|
||||||
|
|||||||
@ -21,8 +21,8 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/systick.h>
|
#include <libopencm3/cm3/systick.h>
|
||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
|
|
||||||
|
|||||||
@ -21,7 +21,7 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
|
|
||||||
|
|||||||
@ -21,7 +21,7 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/f1/flash.h>
|
#include <libopencm3/stm32/f1/flash.h>
|
||||||
#include <libopencm3/stm32/f1/scb.h>
|
#include <libopencm3/cm3/scb.h>
|
||||||
#include <libopencm3/usb/usbd.h>
|
#include <libopencm3/usb/usbd.h>
|
||||||
#include <libopencm3/usb/dfu.h>
|
#include <libopencm3/usb/dfu.h>
|
||||||
|
|
||||||
|
|||||||
@ -20,7 +20,7 @@
|
|||||||
#include <stdlib.h>
|
#include <stdlib.h>
|
||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/systick.h>
|
#include <libopencm3/cm3/systick.h>
|
||||||
#include <libopencm3/usb/usbd.h>
|
#include <libopencm3/usb/usbd.h>
|
||||||
#include <libopencm3/usb/hid.h>
|
#include <libopencm3/usb/hid.h>
|
||||||
|
|
||||||
@ -28,7 +28,7 @@
|
|||||||
#define INCLUDE_DFU_INTERFACE
|
#define INCLUDE_DFU_INTERFACE
|
||||||
|
|
||||||
#ifdef INCLUDE_DFU_INTERFACE
|
#ifdef INCLUDE_DFU_INTERFACE
|
||||||
#include <libopencm3/stm32/f1/scb.h>
|
#include <libopencm3/cm3/scb.h>
|
||||||
#include <libopencm3/usb/dfu.h>
|
#include <libopencm3/usb/dfu.h>
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|||||||
@ -21,7 +21,7 @@
|
|||||||
#include <libopencm3/stm32/f1/rcc.h>
|
#include <libopencm3/stm32/f1/rcc.h>
|
||||||
#include <libopencm3/stm32/f1/gpio.h>
|
#include <libopencm3/stm32/f1/gpio.h>
|
||||||
#include <libopencm3/stm32/f1/flash.h>
|
#include <libopencm3/stm32/f1/flash.h>
|
||||||
#include <libopencm3/stm32/f1/scb.h>
|
#include <libopencm3/cm3/scb.h>
|
||||||
#include <libopencm3/usb/usbd.h>
|
#include <libopencm3/usb/usbd.h>
|
||||||
#include <libopencm3/usb/dfu.h>
|
#include <libopencm3/usb/dfu.h>
|
||||||
|
|
||||||
|
|||||||
@ -23,7 +23,7 @@
|
|||||||
#include <libopencm3/stm32/f1/rtc.h>
|
#include <libopencm3/stm32/f1/rtc.h>
|
||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
|
||||||
#include <libopencm3/stm32/pwr.h>
|
#include <libopencm3/stm32/pwr.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
|
|
||||||
void clock_setup(void)
|
void clock_setup(void)
|
||||||
{
|
{
|
||||||
|
|||||||
@ -22,7 +22,7 @@
|
|||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
#include <libopencm3/stm32/spi.h>
|
#include <libopencm3/stm32/spi.h>
|
||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/f2/gpio.h>
|
#include <libopencm3/stm32/f2/gpio.h>
|
||||||
#include <libopencm3/stm32/f2/rcc.h>
|
#include <libopencm3/stm32/f2/rcc.h>
|
||||||
|
|
||||||
|
|||||||
@ -22,7 +22,7 @@
|
|||||||
#include <errno.h>
|
#include <errno.h>
|
||||||
#include <libopencm3/stm32/f2/gpio.h>
|
#include <libopencm3/stm32/f2/gpio.h>
|
||||||
#include <libopencm3/stm32/usart.h>
|
#include <libopencm3/stm32/usart.h>
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
#include <libopencm3/stm32/f2/rcc.h>
|
#include <libopencm3/stm32/f2/rcc.h>
|
||||||
|
|
||||||
void clock_setup(void)
|
void clock_setup(void)
|
||||||
|
|||||||
@ -1,21 +1,9 @@
|
|||||||
/** @defgroup STM32F_nvic_defines NVIC Defines
|
|
||||||
|
|
||||||
@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
|
|
||||||
|
|
||||||
@ingroup STM32F_defines
|
|
||||||
|
|
||||||
@version 1.0.0
|
|
||||||
|
|
||||||
@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
|
|
||||||
|
|
||||||
@date 18 August 2012
|
|
||||||
|
|
||||||
LGPL License Terms @ref lgpl_license
|
|
||||||
*/
|
|
||||||
/*
|
/*
|
||||||
* This file is part of the libopencm3 project.
|
* This file is part of the libopencm3 project.
|
||||||
*
|
*
|
||||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||||
|
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||||
|
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||||
*
|
*
|
||||||
* This library is free software: you can redistribute it and/or modify
|
* This library is free software: you can redistribute it and/or modify
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
@ -30,13 +18,27 @@ LGPL License Terms @ref lgpl_license
|
|||||||
* You should have received a copy of the GNU Lesser General Public License
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
|
/** @defgroup CM3_nvic_defines NVIC Defines
|
||||||
|
|
||||||
|
@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
|
||||||
|
|
||||||
|
@ingroup CM3_defines
|
||||||
|
|
||||||
|
@version 1.0.0
|
||||||
|
|
||||||
|
@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||||
|
|
||||||
|
@date 18 August 2012
|
||||||
|
|
||||||
|
LGPL License Terms @ref lgpl_license
|
||||||
|
*/
|
||||||
/**@{*/
|
/**@{*/
|
||||||
|
|
||||||
#ifndef LIBOPENCM3_NVIC_H
|
#ifndef LIBOPENCM3_NVIC_H
|
||||||
#define LIBOPENCM3_NVIC_H
|
#define LIBOPENCM3_NVIC_H
|
||||||
|
|
||||||
#include <libopencm3/stm32/memorymap.h>
|
|
||||||
#include <libopencm3/cm3/common.h>
|
#include <libopencm3/cm3/common.h>
|
||||||
|
#include <libopencm3/cm3/memorymap.h>
|
||||||
|
|
||||||
/* --- NVIC Registers ------------------------------------------------------ */
|
/* --- NVIC Registers ------------------------------------------------------ */
|
||||||
|
|
||||||
@ -79,9 +81,9 @@ LGPL License Terms @ref lgpl_license
|
|||||||
|
|
||||||
/* --- IRQ channel numbers-------------------------------------------------- */
|
/* --- IRQ channel numbers-------------------------------------------------- */
|
||||||
|
|
||||||
/* Cortex M3 System Interrupts */
|
/* Cortex M3 and M4 System Interrupts */
|
||||||
/** @defgroup nvic_sysint Cortex M3 System Interrupts
|
/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts
|
||||||
@ingroup STM32F_nvic_defines
|
@ingroup CM3_nvic_defines
|
||||||
|
|
||||||
IRQ numbers -3 and -6 to -9 are reserved
|
IRQ numbers -3 and -6 to -9 are reserved
|
||||||
@{*/
|
@{*/
|
||||||
@ -98,21 +100,11 @@ IRQ numbers -3 and -6 to -9 are reserved
|
|||||||
#define NVIC_SYSTICK_IRQ -1
|
#define NVIC_SYSTICK_IRQ -1
|
||||||
/**@}*/
|
/**@}*/
|
||||||
|
|
||||||
|
|
||||||
/* Note: User interrupts are family specific and are defined in a family
|
/* Note: User interrupts are family specific and are defined in a family
|
||||||
* specific header file in the corresponding subfolder.
|
* specific header file in the corresponding subfolder.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(STM32F1)
|
#include <libopencm3/dispatch/nvic.h>
|
||||||
# include <libopencm3/stm32/f1/nvic_f1.h>
|
|
||||||
#elif defined(STM32F2)
|
|
||||||
# include <libopencm3/stm32/f2/nvic_f2.h>
|
|
||||||
#elif defined(STM32F4)
|
|
||||||
# include <libopencm3/stm32/f4/nvic_f4.h>
|
|
||||||
#else
|
|
||||||
# error "stm32 family not defined."
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
/* --- NVIC functions ------------------------------------------------------ */
|
/* --- NVIC functions ------------------------------------------------------ */
|
||||||
|
|
||||||
@ -131,5 +123,3 @@ void nvic_generate_software_interrupt(u16 irqn);
|
|||||||
END_DECLS
|
END_DECLS
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
/**@}*/
|
|
||||||
|
|
||||||
@ -21,7 +21,7 @@
|
|||||||
#ifndef LIBOPENCM3_SCB_H
|
#ifndef LIBOPENCM3_SCB_H
|
||||||
#define LIBOPENCM3_SCB_H
|
#define LIBOPENCM3_SCB_H
|
||||||
|
|
||||||
#include <libopencm3/stm32/memorymap.h>
|
#include <libopencm3/cm3/memorymap.h>
|
||||||
#include <libopencm3/cm3/common.h>
|
#include <libopencm3/cm3/common.h>
|
||||||
|
|
||||||
/* --- SCB: Registers ------------------------------------------------------ */
|
/* --- SCB: Registers ------------------------------------------------------ */
|
||||||
@ -1,22 +1,8 @@
|
|||||||
/** @defgroup STM32F_systick_defines SysTick Defines
|
|
||||||
|
|
||||||
@brief <b>libopencm3 Defined Constants and Types for the STM32F SysTick </b>
|
|
||||||
|
|
||||||
@ingroup STM32F_defines
|
|
||||||
|
|
||||||
@version 1.0.0
|
|
||||||
|
|
||||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
|
||||||
|
|
||||||
@date 19 August 2012
|
|
||||||
|
|
||||||
LGPL License Terms @ref lgpl_license
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This file is part of the libopencm3 project.
|
* This file is part of the libopencm3 project.
|
||||||
*
|
*
|
||||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||||
|
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||||
*
|
*
|
||||||
* This library is free software: you can redistribute it and/or modify
|
* This library is free software: you can redistribute it and/or modify
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
@ -31,13 +17,27 @@ LGPL License Terms @ref lgpl_license
|
|||||||
* You should have received a copy of the GNU Lesser General Public License
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
|
/** @defgroup CM3_systick_defines SysTick Defines
|
||||||
|
|
||||||
|
@brief <b>libopencm3 Defined Constants and Types for the Cortex SysTick </b>
|
||||||
|
|
||||||
|
@ingroup CM3_defines
|
||||||
|
|
||||||
|
@version 1.0.0
|
||||||
|
|
||||||
|
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||||
|
|
||||||
|
@date 19 August 2012
|
||||||
|
|
||||||
|
LGPL License Terms @ref lgpl_license
|
||||||
|
*/
|
||||||
|
|
||||||
/**@{*/
|
/**@{*/
|
||||||
|
|
||||||
#ifndef LIBOPENCM3_SYSTICK_H
|
#ifndef LIBOPENCM3_SYSTICK_H
|
||||||
#define LIBOPENCM3_SYSTICK_H
|
#define LIBOPENCM3_SYSTICK_H
|
||||||
|
|
||||||
#include <libopencm3/stm32/memorymap.h>
|
#include <libopencm3/cm3/memorymap.h>
|
||||||
#include <libopencm3/cm3/common.h>
|
#include <libopencm3/cm3/common.h>
|
||||||
|
|
||||||
/* --- SYSTICK registers --------------------------------------------------- */
|
/* --- SYSTICK registers --------------------------------------------------- */
|
||||||
@ -63,7 +63,7 @@ LGPL License Terms @ref lgpl_license
|
|||||||
#define STK_CTRL_CLKSOURCE (1 << 2)
|
#define STK_CTRL_CLKSOURCE (1 << 2)
|
||||||
#define STK_CTRL_CLKSOURCE_LSB 2
|
#define STK_CTRL_CLKSOURCE_LSB 2
|
||||||
/** @defgroup systick_clksource Clock source selection
|
/** @defgroup systick_clksource Clock source selection
|
||||||
@ingroup STM32F_systick_defines
|
@ingroup CM3_systick_defines
|
||||||
|
|
||||||
@{*/
|
@{*/
|
||||||
#define STK_CTRL_CLKSOURCE_AHB_DIV8 0
|
#define STK_CTRL_CLKSOURCE_AHB_DIV8 0
|
||||||
@ -104,6 +104,8 @@ void systick_counter_enable(void);
|
|||||||
void systick_counter_disable(void);
|
void systick_counter_disable(void);
|
||||||
u8 systick_get_countflag(void);
|
u8 systick_get_countflag(void);
|
||||||
|
|
||||||
|
u32 systick_get_calib(void);
|
||||||
|
|
||||||
END_DECLS
|
END_DECLS
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
64
include/libopencm3/cm3/vector.h
Normal file
64
include/libopencm3/cm3/vector.h
Normal file
@ -0,0 +1,64 @@
|
|||||||
|
/*
|
||||||
|
* This file is part of the libopencm3 project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
|
||||||
|
*
|
||||||
|
* This library is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This library is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU Lesser General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @file
|
||||||
|
*
|
||||||
|
* Definitions for handling vector tables.
|
||||||
|
*
|
||||||
|
* This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2
|
||||||
|
* (from the EFM32 documentation at
|
||||||
|
* http://www.energymicro.com/downloads/datasheets), and was seen analogously
|
||||||
|
* in other ARM implementations' libopencm3 files.
|
||||||
|
*
|
||||||
|
* The structure of the vector table is implemented independently of the system
|
||||||
|
* vector table starting at memory position 0x0, as it can be relocated to
|
||||||
|
* other memory locations too.
|
||||||
|
*
|
||||||
|
* The exact size of a vector interrupt table depends on the number of
|
||||||
|
* interrupts IRQ_COUNT, which is defined per family.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef LIBOPENCM3_VECTOR_H
|
||||||
|
#define LIBOPENCM3_VECTOR_H
|
||||||
|
|
||||||
|
#include <libopencm3/cm3/common.h>
|
||||||
|
#include <libopencm3/cm3/nvic.h>
|
||||||
|
|
||||||
|
/** Type of an interrupt function. Only used to avoid hard-to-read function
|
||||||
|
* pointers in the efm32_vector_table_t struct. */
|
||||||
|
typedef void (*vector_table_entry_t)(void);
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */
|
||||||
|
vector_table_entry_t reset;
|
||||||
|
vector_table_entry_t nmi;
|
||||||
|
vector_table_entry_t hard_fault;
|
||||||
|
vector_table_entry_t memory_manage_fault;
|
||||||
|
vector_table_entry_t bus_fault;
|
||||||
|
vector_table_entry_t usage_fault;
|
||||||
|
vector_table_entry_t reserved_x001c[4];
|
||||||
|
vector_table_entry_t sv_call;
|
||||||
|
vector_table_entry_t debug_monitor;
|
||||||
|
vector_table_entry_t reserved_x0034;
|
||||||
|
vector_table_entry_t pend_sv;
|
||||||
|
vector_table_entry_t systick;
|
||||||
|
vector_table_entry_t irq[NVIC_IRQ_COUNT];
|
||||||
|
} vector_table_t;
|
||||||
|
|
||||||
|
#endif
|
||||||
26
include/libopencm3/dispatch/nvic.h
Normal file
26
include/libopencm3/dispatch/nvic.h
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
#if defined(STM32F1)
|
||||||
|
# include <libopencm3/stm32/f1/nvic.h>
|
||||||
|
#elif defined(STM32F2)
|
||||||
|
# include <libopencm3/stm32/f2/nvic.h>
|
||||||
|
#elif defined(STM32F4)
|
||||||
|
# include <libopencm3/stm32/f4/nvic.h>
|
||||||
|
|
||||||
|
#elif defined(TINYGECKO)
|
||||||
|
# include <libopencm3/efm32/tinygecko/nvic.h>
|
||||||
|
|
||||||
|
#elif defined(LPC13XX)
|
||||||
|
# include <libopencm3/lpc13xx/nvic.h>
|
||||||
|
#elif defined(LPC17XX)
|
||||||
|
# include <libopencm3/lpc17xx/nvic.h>
|
||||||
|
#elif defined(LPC43XX)
|
||||||
|
# include <libopencm3/lpc43xx/nvic.h>
|
||||||
|
|
||||||
|
#elif defined(LM3S)
|
||||||
|
# include <libopencm3/lm3s/nvic.h>
|
||||||
|
|
||||||
|
#else
|
||||||
|
# warning"no interrupts defined for chipset; NVIC_IRQ_COUNT = 0"
|
||||||
|
|
||||||
|
#define NVIC_IRQ_COUNT 0
|
||||||
|
|
||||||
|
#endif
|
||||||
28
include/libopencm3/efm32/tinygecko/irq.yaml
Normal file
28
include/libopencm3/efm32/tinygecko/irq.yaml
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
includeguard: LIBOPENCM3_EFM32_TINYGECKO_NVIC_H
|
||||||
|
partname_humanreadable: EFM32 Tiny Gecko series
|
||||||
|
partname_doxygen: EFM32TG
|
||||||
|
# The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1.
|
||||||
|
irqs:
|
||||||
|
- dma
|
||||||
|
- gpio_even
|
||||||
|
- timer0
|
||||||
|
- usart0_rx
|
||||||
|
- usart0_tx
|
||||||
|
- acmp01
|
||||||
|
- adc0
|
||||||
|
- dac0
|
||||||
|
- i2c0
|
||||||
|
- gpio_odd
|
||||||
|
- timer1
|
||||||
|
- usart1_rx
|
||||||
|
- usart1_tx
|
||||||
|
- lesense
|
||||||
|
- leuart0
|
||||||
|
- letimer0
|
||||||
|
- pcnt0
|
||||||
|
- rtc
|
||||||
|
- cmu
|
||||||
|
- vcmp
|
||||||
|
- lcd
|
||||||
|
- msc
|
||||||
|
- aes
|
||||||
120
include/libopencm3/lm3s/irq.yaml
Normal file
120
include/libopencm3/lm3s/irq.yaml
Normal file
@ -0,0 +1,120 @@
|
|||||||
|
includeguard: LIBOPENCM3_LM3S_NVIC_H
|
||||||
|
partname_humanreadable: LM3S series
|
||||||
|
partname_doxygen: LM3S
|
||||||
|
irqs:
|
||||||
|
0: GPIOA
|
||||||
|
1: GPIOB
|
||||||
|
2: GPIOC
|
||||||
|
3: GPIOD
|
||||||
|
4: GPIOE
|
||||||
|
5: UART0
|
||||||
|
6: UART1
|
||||||
|
7: SSI0
|
||||||
|
8: I2C0
|
||||||
|
9: PWM0_FAULT
|
||||||
|
10: PWM0_0
|
||||||
|
11: PWM0_1
|
||||||
|
12: PWM0_2
|
||||||
|
13: QEI0
|
||||||
|
14: ADC0SS0
|
||||||
|
15: ADC0SS1
|
||||||
|
16: ADC0SS2
|
||||||
|
17: ADC0SS3
|
||||||
|
18: WATCHDOG
|
||||||
|
19: TIMER0A
|
||||||
|
20: TIMER0B
|
||||||
|
21: TIMER1A
|
||||||
|
22: TIMER1B
|
||||||
|
23: TIMER2A
|
||||||
|
24: TIMER2B
|
||||||
|
25: COMP0
|
||||||
|
26: COMP1
|
||||||
|
27: COMP2
|
||||||
|
28: SYSCTL
|
||||||
|
29: FLASH
|
||||||
|
30: GPIOF
|
||||||
|
31: GPIOG
|
||||||
|
32: GPIOH
|
||||||
|
33: UART2
|
||||||
|
34: SSI1
|
||||||
|
35: TIMER3A
|
||||||
|
36: TIMER3B
|
||||||
|
37: I2C1
|
||||||
|
38: QEI1
|
||||||
|
39: CAN0
|
||||||
|
40: CAN1
|
||||||
|
41: CAN2
|
||||||
|
42: ETH
|
||||||
|
43: HIBERNATE
|
||||||
|
44: USB0
|
||||||
|
45: PWM0_3
|
||||||
|
46: UDMA
|
||||||
|
47: UDMAERR
|
||||||
|
48: ADC1SS0
|
||||||
|
49: ADC1SS1
|
||||||
|
50: ADC1SS2
|
||||||
|
51: ADC1SS3
|
||||||
|
52: I2S0
|
||||||
|
53: EPI0
|
||||||
|
54: GPIOJ
|
||||||
|
55: GPIOK
|
||||||
|
56: GPIOL
|
||||||
|
57: SSI2
|
||||||
|
58: SSI3
|
||||||
|
59: UART3
|
||||||
|
60: UART4
|
||||||
|
61: UART5
|
||||||
|
62: UART6
|
||||||
|
63: UART7
|
||||||
|
# undefined: slot 64 - 67
|
||||||
|
68: I2C2
|
||||||
|
69: I2C3
|
||||||
|
70: TIMER4A
|
||||||
|
71: TIMER4B
|
||||||
|
# undefined: slot 72 - 91
|
||||||
|
92: TIMER5A
|
||||||
|
93: TIMER5B
|
||||||
|
94: WTIMER0A
|
||||||
|
95: WTIMER0B
|
||||||
|
96: WTIMER1A
|
||||||
|
97: WTIMER1B
|
||||||
|
98: WTIMER2A
|
||||||
|
99: WTIMER2B
|
||||||
|
100: WTIMER3A
|
||||||
|
101: WTIMER3B
|
||||||
|
102: WTIMER4A
|
||||||
|
103: WTIMER4B
|
||||||
|
104: WTIMER5A
|
||||||
|
105: WTIMER5B
|
||||||
|
106: SYSEXC
|
||||||
|
107: PECI0
|
||||||
|
108: LPC0
|
||||||
|
109: I2C4
|
||||||
|
110: I2C5
|
||||||
|
111: GPIOM
|
||||||
|
112: GPION
|
||||||
|
# undefined: slot 113
|
||||||
|
114: FAN0
|
||||||
|
# undefined: slot 115
|
||||||
|
116: GPIOP0
|
||||||
|
117: GPIOP1
|
||||||
|
118: GPIOP2
|
||||||
|
119: GPIOP3
|
||||||
|
120: GPIOP4
|
||||||
|
121: GPIOP5
|
||||||
|
122: GPIOP6
|
||||||
|
123: GPIOP7
|
||||||
|
124: GPIOQ0
|
||||||
|
125: GPIOQ1
|
||||||
|
126: GPIOQ2
|
||||||
|
127: GPIOQ3
|
||||||
|
128: GPIOQ4
|
||||||
|
129: GPIOQ5
|
||||||
|
130: GPIOQ6
|
||||||
|
131: GPIOQ7
|
||||||
|
# undefined: slot 132 - 133
|
||||||
|
134: PWM1_0
|
||||||
|
135: PWM1_1
|
||||||
|
136: PWM1_2
|
||||||
|
137: PWM1_3
|
||||||
|
138: PWM1_FAULT
|
||||||
62
include/libopencm3/lpc13xx/irq.yaml
Normal file
62
include/libopencm3/lpc13xx/irq.yaml
Normal file
@ -0,0 +1,62 @@
|
|||||||
|
includeguard: LIBOPENCM3_LPC13xx_NVIC_H
|
||||||
|
partname_humanreadable: LPC 13xx series
|
||||||
|
partname_doxygen: LPC13xx
|
||||||
|
irqs:
|
||||||
|
0: pio0_0
|
||||||
|
1: pio0_1
|
||||||
|
2: pio0_2
|
||||||
|
3: pio0_3
|
||||||
|
4: pio0_4
|
||||||
|
5: pio0_5
|
||||||
|
6: pio0_6
|
||||||
|
7: pio0_7
|
||||||
|
8: pio0_8
|
||||||
|
9: pio0_9
|
||||||
|
10: pio0_10
|
||||||
|
11: pio0_11
|
||||||
|
12: pio1_0
|
||||||
|
13: pio1_1
|
||||||
|
14: pio1_2
|
||||||
|
15: pio1_3
|
||||||
|
16: pio1_4
|
||||||
|
17: pio1_5
|
||||||
|
18: pio1_6
|
||||||
|
19: pio1_7
|
||||||
|
20: pio1_8
|
||||||
|
21: pio1_9
|
||||||
|
22: pio1_10
|
||||||
|
23: pio1_11
|
||||||
|
24: pio2_0
|
||||||
|
25: pio2_1
|
||||||
|
26: pio2_2
|
||||||
|
27: pio2_3
|
||||||
|
28: pio2_4
|
||||||
|
29: pio2_5
|
||||||
|
30: pio2_6
|
||||||
|
31: pio2_7
|
||||||
|
32: pio2_8
|
||||||
|
33: pio2_9
|
||||||
|
34: pio2_10
|
||||||
|
35: pio2_11
|
||||||
|
36: pio3_0
|
||||||
|
37: pio3_1
|
||||||
|
38: pio3_2
|
||||||
|
39: pio3_3
|
||||||
|
40: i2c0
|
||||||
|
41: ct16b0
|
||||||
|
42: ct16b1
|
||||||
|
43: ct32b0
|
||||||
|
44: ct32b1
|
||||||
|
45: ssp0
|
||||||
|
46: uart
|
||||||
|
47: usb
|
||||||
|
48: usb_fiq
|
||||||
|
49: adc
|
||||||
|
50: wdt
|
||||||
|
51: bod
|
||||||
|
# 52: reserved
|
||||||
|
53: pio3
|
||||||
|
54: pio2
|
||||||
|
55: pio1
|
||||||
|
56: pio0
|
||||||
|
56: ssp1
|
||||||
39
include/libopencm3/lpc17xx/irq.yaml
Normal file
39
include/libopencm3/lpc17xx/irq.yaml
Normal file
@ -0,0 +1,39 @@
|
|||||||
|
includeguard: LIBOPENCM3_LPC17xx_NVIC_H
|
||||||
|
partname_humanreadable: LPC 17xx series
|
||||||
|
partname_doxygen: LPC17xx
|
||||||
|
irqs:
|
||||||
|
0: wdt
|
||||||
|
1: timer0
|
||||||
|
2: timer1
|
||||||
|
3: timer2
|
||||||
|
4: timer3
|
||||||
|
5: uart0
|
||||||
|
6: uart1
|
||||||
|
7: uart2
|
||||||
|
8: uart3
|
||||||
|
9: pwm
|
||||||
|
10: i2c0
|
||||||
|
11: i2c1
|
||||||
|
12: i2c2
|
||||||
|
13: spi
|
||||||
|
14: ssp0
|
||||||
|
15: ssp1
|
||||||
|
16: pll0
|
||||||
|
17: rtc
|
||||||
|
18: eint0
|
||||||
|
19: eint1
|
||||||
|
20: eint2
|
||||||
|
21: eint3
|
||||||
|
22: adc
|
||||||
|
23: bod
|
||||||
|
24: usb
|
||||||
|
25: can
|
||||||
|
26: gpdma
|
||||||
|
27: i2s
|
||||||
|
28: ethernet
|
||||||
|
29: rit
|
||||||
|
30: motor_pwm
|
||||||
|
31: qei
|
||||||
|
32: pll1
|
||||||
|
33: usb_act
|
||||||
|
34: can_act
|
||||||
55
include/libopencm3/lpc43xx/irq.yaml
Normal file
55
include/libopencm3/lpc43xx/irq.yaml
Normal file
@ -0,0 +1,55 @@
|
|||||||
|
includeguard: LIBOPENCM3_LPC43xx_NVIC_H
|
||||||
|
partname_humanreadable: LPC 43xx series
|
||||||
|
partname_doxygen: LPC43xx
|
||||||
|
irqs:
|
||||||
|
0: dac
|
||||||
|
1: m0core
|
||||||
|
2: dma
|
||||||
|
# reserved: 3, 4
|
||||||
|
5: ethernet
|
||||||
|
6: sdio
|
||||||
|
7: lcd
|
||||||
|
8: usb0
|
||||||
|
9: usb1
|
||||||
|
10: sct
|
||||||
|
11: ritimer
|
||||||
|
12: timer0
|
||||||
|
13: timer1
|
||||||
|
14: timer2
|
||||||
|
15: timer3
|
||||||
|
16: mcpwm
|
||||||
|
17: adc0
|
||||||
|
18: i2c0
|
||||||
|
19: i2c1
|
||||||
|
20: spi
|
||||||
|
21: adc1
|
||||||
|
22: ssp0
|
||||||
|
23: ssp1
|
||||||
|
24: usart0
|
||||||
|
25: uart1
|
||||||
|
26: usart2
|
||||||
|
27: usart3
|
||||||
|
28: i2s0
|
||||||
|
29: i2s1
|
||||||
|
30: spifi
|
||||||
|
31: sgpio
|
||||||
|
32: pin_int0
|
||||||
|
33: pin_int1
|
||||||
|
34: pin_int2
|
||||||
|
35: pin_int3
|
||||||
|
36: pin_int4
|
||||||
|
37: pin_int5
|
||||||
|
38: pin_int6
|
||||||
|
39: pin_int7
|
||||||
|
40: gint0
|
||||||
|
41: gint1
|
||||||
|
42: eventrouter
|
||||||
|
43: c_can1
|
||||||
|
# reserved: 44, 45
|
||||||
|
46: atimer
|
||||||
|
47: rtc
|
||||||
|
# reserved: 48
|
||||||
|
49: wwdt
|
||||||
|
# reserved: 50
|
||||||
|
51: c_can0
|
||||||
|
52: qei
|
||||||
@ -1,151 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
|
||||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
|
||||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef LPC43XX_NVIC_H
|
|
||||||
#define LPC43XX_NVIC_H
|
|
||||||
|
|
||||||
#include <libopencm3/cm3/common.h>
|
|
||||||
#include <libopencm3/cm3/memorymap.h>
|
|
||||||
#include <libopencm3/lpc43xx/memorymap.h>
|
|
||||||
|
|
||||||
/* --- NVIC Registers ------------------------------------------------------ */
|
|
||||||
|
|
||||||
/* ISER: Interrupt Set Enable Registers */
|
|
||||||
/* Note: 8 32bit Registers */
|
|
||||||
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
|
|
||||||
|
|
||||||
/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
|
|
||||||
|
|
||||||
/* ICER: Interrupt Clear Enable Registers */
|
|
||||||
/* Note: 8 32bit Registers */
|
|
||||||
#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
|
|
||||||
|
|
||||||
/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
|
|
||||||
|
|
||||||
/* ISPR: Interrupt Set Pending Registers */
|
|
||||||
/* Note: 8 32bit Registers */
|
|
||||||
#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
|
|
||||||
|
|
||||||
/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
|
|
||||||
|
|
||||||
/* ICPR: Interrupt Clear Pending Registers */
|
|
||||||
/* Note: 8 32bit Registers */
|
|
||||||
#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
|
|
||||||
|
|
||||||
/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
|
|
||||||
|
|
||||||
/* IABR: Interrupt Active Bit Register */
|
|
||||||
/* Note: 8 32bit Registers */
|
|
||||||
#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
|
|
||||||
|
|
||||||
/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
|
|
||||||
|
|
||||||
/* IPR: Interrupt Priority Registers */
|
|
||||||
/* Note: 240 8bit Registers */
|
|
||||||
#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
|
|
||||||
|
|
||||||
/* STIR: Software Trigger Interrupt Register */
|
|
||||||
#define NVIC_STIR MMIO32(STIR_BASE)
|
|
||||||
|
|
||||||
/* --- IRQ channel numbers-------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Cortex M4 System Interrupts */
|
|
||||||
#define NVIC_NMI_IRQ -14
|
|
||||||
#define NVIC_HARD_FAULT_IRQ -13
|
|
||||||
#define NVIC_MEM_MANAGE_IRQ -12
|
|
||||||
#define NVIC_BUS_FAULT_IRQ -11
|
|
||||||
#define NVIC_USAGE_FAULT_IRQ -10
|
|
||||||
/* irq numbers -6 to -9 are reserved */
|
|
||||||
#define NVIC_SV_CALL_IRQ -5
|
|
||||||
#define DEBUG_MONITOR_IRQ -4
|
|
||||||
/* irq number -3 reserved */
|
|
||||||
#define NVIC_PENDSV_IRQ -2
|
|
||||||
#define NVIC_SYSTICK_IRQ -1
|
|
||||||
|
|
||||||
/* LPC43xx M4 specific user interrupts */
|
|
||||||
#define NVIC_M4_DAC_IRQ 0
|
|
||||||
#define NVIC_M4_M0CORE_IRQ 1
|
|
||||||
#define NVIC_M4_DMA_IRQ 2
|
|
||||||
#define NVIC_M4_ETHERNET_IRQ 5
|
|
||||||
#define NVIC_M4_SDIO_IRQ 6
|
|
||||||
#define NVIC_M4_LCD_IRQ 7
|
|
||||||
#define NVIC_M4_USB0_IRQ 8
|
|
||||||
#define NVIC_M4_USB1_IRQ 9
|
|
||||||
#define NVIC_M4_SCT_IRQ 10
|
|
||||||
#define NVIC_M4_RITIMER_IRQ 11
|
|
||||||
#define NVIC_M4_TIMER0_IRQ 12
|
|
||||||
#define NVIC_M4_TIMER1_IRQ 13
|
|
||||||
#define NVIC_M4_TIMER2_IRQ 14
|
|
||||||
#define NVIC_M4_TIMER3_IRQ 15
|
|
||||||
#define NVIC_M4_MCPWM_IRQ 16
|
|
||||||
#define NVIC_M4_ADC0_IRQ 17
|
|
||||||
#define NVIC_M4_I2C0_IRQ 18
|
|
||||||
#define NVIC_M4_I2C1_IRQ 19
|
|
||||||
#define NVIC_M4_SPI_IRQ 20
|
|
||||||
#define NVIC_M4_ADC1_IRQ 21
|
|
||||||
#define NVIC_M4_SSP0_IRQ 22
|
|
||||||
#define NVIC_M4_SSP1_IRQ 23
|
|
||||||
#define NVIC_M4_USART0_IRQ 24
|
|
||||||
#define NVIC_M4_UART1_IRQ 25
|
|
||||||
#define NVIC_M4_USART2_IRQ 26
|
|
||||||
#define NVIC_M4_USART3_IRQ 27
|
|
||||||
#define NVIC_M4_I2S0_IRQ 28
|
|
||||||
#define NVIC_M4_I2S1_IRQ 29
|
|
||||||
#define NVIC_M4_SPIFI_IRQ 30
|
|
||||||
#define NVIC_M4_SGPIO_IRQ 31
|
|
||||||
#define NVIC_M4_PIN_INT0_IRQ 32
|
|
||||||
#define NVIC_M4_PIN_INT1_IRQ 33
|
|
||||||
#define NVIC_M4_PIN_INT2_IRQ 34
|
|
||||||
#define NVIC_M4_PIN_INT3_IRQ 35
|
|
||||||
#define NVIC_M4_PIN_INT4_IRQ 36
|
|
||||||
#define NVIC_M4_PIN_INT5_IRQ 37
|
|
||||||
#define NVIC_M4_PIN_INT6_IRQ 38
|
|
||||||
#define NVIC_M4_PIN_INT7_IRQ 39
|
|
||||||
#define NVIC_M4_GINT0_IRQ 40
|
|
||||||
#define NVIC_M4_GINT1_IRQ 41
|
|
||||||
#define NVIC_M4_EVENTROUTER_IRQ 42
|
|
||||||
#define NVIC_M4_C_CAN1_IRQ 43
|
|
||||||
#define NVIC_M4_ATIMER_IRQ 46
|
|
||||||
#define NVIC_M4_RTC_IRQ 47
|
|
||||||
#define NVIC_M4_WWDT_IRQ 49
|
|
||||||
#define NVIC_M4_C_CAN0_IRQ 51
|
|
||||||
#define NVIC_M4_QEI_IRQ 52
|
|
||||||
|
|
||||||
/* LPC43xx M0 specific user interrupts */
|
|
||||||
//TODO
|
|
||||||
|
|
||||||
/* --- NVIC functions ------------------------------------------------------ */
|
|
||||||
|
|
||||||
BEGIN_DECLS
|
|
||||||
|
|
||||||
void nvic_enable_irq(u8 irqn);
|
|
||||||
void nvic_disable_irq(u8 irqn);
|
|
||||||
u8 nvic_get_pending_irq(u8 irqn);
|
|
||||||
void nvic_set_pending_irq(u8 irqn);
|
|
||||||
void nvic_clear_pending_irq(u8 irqn);
|
|
||||||
u8 nvic_get_active_irq(u8 irqn);
|
|
||||||
u8 nvic_get_irq_enabled(u8 irqn);
|
|
||||||
void nvic_set_priority(u8 irqn, u8 priority);
|
|
||||||
void nvic_generate_software_interrupt(u8 irqn);
|
|
||||||
|
|
||||||
END_DECLS
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,88 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
|
||||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef LIBOPENCM3_SYSTICK_H
|
|
||||||
#define LIBOPENCM3_SYSTICK_H
|
|
||||||
|
|
||||||
#include <libopencm3/lpc43xx/memorymap.h>
|
|
||||||
#include <libopencm3/cm3/memorymap.h>
|
|
||||||
#include <libopencm3/cm3/common.h>
|
|
||||||
|
|
||||||
/* --- SYSTICK registers --------------------------------------------------- */
|
|
||||||
/* See also libopencm3\cm3\scs.h for details on SysTicks registers */
|
|
||||||
|
|
||||||
/* Control and status register (STK_CTRL) */
|
|
||||||
#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00)
|
|
||||||
|
|
||||||
/* reload value register (STK_LOAD) */
|
|
||||||
#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04)
|
|
||||||
|
|
||||||
/* current value register (STK_VAL) */
|
|
||||||
#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08)
|
|
||||||
|
|
||||||
/* calibration value register (STK_CALIB) */
|
|
||||||
#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
|
|
||||||
|
|
||||||
/* --- STK_CTRL values ----------------------------------------------------- */
|
|
||||||
/* Bits [31:17] Reserved, must be kept cleared. */
|
|
||||||
/* COUNTFLAG: */
|
|
||||||
#define STK_CTRL_COUNTFLAG (1 << 16)
|
|
||||||
/* Bits [15:3] Reserved, must be kept cleared. */
|
|
||||||
/* CLKSOURCE: Clock source selection */
|
|
||||||
#define STK_CTRL_CLKSOURCE (1 << 2)
|
|
||||||
/* TICKINT: SysTick exception request enable */
|
|
||||||
#define STK_CTRL_TICKINT (1 << 1)
|
|
||||||
/* ENABLE: Counter enable */
|
|
||||||
#define STK_CTRL_ENABLE (1 << 0)
|
|
||||||
|
|
||||||
/* --- STK_LOAD values ----------------------------------------------------- */
|
|
||||||
/* Bits [31:24] Reserved, must be kept cleared. */
|
|
||||||
/* RELOAD[23:0]: RELOAD value */
|
|
||||||
|
|
||||||
/* --- STK_VAL values ------------------------------------------------------ */
|
|
||||||
/* Bits [31:24] Reserved, must be kept cleared. */
|
|
||||||
/* CURRENT[23:0]: Current counter value */
|
|
||||||
|
|
||||||
/* --- STK_CALIB values ---------------------------------------------------- */
|
|
||||||
/* NOREF: NOREF flag */
|
|
||||||
#define STK_CALIB_NOREF (1 << 31)
|
|
||||||
/* SKEW: SKEW flag */
|
|
||||||
#define STK_CALIB_SKEW (1 << 30)
|
|
||||||
/* Bits [29:24] Reserved, must be kept cleared. */
|
|
||||||
/* TENMS[23:0]: Calibration value */
|
|
||||||
|
|
||||||
/* --- Function Prototypes ------------------------------------------------- */
|
|
||||||
|
|
||||||
BEGIN_DECLS
|
|
||||||
|
|
||||||
void systick_set_reload(u32 value);
|
|
||||||
u32 systick_get_value(void);
|
|
||||||
void systick_set_clocksource(u8 clocksource);
|
|
||||||
void systick_interrupt_enable(void);
|
|
||||||
void systick_interrupt_disable(void);
|
|
||||||
void systick_counter_enable(void);
|
|
||||||
void systick_counter_disable(void);
|
|
||||||
u8 systick_get_countflag(void);
|
|
||||||
|
|
||||||
u32 systick_get_calib(void);
|
|
||||||
|
|
||||||
END_DECLS
|
|
||||||
|
|
||||||
#endif
|
|
||||||
72
include/libopencm3/stm32/f1/irq.yaml
Normal file
72
include/libopencm3/stm32/f1/irq.yaml
Normal file
@ -0,0 +1,72 @@
|
|||||||
|
includeguard: LIBOPENCM3_STM32_F1_NVIC_H
|
||||||
|
partname_humanreadable: STM32 F1 series
|
||||||
|
partname_doxygen: STM32F1
|
||||||
|
irqs:
|
||||||
|
- wwdg
|
||||||
|
- pvd
|
||||||
|
- tamper
|
||||||
|
- rtc
|
||||||
|
- flash
|
||||||
|
- rcc
|
||||||
|
- exti0
|
||||||
|
- exti1
|
||||||
|
- exti2
|
||||||
|
- exti3
|
||||||
|
- exti4
|
||||||
|
- dma1_channel1
|
||||||
|
- dma1_channel2
|
||||||
|
- dma1_channel3
|
||||||
|
- dma1_channel4
|
||||||
|
- dma1_channel5
|
||||||
|
- dma1_channel6
|
||||||
|
- dma1_channel7
|
||||||
|
- adc1_2
|
||||||
|
- usb_hp_can_tx
|
||||||
|
- usb_lp_can_rx0
|
||||||
|
- can_rx1
|
||||||
|
- can_sce
|
||||||
|
- exti9_5
|
||||||
|
- tim1_brk
|
||||||
|
- tim1_up
|
||||||
|
- tim1_trg_com
|
||||||
|
- tim1_cc
|
||||||
|
- tim2
|
||||||
|
- tim3
|
||||||
|
- tim4
|
||||||
|
- i2c1_ev
|
||||||
|
- i2c1_er
|
||||||
|
- i2c2_ev
|
||||||
|
- i2c2_er
|
||||||
|
- spi1
|
||||||
|
- spi2
|
||||||
|
- usart1
|
||||||
|
- usart2
|
||||||
|
- usart3
|
||||||
|
- exti15_10
|
||||||
|
- rtc_alarm
|
||||||
|
- usb_wakeup
|
||||||
|
- tim8_brk
|
||||||
|
- tim8_up
|
||||||
|
- tim8_trg_com
|
||||||
|
- tim8_cc
|
||||||
|
- adc3
|
||||||
|
- fsmc
|
||||||
|
- sdio
|
||||||
|
- tim5
|
||||||
|
- spi3
|
||||||
|
- uart4
|
||||||
|
- uart5
|
||||||
|
- tim6
|
||||||
|
- tim7
|
||||||
|
- dma2_channel1
|
||||||
|
- dma2_channel2
|
||||||
|
- dma2_channel3
|
||||||
|
- dma2_channel4_5
|
||||||
|
- dma2_channel5
|
||||||
|
- eth
|
||||||
|
- eth_wkup
|
||||||
|
- can2_tx
|
||||||
|
- can2_rx0
|
||||||
|
- can2_rx1
|
||||||
|
- can2_sce
|
||||||
|
- otg_fs
|
||||||
@ -1,114 +0,0 @@
|
|||||||
/** @brief <b>Defined Constants and Types for the STM32F1xx Nested Vectored Interrupt Controller</b>
|
|
||||||
|
|
||||||
@version 1.0.0
|
|
||||||
|
|
||||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
|
||||||
|
|
||||||
@date 18 August 2012
|
|
||||||
|
|
||||||
LGPL License Terms @ref lgpl_license
|
|
||||||
*/
|
|
||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef LIBOPENCM3_NVIC_F1_H
|
|
||||||
#define LIBOPENCM3_NVIC_F1_H
|
|
||||||
|
|
||||||
/* --- IRQ channel numbers-------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Note: These F1 specific user interrupt definitions supplement the
|
|
||||||
* general NVIC definitions in ../nvic.h
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* User Interrupts */
|
|
||||||
/** @defgroup nvic_stm32f1_userint STM32F1xx User Interrupts
|
|
||||||
@ingroup STM32F_nvic_defines
|
|
||||||
|
|
||||||
@{*/
|
|
||||||
#define NVIC_WWDG_IRQ 0
|
|
||||||
#define NVIC_PVD_IRQ 1
|
|
||||||
#define NVIC_TAMPER_IRQ 2
|
|
||||||
#define NVIC_RTC_IRQ 3
|
|
||||||
#define NVIC_FLASH_IRQ 4
|
|
||||||
#define NVIC_RCC_IRQ 5
|
|
||||||
#define NVIC_EXTI0_IRQ 6
|
|
||||||
#define NVIC_EXTI1_IRQ 7
|
|
||||||
#define NVIC_EXTI2_IRQ 8
|
|
||||||
#define NVIC_EXTI3_IRQ 9
|
|
||||||
#define NVIC_EXTI4_IRQ 10
|
|
||||||
#define NVIC_DMA1_CHANNEL1_IRQ 11
|
|
||||||
#define NVIC_DMA1_CHANNEL2_IRQ 12
|
|
||||||
#define NVIC_DMA1_CHANNEL3_IRQ 13
|
|
||||||
#define NVIC_DMA1_CHANNEL4_IRQ 14
|
|
||||||
#define NVIC_DMA1_CHANNEL5_IRQ 15
|
|
||||||
#define NVIC_DMA1_CHANNEL6_IRQ 16
|
|
||||||
#define NVIC_DMA1_CHANNEL7_IRQ 17
|
|
||||||
#define NVIC_ADC1_2_IRQ 18
|
|
||||||
#define NVIC_USB_HP_CAN_TX_IRQ 19
|
|
||||||
#define NVIC_USB_LP_CAN_RX0_IRQ 20
|
|
||||||
#define NVIC_CAN_RX1_IRQ 21
|
|
||||||
#define NVIC_CAN_SCE_IRQ 22
|
|
||||||
#define NVIC_EXTI9_5_IRQ 23
|
|
||||||
#define NVIC_TIM1_BRK_IRQ 24
|
|
||||||
#define NVIC_TIM1_UP_IRQ 25
|
|
||||||
#define NVIC_TIM1_TRG_COM_IRQ 26
|
|
||||||
#define NVIC_TIM1_CC_IRQ 27
|
|
||||||
#define NVIC_TIM2_IRQ 28
|
|
||||||
#define NVIC_TIM3_IRQ 29
|
|
||||||
#define NVIC_TIM4_IRQ 30
|
|
||||||
#define NVIC_I2C1_EV_IRQ 31
|
|
||||||
#define NVIC_I2C1_ER_IRQ 32
|
|
||||||
#define NVIC_I2C2_EV_IRQ 33
|
|
||||||
#define NVIC_I2C2_ER_IRQ 34
|
|
||||||
#define NVIC_SPI1_IRQ 35
|
|
||||||
#define NVIC_SPI2_IRQ 36
|
|
||||||
#define NVIC_USART1_IRQ 37
|
|
||||||
#define NVIC_USART2_IRQ 38
|
|
||||||
#define NVIC_USART3_IRQ 39
|
|
||||||
#define NVIC_EXTI15_10_IRQ 40
|
|
||||||
#define NVIC_RTC_ALARM_IRQ 41
|
|
||||||
#define NVIC_USB_WAKEUP_IRQ 42
|
|
||||||
#define NVIC_TIM8_BRK_IRQ 43
|
|
||||||
#define NVIC_TIM8_UP_IRQ 44
|
|
||||||
#define NVIC_TIM8_TRG_COM_IRQ 45
|
|
||||||
#define NVIC_TIM8_CC_IRQ 46
|
|
||||||
#define NVIC_ADC3_IRQ 47
|
|
||||||
#define NVIC_FSMC_IRQ 48
|
|
||||||
#define NVIC_SDIO_IRQ 49
|
|
||||||
#define NVIC_TIM5_IRQ 50
|
|
||||||
#define NVIC_SPI3_IRQ 51
|
|
||||||
#define NVIC_UART4_IRQ 52
|
|
||||||
#define NVIC_UART5_IRQ 53
|
|
||||||
#define NVIC_TIM6_IRQ 54
|
|
||||||
#define NVIC_TIM7_IRQ 55
|
|
||||||
#define NVIC_DMA2_CHANNEL1_IRQ 56
|
|
||||||
#define NVIC_DMA2_CHANNEL2_IRQ 57
|
|
||||||
#define NVIC_DMA2_CHANNEL3_IRQ 58
|
|
||||||
#define NVIC_DMA2_CHANNEL4_5_IRQ 59
|
|
||||||
#define NVIC_DMA2_CHANNEL5_IRQ 60
|
|
||||||
#define NVIC_ETH_IRQ 61
|
|
||||||
#define NVIC_ETH_WKUP_IRQ 62
|
|
||||||
#define NVIC_CAN2_TX_IRQ 63
|
|
||||||
#define NVIC_CAN2_RX0_IRQ 64
|
|
||||||
#define NVIC_CAN2_RX1_IRQ 65
|
|
||||||
#define NVIC_CAN2_SCE_IRQ 66
|
|
||||||
#define NVIC_OTG_FS_IRQ 67
|
|
||||||
/**@}*/
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,307 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
|
||||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef LIBOPENCM3_SCB_H
|
|
||||||
#define LIBOPENCM3_SCB_H
|
|
||||||
|
|
||||||
#include <libopencm3/stm32/memorymap.h>
|
|
||||||
#include <libopencm3/cm3/common.h>
|
|
||||||
|
|
||||||
/* --- SCB: Registers ------------------------------------------------------ */
|
|
||||||
|
|
||||||
/* CPUID: CPUID base register */
|
|
||||||
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
|
|
||||||
|
|
||||||
/* ICSR: Interrupt Control State Register */
|
|
||||||
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
|
|
||||||
|
|
||||||
/* VTOR: Vector Table Offset Register */
|
|
||||||
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
|
|
||||||
|
|
||||||
/* AIRCR: Application Interrupt and Reset Control Register */
|
|
||||||
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
|
|
||||||
|
|
||||||
/* SCR: System Control Register */
|
|
||||||
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
|
|
||||||
|
|
||||||
/* CCR: Configuration Control Register */
|
|
||||||
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
|
|
||||||
|
|
||||||
/* SHP: System Handler Priority Registers */
|
|
||||||
/* Note: 12 8bit registers */
|
|
||||||
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
|
|
||||||
#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
|
|
||||||
#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
|
|
||||||
#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
|
|
||||||
|
|
||||||
/* SHCSR: System Handler Control and State Register */
|
|
||||||
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
|
|
||||||
|
|
||||||
/* CFSR: Configurable Fault Status Registers */
|
|
||||||
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
|
|
||||||
|
|
||||||
/* HFSR: Hard Fault Status Register */
|
|
||||||
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
|
|
||||||
|
|
||||||
/* DFSR: Debug Fault Status Register */
|
|
||||||
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
|
|
||||||
|
|
||||||
/* MMFAR: Memory Manage Fault Address Register */
|
|
||||||
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
|
|
||||||
|
|
||||||
/* BFAR: Bus Fault Address Register */
|
|
||||||
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
|
|
||||||
|
|
||||||
/* AFSR: Auxiliary Fault Status Register */
|
|
||||||
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
|
|
||||||
|
|
||||||
/* --- SCB values ---------------------------------------------------------- */
|
|
||||||
|
|
||||||
/* --- SCB_CPUID values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Implementer[31:24]: Implementer code */
|
|
||||||
#define SCP_CPUID_IMPLEMENTER_LSB 24
|
|
||||||
/* Variant[23:20]: Variant number */
|
|
||||||
#define SCP_CPUID_VARIANT_LSB 20
|
|
||||||
/* Constant[19:16]: Reads as 0xF */
|
|
||||||
#define SCP_CPUID_CONSTANT_LSB 16
|
|
||||||
/* PartNo[15:4]: Part number of the processor */
|
|
||||||
#define SCP_CPUID_PARTNO_LSB 4
|
|
||||||
/* Revision[3:0]: Revision number */
|
|
||||||
#define SCP_CPUID_REVISION_LSB 0
|
|
||||||
|
|
||||||
/* --- SCB_ICSR values ----------------------------------------------------- */
|
|
||||||
|
|
||||||
/* NMIPENDSET: NMI set-pending bit */
|
|
||||||
#define SCB_ICSR_NMIPENDSET (1 << 31)
|
|
||||||
/* Bits [30:29]: reserved - must be kept cleared */
|
|
||||||
/* PENDSVSET: PendSV set-pending bit */
|
|
||||||
#define SCB_ICSR_PENDSVSET (1 << 28)
|
|
||||||
/* PENDSVCLR: PendSV clear-pending bit */
|
|
||||||
#define SCB_ICSR_PENDSVCLR (1 << 27)
|
|
||||||
/* PENDSTSET: SysTick exception set-pending bit */
|
|
||||||
#define SCB_ICSR_PENDSTSET (1 << 26)
|
|
||||||
/* PENDSTCLR: SysTick exception clear-pending bit */
|
|
||||||
#define SCB_ICSR_PENDSTCLR (1 << 25)
|
|
||||||
/* Bit 24: reserved - must be kept cleared */
|
|
||||||
/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
|
|
||||||
/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
|
|
||||||
#define SCB_ICSR_ISRPENDING (1 << 22)
|
|
||||||
/* VECTPENDING[21:12] Pending vector */
|
|
||||||
#define SCB_ICSR_VECTPENDING_LSB 12
|
|
||||||
/* RETOBASE: Return to base level */
|
|
||||||
#define SCB_ICSR_RETOBASE (1 << 11)
|
|
||||||
/* Bits [10:9]: reserved - must be kept cleared */
|
|
||||||
/* VECTACTIVE[8:0] Active vector */
|
|
||||||
#define SCB_ICSR_VECTACTIVE_LSB 0
|
|
||||||
|
|
||||||
/* --- SCB_VTOR values ----------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Bits [31:30]: reserved - must be kept cleared */
|
|
||||||
/* TBLOFF[29:9]: Vector table base offset field */
|
|
||||||
#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
|
|
||||||
|
|
||||||
/* --- SCB_AIRCR values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
|
|
||||||
#define SCB_AIRCR_VECTKEYSTAT_LSB 16
|
|
||||||
#define SCB_AIRCR_VECTKEY 0x05FA0000
|
|
||||||
/* ENDIANESS Data endianness bit */
|
|
||||||
#define SCB_AIRCR_ENDIANESS (1 << 15)
|
|
||||||
/* Bits [14:11]: reserved - must be kept cleared */
|
|
||||||
/* PRIGROUP[10:8]: Interrupt priority grouping field */
|
|
||||||
#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_SHIFT 8
|
|
||||||
/* Bits [7:3]: reserved - must be kept cleared */
|
|
||||||
/* SYSRESETREQ System reset request */
|
|
||||||
#define SCB_AIRCR_SYSRESETREQ (1 << 2)
|
|
||||||
/* VECTCLRACTIVE */
|
|
||||||
#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
|
|
||||||
/* VECTRESET */
|
|
||||||
#define SCB_AIRCR_VECTRESET (1 << 0)
|
|
||||||
|
|
||||||
/* --- SCB_SCR values ------------------------------------------------------ */
|
|
||||||
|
|
||||||
/* Bits [31:5]: reserved - must be kept cleared */
|
|
||||||
/* SEVEONPEND Send Event on Pending bit */
|
|
||||||
#define SCB_SCR_SEVEONPEND (1 << 4)
|
|
||||||
/* Bit 3: reserved - must be kept cleared */
|
|
||||||
/* SLEEPDEEP */
|
|
||||||
#define SCB_SCR_SLEEPDEEP (1 << 2)
|
|
||||||
/* SLEEPONEXIT */
|
|
||||||
#define SCB_SCR_SLEEPONEXIT (1 << 1)
|
|
||||||
/* Bit 0: reserved - must be kept cleared */
|
|
||||||
|
|
||||||
/* --- SCB_CCR values ------------------------------------------------------ */
|
|
||||||
|
|
||||||
/* Bits [31:10]: reserved - must be kept cleared */
|
|
||||||
/* STKALIGN */
|
|
||||||
#define SCB_CCR_STKALIGN (1 << 9)
|
|
||||||
/* BFHFNMIGN */
|
|
||||||
#define SCB_CCR_BFHFNMIGN (1 << 8)
|
|
||||||
/* Bits [7:5]: reserved - must be kept cleared */
|
|
||||||
/* DIV_0_TRP */
|
|
||||||
#define SCB_CCR_DIV_0_TRP (1 << 4)
|
|
||||||
/* UNALIGN_TRP */
|
|
||||||
#define SCB_CCR_UNALIGN_TRP (1 << 3)
|
|
||||||
/* Bit 2: reserved - must be kept cleared */
|
|
||||||
/* USERSETMPEND */
|
|
||||||
#define SCB_CCR_USERSETMPEND (1 << 1)
|
|
||||||
/* NONBASETHRDENA */
|
|
||||||
#define SCB_CCR_NONBASETHRDENA (1 << 0)
|
|
||||||
|
|
||||||
/* --- SCB_SHPR1 values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Bits [31:24]: reserved - must be kept cleared */
|
|
||||||
/* PRI_6[23:16]: Priority of system handler 6, usage fault */
|
|
||||||
#define SCB_SHPR1_PRI_6_LSB 16
|
|
||||||
/* PRI_5[15:8]: Priority of system handler 5, bus fault */
|
|
||||||
#define SCB_SHPR1_PRI_5_LSB 8
|
|
||||||
/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
|
|
||||||
#define SCB_SHPR1_PRI_4_LSB 0
|
|
||||||
|
|
||||||
/* --- SCB_SHPR2 values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* PRI_11[31:24]: Priority of system handler 11, SVCall */
|
|
||||||
#define SCB_SHPR2_PRI_11_LSB 24
|
|
||||||
/* Bits [23:0]: reserved - must be kept cleared */
|
|
||||||
|
|
||||||
/* --- SCB_SHPR3 values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
|
|
||||||
#define SCB_SHPR3_PRI_15_LSB 24
|
|
||||||
/* PRI_14[23:16]: Priority of system handler 14, PendSV */
|
|
||||||
#define SCB_SHPR3_PRI_14_LSB 16
|
|
||||||
/* Bits [15:0]: reserved - must be kept cleared */
|
|
||||||
|
|
||||||
/* --- SCB_SHCSR values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Bits [31:19]: reserved - must be kept cleared */
|
|
||||||
/* USGFAULTENA: Usage fault enable */
|
|
||||||
#define SCB_SHCSR_USGFAULTENA (1 << 18)
|
|
||||||
/* BUSFAULTENA: Bus fault enable */
|
|
||||||
#define SCB_SHCSR_BUSFAULTENA (1 << 17)
|
|
||||||
/* MEMFAULTENA: Memory management fault enable */
|
|
||||||
#define SCB_SHCSR_MEMFAULTENA (1 << 16)
|
|
||||||
/* SVCALLPENDED: SVC call pending */
|
|
||||||
#define SCB_SHCSR_SVCALLPENDED (1 << 15)
|
|
||||||
/* BUSFAULTPENDED: Bus fault exception pending */
|
|
||||||
#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
|
|
||||||
/* MEMFAULTPENDED: Memory management fault exception pending */
|
|
||||||
#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
|
|
||||||
/* USGFAULTPENDED: Usage fault exception pending */
|
|
||||||
#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
|
|
||||||
/* SYSTICKACT: SysTick exception active */
|
|
||||||
#define SCB_SHCSR_SYSTICKACT (1 << 11)
|
|
||||||
/* PENDSVACT: PendSV exception active */
|
|
||||||
#define SCB_SHCSR_PENDSVACT (1 << 10)
|
|
||||||
/* Bit 9: reserved - must be kept cleared */
|
|
||||||
/* MONITORACT: Debug monitor active */
|
|
||||||
#define SCB_SHCSR_MONITORACT (1 << 8)
|
|
||||||
/* SVCALLACT: SVC call active */
|
|
||||||
#define SCB_SHCSR_SVCALLACT (1 << 7)
|
|
||||||
/* Bits [6:4]: reserved - must be kept cleared */
|
|
||||||
/* USGFAULTACT: Usage fault exception active */
|
|
||||||
#define SCB_SHCSR_USGFAULTACT (1 << 3)
|
|
||||||
/* Bit 2: reserved - must be kept cleared */
|
|
||||||
/* BUSFAULTACT: Bus fault exception active */
|
|
||||||
#define SCB_SHCSR_BUSFAULTACT (1 << 1)
|
|
||||||
/* MEMFAULTACT: Memory management fault exception active */
|
|
||||||
#define SCB_SHCSR_MEMFAULTACT (1 << 0)
|
|
||||||
|
|
||||||
/* --- SCB_CFSR values ----------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Bits [31:26]: reserved - must be kept cleared */
|
|
||||||
/* DIVBYZERO: Divide by zero usage fault */
|
|
||||||
#define SCB_CFSR_DIVBYZERO (1 << 25)
|
|
||||||
/* UNALIGNED: Unaligned access usage fault */
|
|
||||||
#define SCB_CFSR_UNALIGNED (1 << 24)
|
|
||||||
/* Bits [23:20]: reserved - must be kept cleared */
|
|
||||||
/* NOCP: No coprocessor usage fault */
|
|
||||||
#define SCB_CFSR_NOCP (1 << 19)
|
|
||||||
/* INVPC: Invalid PC load usage fault */
|
|
||||||
#define SCB_CFSR_INVPC (1 << 18)
|
|
||||||
/* INVSTATE: Invalid state usage fault */
|
|
||||||
#define SCB_CFSR_INVSTATE (1 << 17)
|
|
||||||
/* UNDEFINSTR: Undefined instruction usage fault */
|
|
||||||
#define SCB_CFSR_UNDEFINSTR (1 << 16)
|
|
||||||
/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
|
|
||||||
#define SCB_CFSR_BFARVALID (1 << 15)
|
|
||||||
/* Bits [14:13]: reserved - must be kept cleared */
|
|
||||||
/* STKERR: Bus fault on stacking for exception entry */
|
|
||||||
#define SCB_CFSR_STKERR (1 << 12)
|
|
||||||
/* UNSTKERR: Bus fault on unstacking for a return from exception */
|
|
||||||
#define SCB_CFSR_UNSTKERR (1 << 11)
|
|
||||||
/* IMPRECISERR: Imprecise data bus error */
|
|
||||||
#define SCB_CFSR_IMPRECISERR (1 << 10)
|
|
||||||
/* PRECISERR: Precise data bus error */
|
|
||||||
#define SCB_CFSR_PRECISERR (1 << 9)
|
|
||||||
/* IBUSERR: Instruction bus error */
|
|
||||||
#define SCB_CFSR_IBUSERR (1 << 8)
|
|
||||||
/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
|
|
||||||
#define SCB_CFSR_MMARVALID (1 << 7)
|
|
||||||
/* Bits [6:5]: reserved - must be kept cleared */
|
|
||||||
/* MSTKERR: Memory manager fault on stacking for exception entry */
|
|
||||||
#define SCB_CFSR_MSTKERR (1 << 4)
|
|
||||||
/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
|
|
||||||
#define SCB_CFSR_MUNSTKERR (1 << 3)
|
|
||||||
/* Bit 2: reserved - must be kept cleared */
|
|
||||||
/* DACCVIOL: Data access violation flag */
|
|
||||||
#define SCB_CFSR_DACCVIOL (1 << 1)
|
|
||||||
/* IACCVIOL: Instruction access violation flag */
|
|
||||||
#define SCB_CFSR_IACCVIOL (1 << 0)
|
|
||||||
|
|
||||||
/* --- SCB_HFSR values ----------------------------------------------------- */
|
|
||||||
|
|
||||||
/* DEBUG_VT: reserved for debug use */
|
|
||||||
#define SCB_HFSR_DEBUG_VT (1 << 31)
|
|
||||||
/* FORCED: Forced hard fault */
|
|
||||||
#define SCB_HFSR_FORCED (1 << 30)
|
|
||||||
/* Bits [29:2]: reserved - must be kept cleared */
|
|
||||||
/* VECTTBL: Vector table hard fault */
|
|
||||||
#define SCB_HFSR_VECTTBL (1 << 1)
|
|
||||||
/* Bit 0: reserved - must be kept cleared */
|
|
||||||
|
|
||||||
/* --- SCB_MMFAR values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* MMFAR [31:0]: Memory management fault address */
|
|
||||||
|
|
||||||
/* --- SCB_BFAR values ----------------------------------------------------- */
|
|
||||||
|
|
||||||
/* BFAR [31:0]: Bus fault address */
|
|
||||||
|
|
||||||
/* --- SCB functions ------------------------------------------------------- */
|
|
||||||
|
|
||||||
BEGIN_DECLS
|
|
||||||
|
|
||||||
void scb_reset_core(void);
|
|
||||||
void scb_reset_system(void);
|
|
||||||
void scb_set_priority_grouping(u32 prigroup);
|
|
||||||
|
|
||||||
/* TODO: */
|
|
||||||
|
|
||||||
END_DECLS
|
|
||||||
|
|
||||||
#endif
|
|
||||||
85
include/libopencm3/stm32/f2/irq.yaml
Normal file
85
include/libopencm3/stm32/f2/irq.yaml
Normal file
@ -0,0 +1,85 @@
|
|||||||
|
includeguard: LIBOPENCM3_STM32_F2_NVIC_H
|
||||||
|
partname_humanreadable: STM32 F2 series
|
||||||
|
partname_doxygen: STM32F2
|
||||||
|
irqs:
|
||||||
|
- nvic_wwdg
|
||||||
|
- pvd
|
||||||
|
- tamp_stamp
|
||||||
|
- rtc_wkup
|
||||||
|
- flash
|
||||||
|
- rcc
|
||||||
|
- exti0
|
||||||
|
- exti1
|
||||||
|
- exti2
|
||||||
|
- exti3
|
||||||
|
- exti4
|
||||||
|
- dma1_stream0
|
||||||
|
- dma1_stream1
|
||||||
|
- dma1_stream2
|
||||||
|
- dma1_stream3
|
||||||
|
- dma1_stream4
|
||||||
|
- dma1_stream5
|
||||||
|
- dma1_stream6
|
||||||
|
- adc
|
||||||
|
- can1_tx
|
||||||
|
- can1_rx0
|
||||||
|
- can1_rx1
|
||||||
|
- can1_sce
|
||||||
|
- exti9_5
|
||||||
|
- tim1_brk_tim9
|
||||||
|
- tim1_up_tim10
|
||||||
|
- tim1_trg_com_tim11
|
||||||
|
- tim1_cc
|
||||||
|
- tim2
|
||||||
|
- tim3
|
||||||
|
- tim4
|
||||||
|
- i2c1_ev
|
||||||
|
- i2c1_er
|
||||||
|
- i2c2_ev
|
||||||
|
- i2c2_er
|
||||||
|
- spi1
|
||||||
|
- spi2
|
||||||
|
- usart1
|
||||||
|
- usart2
|
||||||
|
- usart3
|
||||||
|
- exti15_10
|
||||||
|
- rtc_alarm
|
||||||
|
- usb_fs_wkup
|
||||||
|
- tim8_brk_tim12
|
||||||
|
- tim8_up_tim13
|
||||||
|
- tim8_trg_com_tim14
|
||||||
|
- tim8_cc
|
||||||
|
- dma1_stream7
|
||||||
|
- fsmc
|
||||||
|
- sdio
|
||||||
|
- tim5
|
||||||
|
- spi3
|
||||||
|
- uart4
|
||||||
|
- uart5
|
||||||
|
- tim6_dac
|
||||||
|
- tim7
|
||||||
|
- dma2_stream0
|
||||||
|
- dma2_stream1
|
||||||
|
- dma2_stream2
|
||||||
|
- dma2_stream3
|
||||||
|
- dma2_stream4
|
||||||
|
- eth
|
||||||
|
- eth_wkup
|
||||||
|
- can2_tx
|
||||||
|
- can2_rx0
|
||||||
|
- can2_rx1
|
||||||
|
- can2_sce
|
||||||
|
- otg_fs
|
||||||
|
- dma2_stream5
|
||||||
|
- dma2_stream6
|
||||||
|
- dma2_stream7
|
||||||
|
- usart6
|
||||||
|
- i2c3_ev
|
||||||
|
- i2c3_er
|
||||||
|
- otg_hs_ep1_out
|
||||||
|
- otg_hs_ep1_in
|
||||||
|
- otg_hs_wkup
|
||||||
|
- otg_hs
|
||||||
|
- dcmi
|
||||||
|
- cryp
|
||||||
|
- hash_rng
|
||||||
@ -1,112 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef LIBOPENCM3_NVIC_F2_H
|
|
||||||
#define LIBOPENCM3_NVIC_F2_H
|
|
||||||
|
|
||||||
/* --- IRQ channel numbers-------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Note: These F2 specific user interrupt definitions supplement the
|
|
||||||
* general NVIC definitions in ../nvic.h
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* User Interrupts */
|
|
||||||
#define NVIC_NVIC_WWDG_IRQ 0
|
|
||||||
#define NVIC_PVD_IRQ 1
|
|
||||||
#define NVIC_TAMP_STAMP_IRQ 2
|
|
||||||
#define NVIC_RTC_WKUP_IRQ 3
|
|
||||||
#define NVIC_FLASH_IRQ 4
|
|
||||||
#define NVIC_RCC_IRQ 5
|
|
||||||
#define NVIC_EXTI0_IRQ 6
|
|
||||||
#define NVIC_EXTI1_IRQ 7
|
|
||||||
#define NVIC_EXTI2_IRQ 8
|
|
||||||
#define NVIC_EXTI3_IRQ 9
|
|
||||||
#define NVIC_EXTI4_IRQ 10
|
|
||||||
#define NVIC_DMA1_STREAM0_IRQ 11
|
|
||||||
#define NVIC_DMA1_STREAM1_IRQ 12
|
|
||||||
#define NVIC_DMA1_STREAM2_IRQ 13
|
|
||||||
#define NVIC_DMA1_STREAM3_IRQ 14
|
|
||||||
#define NVIC_DMA1_STREAM4_IRQ 15
|
|
||||||
#define NVIC_DMA1_STREAM5_IRQ 16
|
|
||||||
#define NVIC_DMA1_STREAM6_IRQ 17
|
|
||||||
#define NVIC_ADC_IRQ 18
|
|
||||||
#define NVIC_CAN1_TX_IRQ 19
|
|
||||||
#define NVIC_CAN1_RX0_IRQ 20
|
|
||||||
#define NVIC_CAN1_RX1_IRQ 21
|
|
||||||
#define NVIC_CAN1_SCE_IRQ 22
|
|
||||||
#define NVIC_EXTI9_5_IRQ 23
|
|
||||||
#define NVIC_TIM1_BRK_TIM9_IRQ 24
|
|
||||||
#define NVIC_TIM1_UP_TIM10_IRQ 25
|
|
||||||
#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
|
|
||||||
#define NVIC_TIM1_CC_IRQ 27
|
|
||||||
#define NVIC_TIM2_IRQ 28
|
|
||||||
#define NVIC_TIM3_IRQ 29
|
|
||||||
#define NVIC_TIM4_IRQ 30
|
|
||||||
#define NVIC_I2C1_EV_IRQ 31
|
|
||||||
#define NVIC_I2C1_ER_IRQ 32
|
|
||||||
#define NVIC_I2C2_EV_IRQ 33
|
|
||||||
#define NVIC_I2C2_ER_IRQ 34
|
|
||||||
#define NVIC_SPI1_IRQ 35
|
|
||||||
#define NVIC_SPI2_IRQ 36
|
|
||||||
#define NVIC_USART1_IRQ 37
|
|
||||||
#define NVIC_USART2_IRQ 38
|
|
||||||
#define NVIC_USART3_IRQ 39
|
|
||||||
#define NVIC_EXTI15_10_IRQ 40
|
|
||||||
#define NVIC_RTC_ALARM_IRQ 41
|
|
||||||
#define NVIC_USB_FS_WKUP_IRQ 42
|
|
||||||
#define NVIC_TIM8_BRK_TIM12_IRQ 43
|
|
||||||
#define NVIC_TIM8_UP_TIM13_IRQ 44
|
|
||||||
#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
|
|
||||||
#define NVIC_TIM8_CC_IRQ 46
|
|
||||||
#define NVIC_DMA1_STREAM7_IRQ 47
|
|
||||||
#define NVIC_FSMC_IRQ 48
|
|
||||||
#define NVIC_SDIO_IRQ 49
|
|
||||||
#define NVIC_TIM5_IRQ 50
|
|
||||||
#define NVIC_SPI3_IRQ 51
|
|
||||||
#define NVIC_UART4_IRQ 52
|
|
||||||
#define NVIC_UART5_IRQ 53
|
|
||||||
#define NVIC_TIM6_DAC_IRQ 54
|
|
||||||
#define NVIC_TIM7_IRQ 55
|
|
||||||
#define NVIC_DMA2_STREAM0_IRQ 56
|
|
||||||
#define NVIC_DMA2_STREAM1_IRQ 57
|
|
||||||
#define NVIC_DMA2_STREAM2_IRQ 58
|
|
||||||
#define NVIC_DMA2_STREAM3_IRQ 59
|
|
||||||
#define NVIC_DMA2_STREAM4_IRQ 60
|
|
||||||
#define NVIC_ETH_IRQ 61
|
|
||||||
#define NVIC_ETH_WKUP_IRQ 62
|
|
||||||
#define NVIC_CAN2_TX_IRQ 63
|
|
||||||
#define NVIC_CAN2_RX0_IRQ 64
|
|
||||||
#define NVIC_CAN2_RX1_IRQ 65
|
|
||||||
#define NVIC_CAN2_SCE_IRQ 66
|
|
||||||
#define NVIC_OTG_FS_IRQ 67
|
|
||||||
#define NVIC_DMA2_STREAM5_IRQ 68
|
|
||||||
#define NVIC_DMA2_STREAM6_IRQ 69
|
|
||||||
#define NVIC_DMA2_STREAM7_IRQ 70
|
|
||||||
#define NVIC_USART6_IRQ 71
|
|
||||||
#define NVIC_I2C3_EV_IRQ 72
|
|
||||||
#define NVIC_I2C3_ER_IRQ 73
|
|
||||||
#define NVIC_OTG_HS_EP1_OUT_IRQ 74
|
|
||||||
#define NVIC_OTG_HS_EP1_IN_IRQ 75
|
|
||||||
#define NVIC_OTG_HS_WKUP_IRQ 76
|
|
||||||
#define NVIC_OTG_HS_IRQ 77
|
|
||||||
#define NVIC_DCMI_IRQ 78
|
|
||||||
#define NVIC_CRYP_IRQ 79
|
|
||||||
#define NVIC_HASH_RNG_IRQ 80
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -1,307 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
|
||||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef LIBOPENCM3_SCB_H
|
|
||||||
#define LIBOPENCM3_SCB_H
|
|
||||||
|
|
||||||
#include <libopencm3/stm32/memorymap.h>
|
|
||||||
#include <libopencm3/cm3/common.h>
|
|
||||||
|
|
||||||
/* --- SCB: Registers ------------------------------------------------------ */
|
|
||||||
|
|
||||||
/* CPUID: CPUID base register */
|
|
||||||
#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
|
|
||||||
|
|
||||||
/* ICSR: Interrupt Control State Register */
|
|
||||||
#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
|
|
||||||
|
|
||||||
/* VTOR: Vector Table Offset Register */
|
|
||||||
#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
|
|
||||||
|
|
||||||
/* AIRCR: Application Interrupt and Reset Control Register */
|
|
||||||
#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
|
|
||||||
|
|
||||||
/* SCR: System Control Register */
|
|
||||||
#define SCB_SCR MMIO32(SCB_BASE + 0x10)
|
|
||||||
|
|
||||||
/* CCR: Configuration Control Register */
|
|
||||||
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
|
|
||||||
|
|
||||||
/* SHP: System Handler Priority Registers */
|
|
||||||
/* Note: 12 8bit registers */
|
|
||||||
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
|
|
||||||
#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
|
|
||||||
#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
|
|
||||||
#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
|
|
||||||
|
|
||||||
/* SHCSR: System Handler Control and State Register */
|
|
||||||
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
|
|
||||||
|
|
||||||
/* CFSR: Configurable Fault Status Registers */
|
|
||||||
#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
|
|
||||||
|
|
||||||
/* HFSR: Hard Fault Status Register */
|
|
||||||
#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
|
|
||||||
|
|
||||||
/* DFSR: Debug Fault Status Register */
|
|
||||||
#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
|
|
||||||
|
|
||||||
/* MMFAR: Memory Manage Fault Address Register */
|
|
||||||
#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
|
|
||||||
|
|
||||||
/* BFAR: Bus Fault Address Register */
|
|
||||||
#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
|
|
||||||
|
|
||||||
/* AFSR: Auxiliary Fault Status Register */
|
|
||||||
#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
|
|
||||||
|
|
||||||
/* --- SCB values ---------------------------------------------------------- */
|
|
||||||
|
|
||||||
/* --- SCB_CPUID values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Implementer[31:24]: Implementer code */
|
|
||||||
#define SCP_CPUID_IMPLEMENTER_LSB 24
|
|
||||||
/* Variant[23:20]: Variant number */
|
|
||||||
#define SCP_CPUID_VARIANT_LSB 20
|
|
||||||
/* Constant[19:16]: Reads as 0xF */
|
|
||||||
#define SCP_CPUID_CONSTANT_LSB 16
|
|
||||||
/* PartNo[15:4]: Part number of the processor */
|
|
||||||
#define SCP_CPUID_PARTNO_LSB 4
|
|
||||||
/* Revision[3:0]: Revision number */
|
|
||||||
#define SCP_CPUID_REVISION_LSB 0
|
|
||||||
|
|
||||||
/* --- SCB_ICSR values ----------------------------------------------------- */
|
|
||||||
|
|
||||||
/* NMIPENDSET: NMI set-pending bit */
|
|
||||||
#define SCB_ICSR_NMIPENDSET (1 << 31)
|
|
||||||
/* Bits [30:29]: reserved - must be kept cleared */
|
|
||||||
/* PENDSVSET: PendSV set-pending bit */
|
|
||||||
#define SCB_ICSR_PENDSVSET (1 << 28)
|
|
||||||
/* PENDSVCLR: PendSV clear-pending bit */
|
|
||||||
#define SCB_ICSR_PENDSVCLR (1 << 27)
|
|
||||||
/* PENDSTSET: SysTick exception set-pending bit */
|
|
||||||
#define SCB_ICSR_PENDSTSET (1 << 26)
|
|
||||||
/* PENDSTCLR: SysTick exception clear-pending bit */
|
|
||||||
#define SCB_ICSR_PENDSTCLR (1 << 25)
|
|
||||||
/* Bit 24: reserved - must be kept cleared */
|
|
||||||
/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
|
|
||||||
/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
|
|
||||||
#define SCB_ICSR_ISRPENDING (1 << 22)
|
|
||||||
/* VECTPENDING[21:12] Pending vector */
|
|
||||||
#define SCB_ICSR_VECTPENDING_LSB 12
|
|
||||||
/* RETOBASE: Return to base level */
|
|
||||||
#define SCB_ICSR_RETOBASE (1 << 11)
|
|
||||||
/* Bits [10:9]: reserved - must be kept cleared */
|
|
||||||
/* VECTACTIVE[8:0] Active vector */
|
|
||||||
#define SCB_ICSR_VECTACTIVE_LSB 0
|
|
||||||
|
|
||||||
/* --- SCB_VTOR values ----------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Bits [31:30]: reserved - must be kept cleared */
|
|
||||||
/* TBLOFF[29:9]: Vector table base offset field */
|
|
||||||
#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
|
|
||||||
|
|
||||||
/* --- SCB_AIRCR values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
|
|
||||||
#define SCB_AIRCR_VECTKEYSTAT_LSB 16
|
|
||||||
#define SCB_AIRCR_VECTKEY 0x05FA0000
|
|
||||||
/* ENDIANESS Data endianness bit */
|
|
||||||
#define SCB_AIRCR_ENDIANESS (1 << 15)
|
|
||||||
/* Bits [14:11]: reserved - must be kept cleared */
|
|
||||||
/* PRIGROUP[10:8]: Interrupt priority grouping field */
|
|
||||||
#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
|
|
||||||
#define SCB_AIRCR_PRIGROUP_SHIFT 8
|
|
||||||
/* Bits [7:3]: reserved - must be kept cleared */
|
|
||||||
/* SYSRESETREQ System reset request */
|
|
||||||
#define SCB_AIRCR_SYSRESETREQ (1 << 2)
|
|
||||||
/* VECTCLRACTIVE */
|
|
||||||
#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
|
|
||||||
/* VECTRESET */
|
|
||||||
#define SCB_AIRCR_VECTRESET (1 << 0)
|
|
||||||
|
|
||||||
/* --- SCB_SCR values ------------------------------------------------------ */
|
|
||||||
|
|
||||||
/* Bits [31:5]: reserved - must be kept cleared */
|
|
||||||
/* SEVEONPEND Send Event on Pending bit */
|
|
||||||
#define SCB_SCR_SEVEONPEND (1 << 4)
|
|
||||||
/* Bit 3: reserved - must be kept cleared */
|
|
||||||
/* SLEEPDEEP */
|
|
||||||
#define SCB_SCR_SLEEPDEEP (1 << 2)
|
|
||||||
/* SLEEPONEXIT */
|
|
||||||
#define SCB_SCR_SLEEPONEXIT (1 << 1)
|
|
||||||
/* Bit 0: reserved - must be kept cleared */
|
|
||||||
|
|
||||||
/* --- SCB_CCR values ------------------------------------------------------ */
|
|
||||||
|
|
||||||
/* Bits [31:10]: reserved - must be kept cleared */
|
|
||||||
/* STKALIGN */
|
|
||||||
#define SCB_CCR_STKALIGN (1 << 9)
|
|
||||||
/* BFHFNMIGN */
|
|
||||||
#define SCB_CCR_BFHFNMIGN (1 << 8)
|
|
||||||
/* Bits [7:5]: reserved - must be kept cleared */
|
|
||||||
/* DIV_0_TRP */
|
|
||||||
#define SCB_CCR_DIV_0_TRP (1 << 4)
|
|
||||||
/* UNALIGN_TRP */
|
|
||||||
#define SCB_CCR_UNALIGN_TRP (1 << 3)
|
|
||||||
/* Bit 2: reserved - must be kept cleared */
|
|
||||||
/* USERSETMPEND */
|
|
||||||
#define SCB_CCR_USERSETMPEND (1 << 1)
|
|
||||||
/* NONBASETHRDENA */
|
|
||||||
#define SCB_CCR_NONBASETHRDENA (1 << 0)
|
|
||||||
|
|
||||||
/* --- SCB_SHPR1 values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Bits [31:24]: reserved - must be kept cleared */
|
|
||||||
/* PRI_6[23:16]: Priority of system handler 6, usage fault */
|
|
||||||
#define SCB_SHPR1_PRI_6_LSB 16
|
|
||||||
/* PRI_5[15:8]: Priority of system handler 5, bus fault */
|
|
||||||
#define SCB_SHPR1_PRI_5_LSB 8
|
|
||||||
/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
|
|
||||||
#define SCB_SHPR1_PRI_4_LSB 0
|
|
||||||
|
|
||||||
/* --- SCB_SHPR2 values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* PRI_11[31:24]: Priority of system handler 11, SVCall */
|
|
||||||
#define SCB_SHPR2_PRI_11_LSB 24
|
|
||||||
/* Bits [23:0]: reserved - must be kept cleared */
|
|
||||||
|
|
||||||
/* --- SCB_SHPR3 values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
|
|
||||||
#define SCB_SHPR3_PRI_15_LSB 24
|
|
||||||
/* PRI_14[23:16]: Priority of system handler 14, PendSV */
|
|
||||||
#define SCB_SHPR3_PRI_14_LSB 16
|
|
||||||
/* Bits [15:0]: reserved - must be kept cleared */
|
|
||||||
|
|
||||||
/* --- SCB_SHCSR values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Bits [31:19]: reserved - must be kept cleared */
|
|
||||||
/* USGFAULTENA: Usage fault enable */
|
|
||||||
#define SCB_SHCSR_USGFAULTENA (1 << 18)
|
|
||||||
/* BUSFAULTENA: Bus fault enable */
|
|
||||||
#define SCB_SHCSR_BUSFAULTENA (1 << 17)
|
|
||||||
/* MEMFAULTENA: Memory management fault enable */
|
|
||||||
#define SCB_SHCSR_MEMFAULTENA (1 << 16)
|
|
||||||
/* SVCALLPENDED: SVC call pending */
|
|
||||||
#define SCB_SHCSR_SVCALLPENDED (1 << 15)
|
|
||||||
/* BUSFAULTPENDED: Bus fault exception pending */
|
|
||||||
#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
|
|
||||||
/* MEMFAULTPENDED: Memory management fault exception pending */
|
|
||||||
#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
|
|
||||||
/* USGFAULTPENDED: Usage fault exception pending */
|
|
||||||
#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
|
|
||||||
/* SYSTICKACT: SysTick exception active */
|
|
||||||
#define SCB_SHCSR_SYSTICKACT (1 << 11)
|
|
||||||
/* PENDSVACT: PendSV exception active */
|
|
||||||
#define SCB_SHCSR_PENDSVACT (1 << 10)
|
|
||||||
/* Bit 9: reserved - must be kept cleared */
|
|
||||||
/* MONITORACT: Debug monitor active */
|
|
||||||
#define SCB_SHCSR_MONITORACT (1 << 8)
|
|
||||||
/* SVCALLACT: SVC call active */
|
|
||||||
#define SCB_SHCSR_SVCALLACT (1 << 7)
|
|
||||||
/* Bits [6:4]: reserved - must be kept cleared */
|
|
||||||
/* USGFAULTACT: Usage fault exception active */
|
|
||||||
#define SCB_SHCSR_USGFAULTACT (1 << 3)
|
|
||||||
/* Bit 2: reserved - must be kept cleared */
|
|
||||||
/* BUSFAULTACT: Bus fault exception active */
|
|
||||||
#define SCB_SHCSR_BUSFAULTACT (1 << 1)
|
|
||||||
/* MEMFAULTACT: Memory management fault exception active */
|
|
||||||
#define SCB_SHCSR_MEMFAULTACT (1 << 0)
|
|
||||||
|
|
||||||
/* --- SCB_CFSR values ----------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Bits [31:26]: reserved - must be kept cleared */
|
|
||||||
/* DIVBYZERO: Divide by zero usage fault */
|
|
||||||
#define SCB_CFSR_DIVBYZERO (1 << 25)
|
|
||||||
/* UNALIGNED: Unaligned access usage fault */
|
|
||||||
#define SCB_CFSR_UNALIGNED (1 << 24)
|
|
||||||
/* Bits [23:20]: reserved - must be kept cleared */
|
|
||||||
/* NOCP: No coprocessor usage fault */
|
|
||||||
#define SCB_CFSR_NOCP (1 << 19)
|
|
||||||
/* INVPC: Invalid PC load usage fault */
|
|
||||||
#define SCB_CFSR_INVPC (1 << 18)
|
|
||||||
/* INVSTATE: Invalid state usage fault */
|
|
||||||
#define SCB_CFSR_INVSTATE (1 << 17)
|
|
||||||
/* UNDEFINSTR: Undefined instruction usage fault */
|
|
||||||
#define SCB_CFSR_UNDEFINSTR (1 << 16)
|
|
||||||
/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
|
|
||||||
#define SCB_CFSR_BFARVALID (1 << 15)
|
|
||||||
/* Bits [14:13]: reserved - must be kept cleared */
|
|
||||||
/* STKERR: Bus fault on stacking for exception entry */
|
|
||||||
#define SCB_CFSR_STKERR (1 << 12)
|
|
||||||
/* UNSTKERR: Bus fault on unstacking for a return from exception */
|
|
||||||
#define SCB_CFSR_UNSTKERR (1 << 11)
|
|
||||||
/* IMPRECISERR: Imprecise data bus error */
|
|
||||||
#define SCB_CFSR_IMPRECISERR (1 << 10)
|
|
||||||
/* PRECISERR: Precise data bus error */
|
|
||||||
#define SCB_CFSR_PRECISERR (1 << 9)
|
|
||||||
/* IBUSERR: Instruction bus error */
|
|
||||||
#define SCB_CFSR_IBUSERR (1 << 8)
|
|
||||||
/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
|
|
||||||
#define SCB_CFSR_MMARVALID (1 << 7)
|
|
||||||
/* Bits [6:5]: reserved - must be kept cleared */
|
|
||||||
/* MSTKERR: Memory manager fault on stacking for exception entry */
|
|
||||||
#define SCB_CFSR_MSTKERR (1 << 4)
|
|
||||||
/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
|
|
||||||
#define SCB_CFSR_MUNSTKERR (1 << 3)
|
|
||||||
/* Bit 2: reserved - must be kept cleared */
|
|
||||||
/* DACCVIOL: Data access violation flag */
|
|
||||||
#define SCB_CFSR_DACCVIOL (1 << 1)
|
|
||||||
/* IACCVIOL: Instruction access violation flag */
|
|
||||||
#define SCB_CFSR_IACCVIOL (1 << 0)
|
|
||||||
|
|
||||||
/* --- SCB_HFSR values ----------------------------------------------------- */
|
|
||||||
|
|
||||||
/* DEBUG_VT: reserved for debug use */
|
|
||||||
#define SCB_HFSR_DEBUG_VT (1 << 31)
|
|
||||||
/* FORCED: Forced hard fault */
|
|
||||||
#define SCB_HFSR_FORCED (1 << 30)
|
|
||||||
/* Bits [29:2]: reserved - must be kept cleared */
|
|
||||||
/* VECTTBL: Vector table hard fault */
|
|
||||||
#define SCB_HFSR_VECTTBL (1 << 1)
|
|
||||||
/* Bit 0: reserved - must be kept cleared */
|
|
||||||
|
|
||||||
/* --- SCB_MMFAR values ---------------------------------------------------- */
|
|
||||||
|
|
||||||
/* MMFAR [31:0]: Memory management fault address */
|
|
||||||
|
|
||||||
/* --- SCB_BFAR values ----------------------------------------------------- */
|
|
||||||
|
|
||||||
/* BFAR [31:0]: Bus fault address */
|
|
||||||
|
|
||||||
/* --- SCB functions ------------------------------------------------------- */
|
|
||||||
|
|
||||||
BEGIN_DECLS
|
|
||||||
|
|
||||||
void scb_reset_core(void);
|
|
||||||
void scb_reset_system(void);
|
|
||||||
void scb_set_priority_grouping(u32 prigroup);
|
|
||||||
|
|
||||||
/* TODO: */
|
|
||||||
|
|
||||||
END_DECLS
|
|
||||||
|
|
||||||
#endif
|
|
||||||
85
include/libopencm3/stm32/f4/irq.yaml
Normal file
85
include/libopencm3/stm32/f4/irq.yaml
Normal file
@ -0,0 +1,85 @@
|
|||||||
|
includeguard: LIBOPENCM3_STM32_F4_NVIC_H
|
||||||
|
partname_humanreadable: STM32 F4 series
|
||||||
|
partname_doxygen: STM32F4
|
||||||
|
irqs:
|
||||||
|
- nvic_wwdg
|
||||||
|
- pvd
|
||||||
|
- tamp_stamp
|
||||||
|
- rtc_wkup
|
||||||
|
- flash
|
||||||
|
- rcc
|
||||||
|
- exti0
|
||||||
|
- exti1
|
||||||
|
- exti2
|
||||||
|
- exti3
|
||||||
|
- exti4
|
||||||
|
- dma1_stream0
|
||||||
|
- dma1_stream1
|
||||||
|
- dma1_stream2
|
||||||
|
- dma1_stream3
|
||||||
|
- dma1_stream4
|
||||||
|
- dma1_stream5
|
||||||
|
- dma1_stream6
|
||||||
|
- adc
|
||||||
|
- can1_tx
|
||||||
|
- can1_rx0
|
||||||
|
- can1_rx1
|
||||||
|
- can1_sce
|
||||||
|
- exti9_5
|
||||||
|
- tim1_brk_tim9
|
||||||
|
- tim1_up_tim10
|
||||||
|
- tim1_trg_com_tim11
|
||||||
|
- tim1_cc
|
||||||
|
- tim2
|
||||||
|
- tim3
|
||||||
|
- tim4
|
||||||
|
- i2c1_ev
|
||||||
|
- i2c1_er
|
||||||
|
- i2c2_ev
|
||||||
|
- i2c2_er
|
||||||
|
- spi1
|
||||||
|
- spi2
|
||||||
|
- usart1
|
||||||
|
- usart2
|
||||||
|
- usart3
|
||||||
|
- exti15_10
|
||||||
|
- rtc_alarm
|
||||||
|
- usb_fs_wkup
|
||||||
|
- tim8_brk_tim12
|
||||||
|
- tim8_up_tim13
|
||||||
|
- tim8_trg_com_tim14
|
||||||
|
- tim8_cc
|
||||||
|
- dma1_stream7
|
||||||
|
- fsmc
|
||||||
|
- sdio
|
||||||
|
- tim5
|
||||||
|
- spi3
|
||||||
|
- uart4
|
||||||
|
- uart5
|
||||||
|
- tim6_dac
|
||||||
|
- tim7
|
||||||
|
- dma2_stream0
|
||||||
|
- dma2_stream1
|
||||||
|
- dma2_stream2
|
||||||
|
- dma2_stream3
|
||||||
|
- dma2_stream4
|
||||||
|
- eth
|
||||||
|
- eth_wkup
|
||||||
|
- can2_tx
|
||||||
|
- can2_rx0
|
||||||
|
- can2_rx1
|
||||||
|
- can2_sce
|
||||||
|
- otg_fs
|
||||||
|
- dma2_stream5
|
||||||
|
- dma2_stream6
|
||||||
|
- dma2_stream7
|
||||||
|
- usart6
|
||||||
|
- i2c3_ev
|
||||||
|
- i2c3_er
|
||||||
|
- otg_hs_ep1_out
|
||||||
|
- otg_hs_ep1_in
|
||||||
|
- otg_hs_wkup
|
||||||
|
- otg_hs
|
||||||
|
- dcmi
|
||||||
|
- cryp
|
||||||
|
- hash_rng
|
||||||
@ -1,112 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef LIBOPENCM3_NVIC_F4_H
|
|
||||||
#define LIBOPENCM3_NVIC_F4_H
|
|
||||||
|
|
||||||
/* --- IRQ channel numbers-------------------------------------------------- */
|
|
||||||
|
|
||||||
/* Note: These F4 specific user interrupt definitions supplement the
|
|
||||||
* general NVIC definitions in ../nvic.h
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* User Interrupts */
|
|
||||||
#define NVIC_NVIC_WWDG_IRQ 0
|
|
||||||
#define NVIC_PVD_IRQ 1
|
|
||||||
#define NVIC_TAMP_STAMP_IRQ 2
|
|
||||||
#define NVIC_RTC_WKUP_IRQ 3
|
|
||||||
#define NVIC_FLASH_IRQ 4
|
|
||||||
#define NVIC_RCC_IRQ 5
|
|
||||||
#define NVIC_EXTI0_IRQ 6
|
|
||||||
#define NVIC_EXTI1_IRQ 7
|
|
||||||
#define NVIC_EXTI2_IRQ 8
|
|
||||||
#define NVIC_EXTI3_IRQ 9
|
|
||||||
#define NVIC_EXTI4_IRQ 10
|
|
||||||
#define NVIC_DMA1_STREAM0_IRQ 11
|
|
||||||
#define NVIC_DMA1_STREAM1_IRQ 12
|
|
||||||
#define NVIC_DMA1_STREAM2_IRQ 13
|
|
||||||
#define NVIC_DMA1_STREAM3_IRQ 14
|
|
||||||
#define NVIC_DMA1_STREAM4_IRQ 15
|
|
||||||
#define NVIC_DMA1_STREAM5_IRQ 16
|
|
||||||
#define NVIC_DMA1_STREAM6_IRQ 17
|
|
||||||
#define NVIC_ADC_IRQ 18
|
|
||||||
#define NVIC_CAN1_TX_IRQ 19
|
|
||||||
#define NVIC_CAN1_RX0_IRQ 20
|
|
||||||
#define NVIC_CAN1_RX1_IRQ 21
|
|
||||||
#define NVIC_CAN1_SCE_IRQ 22
|
|
||||||
#define NVIC_EXTI9_5_IRQ 23
|
|
||||||
#define NVIC_TIM1_BRK_TIM9_IRQ 24
|
|
||||||
#define NVIC_TIM1_UP_TIM10_IRQ 25
|
|
||||||
#define NVIC_TIM1_TRG_COM_TIM11_IRQ 26
|
|
||||||
#define NVIC_TIM1_CC_IRQ 27
|
|
||||||
#define NVIC_TIM2_IRQ 28
|
|
||||||
#define NVIC_TIM3_IRQ 29
|
|
||||||
#define NVIC_TIM4_IRQ 30
|
|
||||||
#define NVIC_I2C1_EV_IRQ 31
|
|
||||||
#define NVIC_I2C1_ER_IRQ 32
|
|
||||||
#define NVIC_I2C2_EV_IRQ 33
|
|
||||||
#define NVIC_I2C2_ER_IRQ 34
|
|
||||||
#define NVIC_SPI1_IRQ 35
|
|
||||||
#define NVIC_SPI2_IRQ 36
|
|
||||||
#define NVIC_USART1_IRQ 37
|
|
||||||
#define NVIC_USART2_IRQ 38
|
|
||||||
#define NVIC_USART3_IRQ 39
|
|
||||||
#define NVIC_EXTI15_10_IRQ 40
|
|
||||||
#define NVIC_RTC_ALARM_IRQ 41
|
|
||||||
#define NVIC_USB_FS_WKUP_IRQ 42
|
|
||||||
#define NVIC_TIM8_BRK_TIM12_IRQ 43
|
|
||||||
#define NVIC_TIM8_UP_TIM13_IRQ 44
|
|
||||||
#define NVIC_TIM8_TRG_COM_TIM14_IRQ 45
|
|
||||||
#define NVIC_TIM8_CC_IRQ 46
|
|
||||||
#define NVIC_DMA1_STREAM7_IRQ 47
|
|
||||||
#define NVIC_FSMC_IRQ 48
|
|
||||||
#define NVIC_SDIO_IRQ 49
|
|
||||||
#define NVIC_TIM5_IRQ 50
|
|
||||||
#define NVIC_SPI3_IRQ 51
|
|
||||||
#define NVIC_UART4_IRQ 52
|
|
||||||
#define NVIC_UART5_IRQ 53
|
|
||||||
#define NVIC_TIM6_DAC_IRQ 54
|
|
||||||
#define NVIC_TIM7_IRQ 55
|
|
||||||
#define NVIC_DMA2_STREAM0_IRQ 56
|
|
||||||
#define NVIC_DMA2_STREAM1_IRQ 57
|
|
||||||
#define NVIC_DMA2_STREAM2_IRQ 58
|
|
||||||
#define NVIC_DMA2_STREAM3_IRQ 59
|
|
||||||
#define NVIC_DMA2_STREAM4_IRQ 60
|
|
||||||
#define NVIC_ETH_IRQ 61
|
|
||||||
#define NVIC_ETH_WKUP_IRQ 62
|
|
||||||
#define NVIC_CAN2_TX_IRQ 63
|
|
||||||
#define NVIC_CAN2_RX0_IRQ 64
|
|
||||||
#define NVIC_CAN2_RX1_IRQ 65
|
|
||||||
#define NVIC_CAN2_SCE_IRQ 66
|
|
||||||
#define NVIC_OTG_FS_IRQ 67
|
|
||||||
#define NVIC_DMA2_STREAM5_IRQ 68
|
|
||||||
#define NVIC_DMA2_STREAM6_IRQ 69
|
|
||||||
#define NVIC_DMA2_STREAM7_IRQ 70
|
|
||||||
#define NVIC_USART6_IRQ 71
|
|
||||||
#define NVIC_I2C3_EV_IRQ 72
|
|
||||||
#define NVIC_I2C3_ER_IRQ 73
|
|
||||||
#define NVIC_OTG_HS_EP1_OUT_IRQ 74
|
|
||||||
#define NVIC_OTG_HS_EP1_IN_IRQ 75
|
|
||||||
#define NVIC_OTG_HS_WKUP_IRQ 76
|
|
||||||
#define NVIC_OTG_HS_IRQ 77
|
|
||||||
#define NVIC_DCMI_IRQ 78
|
|
||||||
#define NVIC_CRYP_IRQ 79
|
|
||||||
#define NVIC_HASH_RNG_IRQ 80
|
|
||||||
|
|
||||||
#endif
|
|
||||||
@ -23,6 +23,9 @@ ifneq ($(V),1)
|
|||||||
Q := @
|
Q := @
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
# common objects
|
||||||
|
OBJS += vector.o systick.o scb.o nvic.o assert.o
|
||||||
|
|
||||||
all: $(SRCLIBDIR)/$(LIBNAME).a
|
all: $(SRCLIBDIR)/$(LIBNAME).a
|
||||||
|
|
||||||
$(SRCLIBDIR)/$(LIBNAME).a: $(SRCLIBDIR)/$(LIBNAME).ld $(OBJS)
|
$(SRCLIBDIR)/$(LIBNAME).a: $(SRCLIBDIR)/$(LIBNAME).ld $(OBJS)
|
||||||
|
|||||||
@ -1,31 +1,9 @@
|
|||||||
/** @defgroup STM32F_nvic_file NVIC
|
|
||||||
|
|
||||||
@ingroup STM32F_files
|
|
||||||
|
|
||||||
@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
|
|
||||||
|
|
||||||
@version 1.0.0
|
|
||||||
|
|
||||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
|
||||||
@author @htmlonly © @endhtmlonly 2012 Fergus Noble <fergusnoble@gmail.com>
|
|
||||||
|
|
||||||
@date 18 August 2012
|
|
||||||
|
|
||||||
The STM32F series provides up to 68 maskable user interrupts for the STM32F10x
|
|
||||||
series, and 87 for the STM32F2xx and STM32F4xx series.
|
|
||||||
|
|
||||||
The NVIC registers are defined by the ARM standards but the STM32F series have some
|
|
||||||
additional limitations
|
|
||||||
@see Cortex-M3 Devices Generic User Guide
|
|
||||||
@see STM32F10xxx Cortex-M3 programming manual
|
|
||||||
|
|
||||||
LGPL License Terms @ref lgpl_license
|
|
||||||
*/
|
|
||||||
/*
|
/*
|
||||||
* This file is part of the libopencm3 project.
|
* This file is part of the libopencm3 project.
|
||||||
*
|
*
|
||||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||||
* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
|
* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
|
||||||
|
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||||
*
|
*
|
||||||
* This library is free software: you can redistribute it and/or modify
|
* This library is free software: you can redistribute it and/or modify
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
@ -40,10 +18,32 @@ LGPL License Terms @ref lgpl_license
|
|||||||
* You should have received a copy of the GNU Lesser General Public License
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
|
/** @defgroup CM3_nvic_file NVIC
|
||||||
|
|
||||||
|
@ingroup CM3_files
|
||||||
|
|
||||||
|
@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
|
||||||
|
|
||||||
|
@version 1.0.0
|
||||||
|
|
||||||
|
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||||
|
@author @htmlonly © @endhtmlonly 2012 Fergus Noble <fergusnoble@gmail.com>
|
||||||
|
|
||||||
|
@date 18 August 2012
|
||||||
|
|
||||||
|
Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults,
|
||||||
|
systicks etc.) and varying numbers of implementation defined interrupts
|
||||||
|
(typically peripherial interrupts and DMA).
|
||||||
|
|
||||||
|
@see Cortex-M3 Devices Generic User Guide
|
||||||
|
@see STM32F10xxx Cortex-M3 programming manual
|
||||||
|
|
||||||
|
LGPL License Terms @ref lgpl_license
|
||||||
|
*/
|
||||||
/**@{*/
|
/**@{*/
|
||||||
|
|
||||||
#include <libopencm3/stm32/nvic.h>
|
#include <libopencm3/cm3/nvic.h>
|
||||||
|
#include <libopencm3/cm3/scs.h>
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------------*/
|
/*-----------------------------------------------------------------------------*/
|
||||||
/** @brief NVIC Enable Interrupt
|
/** @brief NVIC Enable Interrupt
|
||||||
@ -153,7 +153,18 @@ Control Register (SCB_AIRCR), as done in @ref scb_set_priority_grouping.
|
|||||||
|
|
||||||
void nvic_set_priority(u8 irqn, u8 priority)
|
void nvic_set_priority(u8 irqn, u8 priority)
|
||||||
{
|
{
|
||||||
NVIC_IPR(irqn) = priority;
|
/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
|
||||||
|
* negative interrupt numbers assigned to the system interrupts. better
|
||||||
|
* handling would mean signed integers. */
|
||||||
|
if(irqn>=NVIC_IRQ_COUNT)
|
||||||
|
{
|
||||||
|
/* Cortex-M system interrupts */
|
||||||
|
SCS_SHPR( (irqn&0xF)-4 ) = priority;
|
||||||
|
}else
|
||||||
|
{
|
||||||
|
/* Device specific interrupts */
|
||||||
|
NVIC_IPR(irqn) = priority;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------------*/
|
/*-----------------------------------------------------------------------------*/
|
||||||
@ -171,4 +182,3 @@ void nvic_generate_software_interrupt(u16 irqn)
|
|||||||
NVIC_STIR |= irqn;
|
NVIC_STIR |= irqn;
|
||||||
}
|
}
|
||||||
/**@}*/
|
/**@}*/
|
||||||
|
|
||||||
@ -17,7 +17,7 @@
|
|||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <libopencm3/stm32/f4/scb.h>
|
#include <libopencm3/cm3/scb.h>
|
||||||
|
|
||||||
void scb_reset_core(void)
|
void scb_reset_core(void)
|
||||||
{
|
{
|
||||||
@ -1,27 +1,8 @@
|
|||||||
/** @defgroup STM32F_systick_file SysTick
|
|
||||||
|
|
||||||
@ingroup STM32F_files
|
|
||||||
|
|
||||||
@brief <b>libopencm3 STM32Fxx System Tick Timer</b>
|
|
||||||
|
|
||||||
@version 1.0.0
|
|
||||||
|
|
||||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
|
||||||
|
|
||||||
@date 19 August 2012
|
|
||||||
|
|
||||||
This library supports the System Tick timer in the
|
|
||||||
STM32F series of ARM Cortex Microcontrollers by ST Microelectronics.
|
|
||||||
|
|
||||||
The System Tick timer is part of the ARM Cortex core. It is a 24 bit
|
|
||||||
down counter that can be configured with an automatical reload value.
|
|
||||||
|
|
||||||
LGPL License Terms @ref lgpl_license
|
|
||||||
*/
|
|
||||||
/*
|
/*
|
||||||
* This file is part of the libopencm3 project.
|
* This file is part of the libopencm3 project.
|
||||||
*
|
*
|
||||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||||
|
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
||||||
*
|
*
|
||||||
* This library is free software: you can redistribute it and/or modify
|
* This library is free software: you can redistribute it and/or modify
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
@ -36,9 +17,28 @@ LGPL License Terms @ref lgpl_license
|
|||||||
* You should have received a copy of the GNU Lesser General Public License
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
|
/** @defgroup CM3_systick_file SysTick
|
||||||
|
|
||||||
|
@ingroup CM3_files
|
||||||
|
|
||||||
|
@brief <b>libopencm3 Cortex System Tick Timer</b>
|
||||||
|
|
||||||
|
@version 1.0.0
|
||||||
|
|
||||||
|
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||||
|
|
||||||
|
@date 19 August 2012
|
||||||
|
|
||||||
|
This library supports the System Tick timer in ARM Cortex Microcontrollers.
|
||||||
|
|
||||||
|
The System Tick timer is part of the ARM Cortex core. It is a 24 bit
|
||||||
|
down counter that can be configured with an automatical reload value.
|
||||||
|
|
||||||
|
LGPL License Terms @ref lgpl_license
|
||||||
|
*/
|
||||||
|
|
||||||
/**@{*/
|
/**@{*/
|
||||||
#include <libopencm3/stm32/systick.h>
|
#include <libopencm3/cm3/systick.h>
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------------*/
|
/*-----------------------------------------------------------------------------*/
|
||||||
/** @brief SysTick Set the Automatic Reload Value.
|
/** @brief SysTick Set the Automatic Reload Value.
|
||||||
@ -135,5 +135,15 @@ u8 systick_get_countflag(void)
|
|||||||
else
|
else
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief SysTick Get Calibration Value
|
||||||
|
|
||||||
|
@returns Current calibration value
|
||||||
|
*/
|
||||||
|
u32 systick_get_calib(void)
|
||||||
|
{
|
||||||
|
return (STK_CALIB&0x00FFFFFF);
|
||||||
|
}
|
||||||
/**@}*/
|
/**@}*/
|
||||||
|
|
||||||
@ -1,7 +1,8 @@
|
|||||||
/*
|
/*
|
||||||
* This file is part of the libopencm3 project.
|
* This file is part of the libopencm3 project.
|
||||||
*
|
*
|
||||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>,
|
||||||
|
* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
|
||||||
*
|
*
|
||||||
* This library is free software: you can redistribute it and/or modify
|
* This library is free software: you can redistribute it and/or modify
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
@ -14,19 +15,26 @@
|
|||||||
* GNU Lesser General Public License for more details.
|
* GNU Lesser General Public License for more details.
|
||||||
*
|
*
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <libopencm3/cm3/vector.h>
|
||||||
|
|
||||||
|
/* load optional platform dependent initialization routines */
|
||||||
|
#include "../dispatch/vector_chipset.c"
|
||||||
|
/* load the weak symbols for IRQ_HANDLERS */
|
||||||
|
#include "../dispatch/vector_nvic.c"
|
||||||
|
|
||||||
#define WEAK __attribute__ ((weak))
|
#define WEAK __attribute__ ((weak))
|
||||||
|
|
||||||
/* Symbols exported by the linker script(s): */
|
/* Symbols exported by the linker script(s): */
|
||||||
extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
|
extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
|
||||||
|
|
||||||
void main(void);
|
void main(void);
|
||||||
void reset_handler(void);
|
|
||||||
void blocking_handler(void);
|
void blocking_handler(void);
|
||||||
void null_handler(void);
|
void null_handler(void);
|
||||||
|
|
||||||
|
void WEAK reset_handler(void);
|
||||||
void WEAK nmi_handler(void);
|
void WEAK nmi_handler(void);
|
||||||
void WEAK hard_fault_handler(void);
|
void WEAK hard_fault_handler(void);
|
||||||
void WEAK mem_manage_handler(void);
|
void WEAK mem_manage_handler(void);
|
||||||
@ -37,27 +45,25 @@ void WEAK debug_monitor_handler(void);
|
|||||||
void WEAK pend_sv_handler(void);
|
void WEAK pend_sv_handler(void);
|
||||||
void WEAK sys_tick_handler(void);
|
void WEAK sys_tick_handler(void);
|
||||||
|
|
||||||
/* TODO: Interrupt handler prototypes */
|
|
||||||
|
|
||||||
__attribute__ ((section(".vectors")))
|
__attribute__ ((section(".vectors")))
|
||||||
void (*const vector_table[]) (void) = {
|
vector_table_t vector_table = {
|
||||||
(void*)&_stack, /* Addr: 0x0000_0000 */
|
.initial_sp_value = &_stack,
|
||||||
reset_handler, /* Addr: 0x0000_0004 */
|
.reset = reset_handler,
|
||||||
nmi_handler, /* Addr: 0x0000_0008 */
|
.nmi = nmi_handler,
|
||||||
hard_fault_handler, /* Addr: 0x0000_000C */
|
.hard_fault = hard_fault_handler,
|
||||||
mem_manage_handler, /* Addr: 0x0000_0010 */
|
.memory_manage_fault = mem_manage_handler,
|
||||||
bus_fault_handler, /* Addr: 0x0000_0014 */
|
.bus_fault = bus_fault_handler,
|
||||||
usage_fault_handler, /* Addr: 0x0000_0018 */
|
.usage_fault = usage_fault_handler,
|
||||||
0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */
|
.debug_monitor = debug_monitor_handler,
|
||||||
sv_call_handler, /* Addr: 0x0000_002C */
|
.sv_call = sv_call_handler,
|
||||||
debug_monitor_handler, /* Addr: 0x0000_0030 */
|
.pend_sv = pend_sv_handler,
|
||||||
0, /* Reserved Addr: 0x0000_00034 */
|
.systick = sys_tick_handler,
|
||||||
pend_sv_handler, /* Addr: 0x0000_0038 */
|
.irq = {
|
||||||
sys_tick_handler, /* Addr: 0x0000_003C */
|
IRQ_HANDLERS
|
||||||
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
void WEAK reset_handler(void)
|
||||||
void reset_handler(void)
|
|
||||||
{
|
{
|
||||||
volatile unsigned *src, *dest;
|
volatile unsigned *src, *dest;
|
||||||
|
|
||||||
@ -69,6 +75,9 @@ void reset_handler(void)
|
|||||||
while (dest < &_ebss)
|
while (dest < &_ebss)
|
||||||
*dest++ = 0;
|
*dest++ = 0;
|
||||||
|
|
||||||
|
/* might be provided by platform specific vector.c */
|
||||||
|
pre_main();
|
||||||
|
|
||||||
/* Call the application's entry point. */
|
/* Call the application's entry point. */
|
||||||
main();
|
main();
|
||||||
}
|
}
|
||||||
@ -92,4 +101,3 @@ void null_handler(void)
|
|||||||
#pragma weak debug_monitor_handler = null_handler
|
#pragma weak debug_monitor_handler = null_handler
|
||||||
#pragma weak pend_sv_handler = null_handler
|
#pragma weak pend_sv_handler = null_handler
|
||||||
#pragma weak sys_tick_handler = null_handler
|
#pragma weak sys_tick_handler = null_handler
|
||||||
/* TODO: Interrupt handler weak aliases */
|
|
||||||
11
lib/dispatch/vector_chipset.c
Normal file
11
lib/dispatch/vector_chipset.c
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
#if defined(STM32F4)
|
||||||
|
# include "../stm32/f4/vector_chipset.c"
|
||||||
|
|
||||||
|
#elif defined(LPC43XX)
|
||||||
|
# include "../lpc43xx/vector_chipset.c"
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
static void pre_main(void) {}
|
||||||
|
|
||||||
|
#endif
|
||||||
26
lib/dispatch/vector_nvic.c
Normal file
26
lib/dispatch/vector_nvic.c
Normal file
@ -0,0 +1,26 @@
|
|||||||
|
#if defined(STM32F1)
|
||||||
|
# include "../stm32/f1/vector_nvic.c"
|
||||||
|
#elif defined(STM32F2)
|
||||||
|
# include "../stm32/f2/vector_nvic.c"
|
||||||
|
#elif defined(STM32F4)
|
||||||
|
# include "../stm32/f4/vector_nvic.c"
|
||||||
|
|
||||||
|
#elif defined(TINYGECKO)
|
||||||
|
# include "../efm32/tinygecko/vector_nvic.c"
|
||||||
|
|
||||||
|
#elif defined(LPC13XX)
|
||||||
|
# include "../lpc13xx/vector_nvic.c"
|
||||||
|
#elif defined(LPC17XX)
|
||||||
|
# include "../lpc17xx/vector_nvic.c"
|
||||||
|
#elif defined(LPC43XX)
|
||||||
|
# include "../lpc43xx/vector_nvic.c"
|
||||||
|
|
||||||
|
#elif defined(LM3S)
|
||||||
|
# include "../lm3s/vector_nvic.c"
|
||||||
|
|
||||||
|
#else
|
||||||
|
# warning"no interrupts defined for chipset; not allocating space in the vector table"
|
||||||
|
|
||||||
|
#define IRQ_HANDLERS
|
||||||
|
|
||||||
|
#endif
|
||||||
@ -25,7 +25,7 @@ CC = $(PREFIX)-gcc
|
|||||||
AR = $(PREFIX)-ar
|
AR = $(PREFIX)-ar
|
||||||
CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \
|
CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \
|
||||||
-mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
|
-mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
|
||||||
-ffunction-sections -fdata-sections -MD
|
-ffunction-sections -fdata-sections -MD -DLM3S
|
||||||
# ARFLAGS = rcsv
|
# ARFLAGS = rcsv
|
||||||
ARFLAGS = rcs
|
ARFLAGS = rcs
|
||||||
OBJS = gpio.o vector.o assert.o
|
OBJS = gpio.o vector.o assert.o
|
||||||
|
|||||||
@ -1,454 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define WEAK __attribute__ ((weak))
|
|
||||||
|
|
||||||
/* Symbols exported by the linker script(s): */
|
|
||||||
extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
|
|
||||||
|
|
||||||
void main(void);
|
|
||||||
void reset_handler(void);
|
|
||||||
void blocking_handler(void);
|
|
||||||
void null_handler(void);
|
|
||||||
|
|
||||||
void WEAK nmi_handler(void);
|
|
||||||
void WEAK hard_fault_handler(void);
|
|
||||||
void WEAK mem_manage_handler(void);
|
|
||||||
void WEAK bus_fault_handler(void);
|
|
||||||
void WEAK usage_fault_handler(void);
|
|
||||||
void WEAK sv_call_handler(void);
|
|
||||||
void WEAK debug_monitor_handler(void);
|
|
||||||
void WEAK pend_sv_handler(void);
|
|
||||||
void WEAK sys_tick_handler(void);
|
|
||||||
|
|
||||||
void WEAK gpioa_handler(void);
|
|
||||||
void WEAK gpiob_handler(void);
|
|
||||||
void WEAK gpioc_handler(void);
|
|
||||||
void WEAK gpiod_handler(void);
|
|
||||||
void WEAK gpioe_handler(void);
|
|
||||||
void WEAK uart0_handler(void);
|
|
||||||
void WEAK uart1_handler(void);
|
|
||||||
void WEAK ssi0_handler(void);
|
|
||||||
void WEAK i2c0_handler(void);
|
|
||||||
void WEAK pwm0_fault_handler(void);
|
|
||||||
void WEAK pwm0_0_handler(void);
|
|
||||||
void WEAK pwm0_1_handler(void);
|
|
||||||
void WEAK pwm0_2_handler(void);
|
|
||||||
void WEAK qei0_handler(void);
|
|
||||||
void WEAK adc0ss0_handler(void);
|
|
||||||
void WEAK adc0ss1_handler(void);
|
|
||||||
void WEAK adc0ss2_handler(void);
|
|
||||||
void WEAK adc0ss3_handler(void);
|
|
||||||
void WEAK watchdog_handler(void);
|
|
||||||
void WEAK timer0a_handler(void);
|
|
||||||
void WEAK timer0b_handler(void);
|
|
||||||
void WEAK timer1a_handler(void);
|
|
||||||
void WEAK timer1b_handler(void);
|
|
||||||
void WEAK timer2a_handler(void);
|
|
||||||
void WEAK timer2b_handler(void);
|
|
||||||
void WEAK comp0_handler(void);
|
|
||||||
void WEAK comp1_handler(void);
|
|
||||||
void WEAK comp2_handler(void);
|
|
||||||
void WEAK sysctl_handler(void);
|
|
||||||
void WEAK flash_handler(void);
|
|
||||||
void WEAK gpiof_handler(void);
|
|
||||||
void WEAK gpiog_handler(void);
|
|
||||||
void WEAK gpioh_handler(void);
|
|
||||||
void WEAK uart2_handler(void);
|
|
||||||
void WEAK ssi1_handler(void);
|
|
||||||
void WEAK timer3a_handler(void);
|
|
||||||
void WEAK timer3b_handler(void);
|
|
||||||
void WEAK i2c1_handler(void);
|
|
||||||
void WEAK qei1_handler(void);
|
|
||||||
void WEAK can0_handler(void);
|
|
||||||
void WEAK can1_handler(void);
|
|
||||||
void WEAK can2_handler(void);
|
|
||||||
void WEAK eth_handler(void);
|
|
||||||
void WEAK hibernate_handler(void);
|
|
||||||
void WEAK usb0_handler(void);
|
|
||||||
void WEAK pwm0_3_handler(void);
|
|
||||||
void WEAK udma_handler(void);
|
|
||||||
void WEAK udmaerr_handler(void);
|
|
||||||
void WEAK adc1ss0_handler(void);
|
|
||||||
void WEAK adc1ss1_handler(void);
|
|
||||||
void WEAK adc1ss2_handler(void);
|
|
||||||
void WEAK adc1ss3_handler(void);
|
|
||||||
void WEAK i2s0_handler(void);
|
|
||||||
void WEAK epi0_handler(void);
|
|
||||||
void WEAK gpioj_handler(void);
|
|
||||||
void WEAK gpiok_handler(void);
|
|
||||||
void WEAK gpiol_handler(void);
|
|
||||||
void WEAK ssi2_handler(void);
|
|
||||||
void WEAK ssi3_handler(void);
|
|
||||||
void WEAK uart3_handler(void);
|
|
||||||
void WEAK uart4_handler(void);
|
|
||||||
void WEAK uart5_handler(void);
|
|
||||||
void WEAK uart6_handler(void);
|
|
||||||
void WEAK uart7_handler(void);
|
|
||||||
void WEAK i2c2_handler(void);
|
|
||||||
void WEAK i2c3_handler(void);
|
|
||||||
void WEAK timer4a_handler(void);
|
|
||||||
void WEAK timer4b_handler(void);
|
|
||||||
void WEAK timer5a_handler(void);
|
|
||||||
void WEAK timer5b_handler(void);
|
|
||||||
void WEAK wtimer0a_handler(void);
|
|
||||||
void WEAK wtimer0b_handler(void);
|
|
||||||
void WEAK wtimer1a_handler(void);
|
|
||||||
void WEAK wtimer1b_handler(void);
|
|
||||||
void WEAK wtimer2a_handler(void);
|
|
||||||
void WEAK wtimer2b_handler(void);
|
|
||||||
void WEAK wtimer3a_handler(void);
|
|
||||||
void WEAK wtimer3b_handler(void);
|
|
||||||
void WEAK wtimer4a_handler(void);
|
|
||||||
void WEAK wtimer4b_handler(void);
|
|
||||||
void WEAK wtimer5a_handler(void);
|
|
||||||
void WEAK wtimer5b_handler(void);
|
|
||||||
void WEAK sysexc_handler(void);
|
|
||||||
void WEAK peci0_handler(void);
|
|
||||||
void WEAK lpc0_handler(void);
|
|
||||||
void WEAK i2c4_handler(void);
|
|
||||||
void WEAK i2c5_handler(void);
|
|
||||||
void WEAK gpiom_handler(void);
|
|
||||||
void WEAK gpion_handler(void);
|
|
||||||
void WEAK fan0_handler(void);
|
|
||||||
void WEAK gpiop0_handler(void);
|
|
||||||
void WEAK gpiop1_handler(void);
|
|
||||||
void WEAK gpiop2_handler(void);
|
|
||||||
void WEAK gpiop3_handler(void);
|
|
||||||
void WEAK gpiop4_handler(void);
|
|
||||||
void WEAK gpiop5_handler(void);
|
|
||||||
void WEAK gpiop6_handler(void);
|
|
||||||
void WEAK gpiop7_handler(void);
|
|
||||||
void WEAK gpioq0_handler(void);
|
|
||||||
void WEAK gpioq1_handler(void);
|
|
||||||
void WEAK gpioq2_handler(void);
|
|
||||||
void WEAK gpioq3_handler(void);
|
|
||||||
void WEAK gpioq4_handler(void);
|
|
||||||
void WEAK gpioq5_handler(void);
|
|
||||||
void WEAK gpioq6_handler(void);
|
|
||||||
void WEAK gpioq7_handler(void);
|
|
||||||
void WEAK pwm1_0_handler(void);
|
|
||||||
void WEAK pwm1_1_handler(void);
|
|
||||||
void WEAK pwm1_2_handler(void);
|
|
||||||
void WEAK pwm1_3_handler(void);
|
|
||||||
void WEAK pwm1_fault_handler(void);
|
|
||||||
|
|
||||||
__attribute__ ((section(".vectors")))
|
|
||||||
void (*const vector_table[]) (void) = {
|
|
||||||
(void *)&_stack,
|
|
||||||
reset_handler,
|
|
||||||
nmi_handler,
|
|
||||||
hard_fault_handler,
|
|
||||||
mem_manage_handler,
|
|
||||||
bus_fault_handler,
|
|
||||||
usage_fault_handler,
|
|
||||||
0, 0, 0, 0, /* Reserved */
|
|
||||||
sv_call_handler,
|
|
||||||
debug_monitor_handler,
|
|
||||||
0, /* Reserved */
|
|
||||||
pend_sv_handler,
|
|
||||||
sys_tick_handler,
|
|
||||||
|
|
||||||
gpioa_handler, /* 16 */
|
|
||||||
gpiob_handler, /* 17 */
|
|
||||||
gpioc_handler, /* 18 */
|
|
||||||
gpiod_handler, /* 19 */
|
|
||||||
gpioe_handler, /* 20 */
|
|
||||||
uart0_handler, /* 21 */
|
|
||||||
uart1_handler, /* 22 */
|
|
||||||
ssi0_handler, /* 23 */
|
|
||||||
i2c0_handler, /* 24 */
|
|
||||||
pwm0_fault_handler, /* 25 */
|
|
||||||
pwm0_0_handler, /* 26 */
|
|
||||||
pwm0_1_handler, /* 27 */
|
|
||||||
pwm0_2_handler, /* 28 */
|
|
||||||
qei0_handler, /* 29 */
|
|
||||||
adc0ss0_handler, /* 30 */
|
|
||||||
adc0ss1_handler, /* 31 */
|
|
||||||
adc0ss2_handler, /* 32 */
|
|
||||||
adc0ss3_handler, /* 33 */
|
|
||||||
watchdog_handler, /* 34 */
|
|
||||||
timer0a_handler, /* 35 */
|
|
||||||
timer0b_handler, /* 36 */
|
|
||||||
timer1a_handler, /* 37 */
|
|
||||||
timer1b_handler, /* 38 */
|
|
||||||
timer2a_handler, /* 39 */
|
|
||||||
timer2b_handler, /* 40 */
|
|
||||||
comp0_handler, /* 41 */
|
|
||||||
comp1_handler, /* 42 */
|
|
||||||
comp2_handler, /* 43 */
|
|
||||||
sysctl_handler, /* 44 */
|
|
||||||
flash_handler, /* 45 */
|
|
||||||
gpiof_handler, /* 46 */
|
|
||||||
gpiog_handler, /* 47 */
|
|
||||||
gpioh_handler, /* 48 */
|
|
||||||
uart2_handler, /* 49 */
|
|
||||||
ssi1_handler, /* 50 */
|
|
||||||
timer3a_handler, /* 51 */
|
|
||||||
timer3b_handler, /* 52 */
|
|
||||||
i2c1_handler, /* 53 */
|
|
||||||
qei1_handler, /* 54 */
|
|
||||||
can0_handler, /* 55 */
|
|
||||||
can1_handler, /* 56 */
|
|
||||||
can2_handler, /* 57 */
|
|
||||||
eth_handler, /* 58 */
|
|
||||||
hibernate_handler, /* 59 */
|
|
||||||
usb0_handler, /* 60 */
|
|
||||||
pwm0_3_handler, /* 61 */
|
|
||||||
udma_handler, /* 62 */
|
|
||||||
udmaerr_handler, /* 63 */
|
|
||||||
adc1ss0_handler, /* 64 */
|
|
||||||
adc1ss1_handler, /* 65 */
|
|
||||||
adc1ss2_handler, /* 66 */
|
|
||||||
adc1ss3_handler, /* 67 */
|
|
||||||
i2s0_handler, /* 68 */
|
|
||||||
epi0_handler, /* 69 */
|
|
||||||
gpioj_handler, /* 70 */
|
|
||||||
gpiok_handler, /* 71 */
|
|
||||||
gpiol_handler, /* 72 */
|
|
||||||
ssi2_handler, /* 73 */
|
|
||||||
ssi3_handler, /* 74 */
|
|
||||||
uart3_handler, /* 75 */
|
|
||||||
uart4_handler, /* 76 */
|
|
||||||
uart5_handler, /* 77 */
|
|
||||||
uart6_handler, /* 78 */
|
|
||||||
uart7_handler, /* 79 */
|
|
||||||
0, /* 80 */
|
|
||||||
0, /* 81 */
|
|
||||||
0, /* 82 */
|
|
||||||
0, /* 83 */
|
|
||||||
i2c2_handler, /* 84 */
|
|
||||||
i2c3_handler, /* 85 */
|
|
||||||
timer4a_handler, /* 86 */
|
|
||||||
timer4b_handler, /* 87 */
|
|
||||||
0, /* 88 */
|
|
||||||
0, /* 89 */
|
|
||||||
0, /* 90 */
|
|
||||||
0, /* 91 */
|
|
||||||
0, /* 92 */
|
|
||||||
0, /* 93 */
|
|
||||||
0, /* 94 */
|
|
||||||
0, /* 95 */
|
|
||||||
0, /* 96 */
|
|
||||||
0, /* 97 */
|
|
||||||
0, /* 98 */
|
|
||||||
0, /* 99 */
|
|
||||||
0, /* 100 */
|
|
||||||
0, /* 101 */
|
|
||||||
0, /* 102 */
|
|
||||||
0, /* 103 */
|
|
||||||
0, /* 104 */
|
|
||||||
0, /* 105 */
|
|
||||||
0, /* 106 */
|
|
||||||
0, /* 107 */
|
|
||||||
timer5a_handler, /* 108 */
|
|
||||||
timer5b_handler, /* 109 */
|
|
||||||
wtimer0a_handler, /* 110 */
|
|
||||||
wtimer0b_handler, /* 111 */
|
|
||||||
wtimer1a_handler, /* 112 */
|
|
||||||
wtimer1b_handler, /* 113 */
|
|
||||||
wtimer2a_handler, /* 114 */
|
|
||||||
wtimer2b_handler, /* 115 */
|
|
||||||
wtimer3a_handler, /* 116 */
|
|
||||||
wtimer3b_handler, /* 117 */
|
|
||||||
wtimer4a_handler, /* 118 */
|
|
||||||
wtimer4b_handler, /* 119 */
|
|
||||||
wtimer5a_handler, /* 120 */
|
|
||||||
wtimer5b_handler, /* 121 */
|
|
||||||
sysexc_handler, /* 122 */
|
|
||||||
peci0_handler, /* 123 */
|
|
||||||
lpc0_handler, /* 124 */
|
|
||||||
i2c4_handler, /* 125 */
|
|
||||||
i2c5_handler, /* 126 */
|
|
||||||
gpiom_handler, /* 127 */
|
|
||||||
gpion_handler, /* 128 */
|
|
||||||
0, /* 129 */
|
|
||||||
fan0_handler, /* 130 */
|
|
||||||
0, /* 131 */
|
|
||||||
gpiop0_handler, /* 132 */
|
|
||||||
gpiop1_handler, /* 133 */
|
|
||||||
gpiop2_handler, /* 134 */
|
|
||||||
gpiop3_handler, /* 135 */
|
|
||||||
gpiop4_handler, /* 136 */
|
|
||||||
gpiop5_handler, /* 137 */
|
|
||||||
gpiop6_handler, /* 138 */
|
|
||||||
gpiop7_handler, /* 139 */
|
|
||||||
gpioq0_handler, /* 140 */
|
|
||||||
gpioq1_handler, /* 141 */
|
|
||||||
gpioq2_handler, /* 142 */
|
|
||||||
gpioq3_handler, /* 143 */
|
|
||||||
gpioq4_handler, /* 144 */
|
|
||||||
gpioq5_handler, /* 145 */
|
|
||||||
gpioq6_handler, /* 146 */
|
|
||||||
gpioq7_handler, /* 147 */
|
|
||||||
0, /* 148 */
|
|
||||||
0, /* 149 */
|
|
||||||
pwm1_0_handler, /* 150 */
|
|
||||||
pwm1_1_handler, /* 151 */
|
|
||||||
pwm1_2_handler, /* 152 */
|
|
||||||
pwm1_3_handler, /* 153 */
|
|
||||||
pwm1_fault_handler, /* 154 */
|
|
||||||
};
|
|
||||||
|
|
||||||
void reset_handler(void)
|
|
||||||
{
|
|
||||||
volatile unsigned *src, *dest;
|
|
||||||
|
|
||||||
__asm__("MSR msp, %0" : : "r"(&_stack));
|
|
||||||
|
|
||||||
for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
|
|
||||||
*dest = *src;
|
|
||||||
|
|
||||||
while (dest < &_ebss)
|
|
||||||
*dest++ = 0;
|
|
||||||
|
|
||||||
/* Call the application's entry point. */
|
|
||||||
main();
|
|
||||||
}
|
|
||||||
|
|
||||||
void blocking_handler(void)
|
|
||||||
{
|
|
||||||
while (1) ;
|
|
||||||
}
|
|
||||||
|
|
||||||
void null_handler(void)
|
|
||||||
{
|
|
||||||
/* Do nothing. */
|
|
||||||
}
|
|
||||||
|
|
||||||
#pragma weak nmi_handler = null_handler
|
|
||||||
#pragma weak hard_fault_handler = blocking_handler
|
|
||||||
#pragma weak mem_manage_handler = blocking_handler
|
|
||||||
#pragma weak bus_fault_handler = blocking_handler
|
|
||||||
#pragma weak usage_fault_handler = blocking_handler
|
|
||||||
#pragma weak sv_call_handler = null_handler
|
|
||||||
#pragma weak debug_monitor_handler = null_handler
|
|
||||||
#pragma weak pend_sv_handler = null_handler
|
|
||||||
#pragma weak sys_tick_handler = null_handler
|
|
||||||
#pragma weak gpioa_handler = null_handler
|
|
||||||
#pragma weak gpiob_handler = null_handler
|
|
||||||
#pragma weak gpioc_handler = null_handler
|
|
||||||
#pragma weak gpiod_handler = null_handler
|
|
||||||
#pragma weak gpioe_handler = null_handler
|
|
||||||
#pragma weak uart0_handler = null_handler
|
|
||||||
#pragma weak uart1_handler = null_handler
|
|
||||||
#pragma weak ssi0_handler = null_handler
|
|
||||||
#pragma weak i2c0_handler = null_handler
|
|
||||||
#pragma weak pwm0_fault_handler = null_handler
|
|
||||||
#pragma weak pwm0_0_handler = null_handler
|
|
||||||
#pragma weak pwm0_1_handler = null_handler
|
|
||||||
#pragma weak pwm0_2_handler = null_handler
|
|
||||||
#pragma weak qei0_handler = null_handler
|
|
||||||
#pragma weak adc0ss0_handler = null_handler
|
|
||||||
#pragma weak adc0ss1_handler = null_handler
|
|
||||||
#pragma weak adc0ss2_handler = null_handler
|
|
||||||
#pragma weak adc0ss3_handler = null_handler
|
|
||||||
#pragma weak watchdog_handler = null_handler
|
|
||||||
#pragma weak timer0a_handler = null_handler
|
|
||||||
#pragma weak timer0b_handler = null_handler
|
|
||||||
#pragma weak timer1a_handler = null_handler
|
|
||||||
#pragma weak timer1b_handler = null_handler
|
|
||||||
#pragma weak timer2a_handler = null_handler
|
|
||||||
#pragma weak timer2b_handler = null_handler
|
|
||||||
#pragma weak comp0_handler = null_handler
|
|
||||||
#pragma weak comp1_handler = null_handler
|
|
||||||
#pragma weak comp2_handler = null_handler
|
|
||||||
#pragma weak sysctl_handler = null_handler
|
|
||||||
#pragma weak flash_handler = null_handler
|
|
||||||
#pragma weak gpiof_handler = null_handler
|
|
||||||
#pragma weak gpiog_handler = null_handler
|
|
||||||
#pragma weak gpioh_handler = null_handler
|
|
||||||
#pragma weak uart2_handler = null_handler
|
|
||||||
#pragma weak ssi1_handler = null_handler
|
|
||||||
#pragma weak timer3a_handler = null_handler
|
|
||||||
#pragma weak timer3b_handler = null_handler
|
|
||||||
#pragma weak i2c1_handler = null_handler
|
|
||||||
#pragma weak qei1_handler = null_handler
|
|
||||||
#pragma weak can0_handler = null_handler
|
|
||||||
#pragma weak can1_handler = null_handler
|
|
||||||
#pragma weak can2_handler = null_handler
|
|
||||||
#pragma weak eth_handler = null_handler
|
|
||||||
#pragma weak hibernate_handler = null_handler
|
|
||||||
#pragma weak usb0_handler = null_handler
|
|
||||||
#pragma weak pwm0_3_handler = null_handler
|
|
||||||
#pragma weak udma_handler = null_handler
|
|
||||||
#pragma weak udmaerr_handler = null_handler
|
|
||||||
#pragma weak adc1ss0_handler = null_handler
|
|
||||||
#pragma weak adc1ss1_handler = null_handler
|
|
||||||
#pragma weak adc1ss2_handler = null_handler
|
|
||||||
#pragma weak adc1ss3_handler = null_handler
|
|
||||||
#pragma weak i2s0_handler = null_handler
|
|
||||||
#pragma weak epi0_handler = null_handler
|
|
||||||
#pragma weak gpioj_handler = null_handler
|
|
||||||
#pragma weak gpiok_handler = null_handler
|
|
||||||
#pragma weak gpiol_handler = null_handler
|
|
||||||
#pragma weak ssi2_handler = null_handler
|
|
||||||
#pragma weak ssi3_handler = null_handler
|
|
||||||
#pragma weak uart3_handler = null_handler
|
|
||||||
#pragma weak uart4_handler = null_handler
|
|
||||||
#pragma weak uart5_handler = null_handler
|
|
||||||
#pragma weak uart6_handler = null_handler
|
|
||||||
#pragma weak uart7_handler = null_handler
|
|
||||||
#pragma weak i2c2_handler = null_handler
|
|
||||||
#pragma weak i2c3_handler = null_handler
|
|
||||||
#pragma weak timer4a_handler = null_handler
|
|
||||||
#pragma weak timer4b_handler = null_handler
|
|
||||||
#pragma weak timer5a_handler = null_handler
|
|
||||||
#pragma weak timer5b_handler = null_handler
|
|
||||||
#pragma weak wtimer0a_handler = null_handler
|
|
||||||
#pragma weak wtimer0b_handler = null_handler
|
|
||||||
#pragma weak wtimer1a_handler = null_handler
|
|
||||||
#pragma weak wtimer1b_handler = null_handler
|
|
||||||
#pragma weak wtimer2a_handler = null_handler
|
|
||||||
#pragma weak wtimer2b_handler = null_handler
|
|
||||||
#pragma weak wtimer3a_handler = null_handler
|
|
||||||
#pragma weak wtimer3b_handler = null_handler
|
|
||||||
#pragma weak wtimer4a_handler = null_handler
|
|
||||||
#pragma weak wtimer4b_handler = null_handler
|
|
||||||
#pragma weak wtimer5a_handler = null_handler
|
|
||||||
#pragma weak wtimer5b_handler = null_handler
|
|
||||||
#pragma weak sysexc_handler = null_handler
|
|
||||||
#pragma weak peci0_handler = null_handler
|
|
||||||
#pragma weak lpc0_handler = null_handler
|
|
||||||
#pragma weak i2c4_handler = null_handler
|
|
||||||
#pragma weak i2c5_handler = null_handler
|
|
||||||
#pragma weak gpiom_handler = null_handler
|
|
||||||
#pragma weak gpion_handler = null_handler
|
|
||||||
#pragma weak fan0_handler = null_handler
|
|
||||||
#pragma weak gpiop0_handler = null_handler
|
|
||||||
#pragma weak gpiop1_handler = null_handler
|
|
||||||
#pragma weak gpiop2_handler = null_handler
|
|
||||||
#pragma weak gpiop3_handler = null_handler
|
|
||||||
#pragma weak gpiop4_handler = null_handler
|
|
||||||
#pragma weak gpiop5_handler = null_handler
|
|
||||||
#pragma weak gpiop6_handler = null_handler
|
|
||||||
#pragma weak gpiop7_handler = null_handler
|
|
||||||
#pragma weak gpioq0_handler = null_handler
|
|
||||||
#pragma weak gpioq1_handler = null_handler
|
|
||||||
#pragma weak gpioq2_handler = null_handler
|
|
||||||
#pragma weak gpioq3_handler = null_handler
|
|
||||||
#pragma weak gpioq4_handler = null_handler
|
|
||||||
#pragma weak gpioq5_handler = null_handler
|
|
||||||
#pragma weak gpioq6_handler = null_handler
|
|
||||||
#pragma weak gpioq7_handler = null_handler
|
|
||||||
#pragma weak pwm1_0_handler = null_handler
|
|
||||||
#pragma weak pwm1_1_handler = null_handler
|
|
||||||
#pragma weak pwm1_2_handler = null_handler
|
|
||||||
#pragma weak pwm1_3_handler = null_handler
|
|
||||||
#pragma weak pwm1_fault_handler = null_handler
|
|
||||||
@ -25,10 +25,10 @@ CC = $(PREFIX)-gcc
|
|||||||
AR = $(PREFIX)-ar
|
AR = $(PREFIX)-ar
|
||||||
CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \
|
CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \
|
||||||
-mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
|
-mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
|
||||||
-ffunction-sections -fdata-sections -MD
|
-ffunction-sections -fdata-sections -MD -DLPC13XX
|
||||||
# ARFLAGS = rcsv
|
# ARFLAGS = rcsv
|
||||||
ARFLAGS = rcs
|
ARFLAGS = rcs
|
||||||
OBJS = gpio.o assert.o
|
OBJS = gpio.o
|
||||||
|
|
||||||
VPATH += ../cm3
|
VPATH += ../cm3
|
||||||
|
|
||||||
|
|||||||
@ -25,10 +25,10 @@ CC = $(PREFIX)-gcc
|
|||||||
AR = $(PREFIX)-ar
|
AR = $(PREFIX)-ar
|
||||||
CFLAGS = -O0 -g -Wall -Wextra -I../../include -fno-common \
|
CFLAGS = -O0 -g -Wall -Wextra -I../../include -fno-common \
|
||||||
-mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
|
-mcpu=cortex-m3 -mthumb -Wstrict-prototypes \
|
||||||
-ffunction-sections -fdata-sections -MD
|
-ffunction-sections -fdata-sections -MD -DLPC17XX
|
||||||
# ARFLAGS = rcsv
|
# ARFLAGS = rcsv
|
||||||
ARFLAGS = rcs
|
ARFLAGS = rcs
|
||||||
OBJS = gpio.o vector.o assert.o
|
OBJS = gpio.o
|
||||||
|
|
||||||
VPATH += ../cm3
|
VPATH += ../cm3
|
||||||
|
|
||||||
|
|||||||
@ -28,11 +28,10 @@ AR = $(PREFIX)-ar
|
|||||||
CFLAGS = -O2 -g3 -Wall -Wextra -I../../include -fno-common \
|
CFLAGS = -O2 -g3 -Wall -Wextra -I../../include -fno-common \
|
||||||
-mcpu=cortex-m4 -mthumb -Wstrict-prototypes \
|
-mcpu=cortex-m4 -mthumb -Wstrict-prototypes \
|
||||||
-ffunction-sections -fdata-sections -MD \
|
-ffunction-sections -fdata-sections -MD \
|
||||||
-mfloat-abi=hard -mfpu=fpv4-sp-d16
|
-mfloat-abi=hard -mfpu=fpv4-sp-d16 -DLPC43XX
|
||||||
# ARFLAGS = rcsv
|
# ARFLAGS = rcsv
|
||||||
ARFLAGS = rcs
|
ARFLAGS = rcs
|
||||||
OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o \
|
OBJS = gpio.o scu.o i2c.o ssp.o
|
||||||
assert.o
|
|
||||||
|
|
||||||
VPATH += ../cm3
|
VPATH += ../cm3
|
||||||
|
|
||||||
|
|||||||
@ -1,76 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
|
||||||
* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
|
|
||||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
#include <libopencm3/cm3/scs.h>
|
|
||||||
#include <libopencm3/lpc43xx/nvic.h>
|
|
||||||
|
|
||||||
void nvic_enable_irq(u8 irqn)
|
|
||||||
{
|
|
||||||
NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
|
|
||||||
}
|
|
||||||
|
|
||||||
void nvic_disable_irq(u8 irqn)
|
|
||||||
{
|
|
||||||
NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
|
|
||||||
}
|
|
||||||
|
|
||||||
u8 nvic_get_pending_irq(u8 irqn)
|
|
||||||
{
|
|
||||||
return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
void nvic_set_pending_irq(u8 irqn)
|
|
||||||
{
|
|
||||||
NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
|
|
||||||
}
|
|
||||||
|
|
||||||
void nvic_clear_pending_irq(u8 irqn)
|
|
||||||
{
|
|
||||||
NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
|
|
||||||
}
|
|
||||||
|
|
||||||
u8 nvic_get_active_irq(u8 irqn)
|
|
||||||
{
|
|
||||||
return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
u8 nvic_get_irq_enabled(u8 irqn)
|
|
||||||
{
|
|
||||||
return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
void nvic_set_priority(u8 irqn, u8 priority)
|
|
||||||
{
|
|
||||||
if(irqn>NVIC_M4_QEI_IRQ)
|
|
||||||
{
|
|
||||||
/* Cortex-M system interrupts */
|
|
||||||
SCS_SHPR( (irqn&0xF)-4 ) = priority;
|
|
||||||
}else
|
|
||||||
{
|
|
||||||
/* Device specific interrupts */
|
|
||||||
NVIC_IPR(irqn) = priority;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void nvic_generate_software_interrupt(u8 irqn)
|
|
||||||
{
|
|
||||||
if (irqn <= 239)
|
|
||||||
NVIC_STIR |= irqn;
|
|
||||||
}
|
|
||||||
@ -1,69 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
|
||||||
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <libopencm3/lpc43xx/systick.h>
|
|
||||||
|
|
||||||
void systick_set_reload(u32 value)
|
|
||||||
{
|
|
||||||
STK_LOAD = (value & 0x00FFFFFF);
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 systick_get_value(void)
|
|
||||||
{
|
|
||||||
return STK_VAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
void systick_set_clocksource(u8 clocksource)
|
|
||||||
{
|
|
||||||
STK_CTRL |= clocksource;
|
|
||||||
}
|
|
||||||
|
|
||||||
void systick_interrupt_enable(void)
|
|
||||||
{
|
|
||||||
STK_CTRL |= STK_CTRL_TICKINT;
|
|
||||||
}
|
|
||||||
|
|
||||||
void systick_interrupt_disable(void)
|
|
||||||
{
|
|
||||||
STK_CTRL &= ~STK_CTRL_TICKINT;
|
|
||||||
}
|
|
||||||
|
|
||||||
void systick_counter_enable(void)
|
|
||||||
{
|
|
||||||
STK_CTRL |= STK_CTRL_ENABLE;
|
|
||||||
}
|
|
||||||
|
|
||||||
void systick_counter_disable(void)
|
|
||||||
{
|
|
||||||
STK_CTRL &= ~STK_CTRL_ENABLE;
|
|
||||||
}
|
|
||||||
|
|
||||||
u8 systick_get_countflag(void)
|
|
||||||
{
|
|
||||||
if (STK_CTRL & STK_CTRL_COUNTFLAG)
|
|
||||||
return 1;
|
|
||||||
else
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
u32 systick_get_calib(void)
|
|
||||||
{
|
|
||||||
return (STK_CALIB&0x00FFFFFF);
|
|
||||||
}
|
|
||||||
@ -1,264 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
|
||||||
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define WEAK __attribute__ ((weak))
|
|
||||||
|
|
||||||
/* Symbols exported by the linker script(s): */
|
|
||||||
extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
|
|
||||||
extern unsigned _etext_ram, _text_ram, _etext_rom;
|
|
||||||
|
|
||||||
void main(void);
|
|
||||||
void reset_handler(void);
|
|
||||||
void blocking_handler(void);
|
|
||||||
void null_handler(void);
|
|
||||||
|
|
||||||
void WEAK nmi_handler(void);
|
|
||||||
void WEAK hard_fault_handler(void);
|
|
||||||
void WEAK mem_manage_handler(void);
|
|
||||||
void WEAK bus_fault_handler(void);
|
|
||||||
void WEAK usage_fault_handler(void);
|
|
||||||
void WEAK sv_call_handler(void);
|
|
||||||
void WEAK debug_monitor_handler(void);
|
|
||||||
void WEAK pend_sv_handler(void);
|
|
||||||
void WEAK sys_tick_handler(void);
|
|
||||||
void WEAK dac_irqhandler(void);
|
|
||||||
void WEAK m0core_irqhandler(void);
|
|
||||||
void WEAK dma_irqhandler(void);
|
|
||||||
void WEAK ethernet_irqhandler(void);
|
|
||||||
void WEAK sdio_irqhandler(void);
|
|
||||||
void WEAK lcd_irqhandler(void);
|
|
||||||
void WEAK usb0_irqhandler(void);
|
|
||||||
void WEAK usb1_irqhandler(void);
|
|
||||||
void WEAK sct_irqhandler(void);
|
|
||||||
void WEAK ritimer_irqhandler(void);
|
|
||||||
void WEAK timer0_irqhandler(void);
|
|
||||||
void WEAK timer1_irqhandler(void);
|
|
||||||
void WEAK timer2_irqhandler(void);
|
|
||||||
void WEAK timer3_irqhandler(void);
|
|
||||||
void WEAK mcpwm_irqhandler(void);
|
|
||||||
void WEAK adc0_irqhandler(void);
|
|
||||||
void WEAK i2c0_irqhandler(void);
|
|
||||||
void WEAK i2c1_irqhandler(void);
|
|
||||||
void WEAK spi_irqhandler(void);
|
|
||||||
void WEAK adc1_irqhandler(void);
|
|
||||||
void WEAK ssp0_irqhandler(void);
|
|
||||||
void WEAK ssp1_irqhandler(void);
|
|
||||||
void WEAK usart0_irqhandler(void);
|
|
||||||
void WEAK uart1_irqhandler(void);
|
|
||||||
void WEAK usart2_irqhandler(void);
|
|
||||||
void WEAK usart3_irqhandler(void);
|
|
||||||
void WEAK i2s0_irqhandler(void);
|
|
||||||
void WEAK i2s1_irqhandler(void);
|
|
||||||
void WEAK spifi_irqhandler(void);
|
|
||||||
void WEAK sgpio_irqhandler(void);
|
|
||||||
void WEAK pin_int0_irqhandler(void);
|
|
||||||
void WEAK pin_int1_irqhandler(void);
|
|
||||||
void WEAK pin_int2_irqhandler(void);
|
|
||||||
void WEAK pin_int3_irqhandler(void);
|
|
||||||
void WEAK pin_int4_irqhandler(void);
|
|
||||||
void WEAK pin_int5_irqhandler(void);
|
|
||||||
void WEAK pin_int6_irqhandler(void);
|
|
||||||
void WEAK pin_int7_irqhandler(void);
|
|
||||||
void WEAK gint0_irqhandler(void);
|
|
||||||
void WEAK gint1_irqhandler(void);
|
|
||||||
void WEAK eventrouter_irqhandler(void);
|
|
||||||
void WEAK c_can1_irqhandler(void);
|
|
||||||
void WEAK atimer_irqhandler(void);
|
|
||||||
void WEAK rtc_irqhandler(void);
|
|
||||||
void WEAK wwdt_irqhandler(void);
|
|
||||||
void WEAK c_can0_irqhandler(void);
|
|
||||||
void WEAK qei_irqhandler(void);
|
|
||||||
|
|
||||||
__attribute__ ((section(".vectors")))
|
|
||||||
void (*const vector_table[]) (void) = {
|
|
||||||
/* Cortex-M4 interrupts */
|
|
||||||
(void*)&_stack,
|
|
||||||
reset_handler,
|
|
||||||
nmi_handler,
|
|
||||||
hard_fault_handler,
|
|
||||||
mem_manage_handler,
|
|
||||||
bus_fault_handler,
|
|
||||||
usage_fault_handler,
|
|
||||||
0, 0, 0, 0, /* reserved */
|
|
||||||
sv_call_handler,
|
|
||||||
debug_monitor_handler,
|
|
||||||
0, /* reserved */
|
|
||||||
pend_sv_handler,
|
|
||||||
sys_tick_handler,
|
|
||||||
|
|
||||||
/* LPC43xx interrupts */
|
|
||||||
dac_irqhandler,
|
|
||||||
m0core_irqhandler,
|
|
||||||
dma_irqhandler,
|
|
||||||
0, /* reserved */
|
|
||||||
0, /* reserved */
|
|
||||||
ethernet_irqhandler,
|
|
||||||
sdio_irqhandler,
|
|
||||||
lcd_irqhandler,
|
|
||||||
usb0_irqhandler,
|
|
||||||
usb1_irqhandler,
|
|
||||||
sct_irqhandler,
|
|
||||||
ritimer_irqhandler,
|
|
||||||
timer0_irqhandler,
|
|
||||||
timer1_irqhandler,
|
|
||||||
timer2_irqhandler,
|
|
||||||
timer3_irqhandler,
|
|
||||||
mcpwm_irqhandler,
|
|
||||||
adc0_irqhandler,
|
|
||||||
i2c0_irqhandler,
|
|
||||||
i2c1_irqhandler,
|
|
||||||
spi_irqhandler,
|
|
||||||
adc1_irqhandler,
|
|
||||||
ssp0_irqhandler,
|
|
||||||
ssp1_irqhandler,
|
|
||||||
usart0_irqhandler,
|
|
||||||
uart1_irqhandler,
|
|
||||||
usart2_irqhandler,
|
|
||||||
usart3_irqhandler,
|
|
||||||
i2s0_irqhandler,
|
|
||||||
i2s1_irqhandler,
|
|
||||||
spifi_irqhandler,
|
|
||||||
sgpio_irqhandler,
|
|
||||||
pin_int0_irqhandler,
|
|
||||||
pin_int1_irqhandler,
|
|
||||||
pin_int2_irqhandler,
|
|
||||||
pin_int3_irqhandler,
|
|
||||||
pin_int4_irqhandler,
|
|
||||||
pin_int5_irqhandler,
|
|
||||||
pin_int6_irqhandler,
|
|
||||||
pin_int7_irqhandler,
|
|
||||||
gint0_irqhandler,
|
|
||||||
gint1_irqhandler,
|
|
||||||
eventrouter_irqhandler,
|
|
||||||
c_can1_irqhandler,
|
|
||||||
0, /* reserved */
|
|
||||||
0, /* reserved */
|
|
||||||
atimer_irqhandler,
|
|
||||||
rtc_irqhandler,
|
|
||||||
0, /* reserved */
|
|
||||||
wwdt_irqhandler,
|
|
||||||
0, /* reserved */
|
|
||||||
c_can0_irqhandler,
|
|
||||||
qei_irqhandler,
|
|
||||||
};
|
|
||||||
|
|
||||||
#define MMIO32(addr) (*(volatile unsigned long*)(addr))
|
|
||||||
#define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) )
|
|
||||||
|
|
||||||
void reset_handler(void)
|
|
||||||
{
|
|
||||||
volatile unsigned *src, *dest;
|
|
||||||
|
|
||||||
__asm__("MSR msp, %0" : : "r"(&_stack));
|
|
||||||
|
|
||||||
/* Copy the code from ROM to Real RAM (if enabled) */
|
|
||||||
if( (&_etext_ram-&_text_ram) > 0 )
|
|
||||||
{
|
|
||||||
src = &_etext_rom-(&_etext_ram-&_text_ram);
|
|
||||||
/* Change Shadow memory to ROM (for Debug Purpose in case Boot has not set correctly the M4MEMMAP because of debug) */
|
|
||||||
CREG_M4MEMMAP = (unsigned long)src;
|
|
||||||
|
|
||||||
for(dest = &_text_ram; dest < &_etext_ram; )
|
|
||||||
{
|
|
||||||
*dest++ = *src++;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Change Shadow memory to Real RAM */
|
|
||||||
CREG_M4MEMMAP = (unsigned long)&_text_ram;
|
|
||||||
|
|
||||||
/* Continue Execution in RAM */
|
|
||||||
}
|
|
||||||
|
|
||||||
for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
|
|
||||||
*dest = *src;
|
|
||||||
|
|
||||||
while (dest < &_ebss)
|
|
||||||
*dest++ = 0;
|
|
||||||
|
|
||||||
/* Call the application's entry point. */
|
|
||||||
main();
|
|
||||||
}
|
|
||||||
|
|
||||||
void blocking_handler(void)
|
|
||||||
{
|
|
||||||
while (1) ;
|
|
||||||
}
|
|
||||||
|
|
||||||
void null_handler(void)
|
|
||||||
{
|
|
||||||
/* Do nothing. */
|
|
||||||
}
|
|
||||||
|
|
||||||
#pragma weak nmi_handler = null_handler
|
|
||||||
#pragma weak hard_fault_handler = blocking_handler
|
|
||||||
#pragma weak mem_manage_handler = blocking_handler
|
|
||||||
#pragma weak bus_fault_handler = blocking_handler
|
|
||||||
#pragma weak usage_fault_handler = blocking_handler
|
|
||||||
#pragma weak sv_call_handler = null_handler
|
|
||||||
#pragma weak debug_monitor_handler = null_handler
|
|
||||||
#pragma weak pend_sv_handler = null_handler
|
|
||||||
#pragma weak sys_tick_handler = null_handler
|
|
||||||
#pragma weak dac_irqhandler = null_handler
|
|
||||||
#pragma weak m0core_irqhandler = null_handler
|
|
||||||
#pragma weak dma_irqhandler = null_handler
|
|
||||||
#pragma weak ethernet_irqhandler = null_handler
|
|
||||||
#pragma weak sdio_irqhandler = null_handler
|
|
||||||
#pragma weak lcd_irqhandler = null_handler
|
|
||||||
#pragma weak usb0_irqhandler = null_handler
|
|
||||||
#pragma weak usb1_irqhandler = null_handler
|
|
||||||
#pragma weak sct_irqhandler = null_handler
|
|
||||||
#pragma weak ritimer_irqhandler = null_handler
|
|
||||||
#pragma weak timer0_irqhandler = null_handler
|
|
||||||
#pragma weak timer1_irqhandler = null_handler
|
|
||||||
#pragma weak timer2_irqhandler = null_handler
|
|
||||||
#pragma weak timer3_irqhandler = null_handler
|
|
||||||
#pragma weak mcpwm_irqhandler = null_handler
|
|
||||||
#pragma weak adc0_irqhandler = null_handler
|
|
||||||
#pragma weak i2c0_irqhandler = null_handler
|
|
||||||
#pragma weak i2c1_irqhandler = null_handler
|
|
||||||
#pragma weak spi_irqhandler = null_handler
|
|
||||||
#pragma weak adc1_irqhandler = null_handler
|
|
||||||
#pragma weak ssp0_irqhandler = null_handler
|
|
||||||
#pragma weak ssp1_irqhandler = null_handler
|
|
||||||
#pragma weak usart0_irqhandler = null_handler
|
|
||||||
#pragma weak uart1_irqhandler = null_handler
|
|
||||||
#pragma weak usart2_irqhandler = null_handler
|
|
||||||
#pragma weak usart3_irqhandler = null_handler
|
|
||||||
#pragma weak i2s0_irqhandler = null_handler
|
|
||||||
#pragma weak i2s1_irqhandler = null_handler
|
|
||||||
#pragma weak spifi_irqhandler = null_handler
|
|
||||||
#pragma weak sgpio_irqhandler = null_handler
|
|
||||||
#pragma weak pin_int0_irqhandler = null_handler
|
|
||||||
#pragma weak pin_int1_irqhandler = null_handler
|
|
||||||
#pragma weak pin_int2_irqhandler = null_handler
|
|
||||||
#pragma weak pin_int3_irqhandler = null_handler
|
|
||||||
#pragma weak pin_int4_irqhandler = null_handler
|
|
||||||
#pragma weak pin_int5_irqhandler = null_handler
|
|
||||||
#pragma weak pin_int6_irqhandler = null_handler
|
|
||||||
#pragma weak pin_int7_irqhandler = null_handler
|
|
||||||
#pragma weak gint0_irqhandler = null_handler
|
|
||||||
#pragma weak gint1_irqhandler = null_handler
|
|
||||||
#pragma weak eventrouter_irqhandler = null_handler
|
|
||||||
#pragma weak c_can1_irqhandler = null_handler
|
|
||||||
#pragma weak atimer_irqhandler = null_handler
|
|
||||||
#pragma weak rtc_irqhandler = null_handler
|
|
||||||
#pragma weak wwdt_irqhandler = null_handler
|
|
||||||
#pragma weak c_can0_irqhandler = null_handler
|
|
||||||
#pragma weak qei_irqhandler = null_handler
|
|
||||||
48
lib/lpc43xx/vector_chipset.c
Normal file
48
lib/lpc43xx/vector_chipset.c
Normal file
@ -0,0 +1,48 @@
|
|||||||
|
/*
|
||||||
|
* This file is part of the libopencm3 project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||||
|
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
|
||||||
|
*
|
||||||
|
* This library is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This library is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU Lesser General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <libopencm3/cm3/common.h>
|
||||||
|
|
||||||
|
extern unsigned _etext_ram, _text_ram, _etext_rom;
|
||||||
|
|
||||||
|
#define CREG_M4MEMMAP MMIO32( (0x40043000 + 0x100) )
|
||||||
|
|
||||||
|
static void pre_main(void)
|
||||||
|
{
|
||||||
|
volatile unsigned *src, *dest;
|
||||||
|
|
||||||
|
/* Copy the code from ROM to Real RAM (if enabled) */
|
||||||
|
if( (&_etext_ram-&_text_ram) > 0 )
|
||||||
|
{
|
||||||
|
src = &_etext_rom-(&_etext_ram-&_text_ram);
|
||||||
|
/* Change Shadow memory to ROM (for Debug Purpose in case Boot has not set correctly the M4MEMMAP because of debug) */
|
||||||
|
CREG_M4MEMMAP = (unsigned long)src;
|
||||||
|
|
||||||
|
for(dest = &_text_ram; dest < &_etext_ram; )
|
||||||
|
{
|
||||||
|
*dest++ = *src++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Change Shadow memory to Real RAM */
|
||||||
|
CREG_M4MEMMAP = (unsigned long)&_text_ram;
|
||||||
|
|
||||||
|
/* Continue Execution in RAM */
|
||||||
|
}
|
||||||
|
}
|
||||||
@ -28,10 +28,10 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
|
|||||||
-ffunction-sections -fdata-sections -MD -DSTM32F1
|
-ffunction-sections -fdata-sections -MD -DSTM32F1
|
||||||
# ARFLAGS = rcsv
|
# ARFLAGS = rcsv
|
||||||
ARFLAGS = rcs
|
ARFLAGS = rcs
|
||||||
OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \
|
OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o \
|
||||||
rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \
|
rtc.o i2c.o dma.o exti.o ethernet.o \
|
||||||
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
|
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
|
||||||
timer.o usb_f107.o desig.o crc.o assert.o dac.o iwdg.o pwr.o
|
timer.o usb_f107.o desig.o crc.o dac.o iwdg.o pwr.o
|
||||||
|
|
||||||
VPATH += ../../usb:../:../../cm3
|
VPATH += ../../usb:../:../../cm3
|
||||||
|
|
||||||
|
|||||||
@ -1,296 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define WEAK __attribute__ ((weak))
|
|
||||||
|
|
||||||
/* Symbols exported by the linker script(s): */
|
|
||||||
extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
|
|
||||||
|
|
||||||
void main(void);
|
|
||||||
void reset_handler(void);
|
|
||||||
void blocking_handler(void);
|
|
||||||
void null_handler(void);
|
|
||||||
|
|
||||||
void WEAK nmi_handler(void);
|
|
||||||
void WEAK hard_fault_handler(void);
|
|
||||||
void WEAK mem_manage_handler(void);
|
|
||||||
void WEAK bus_fault_handler(void);
|
|
||||||
void WEAK usage_fault_handler(void);
|
|
||||||
void WEAK sv_call_handler(void);
|
|
||||||
void WEAK debug_monitor_handler(void);
|
|
||||||
void WEAK pend_sv_handler(void);
|
|
||||||
void WEAK sys_tick_handler(void);
|
|
||||||
void WEAK wwdg_isr(void);
|
|
||||||
void WEAK pvd_isr(void);
|
|
||||||
void WEAK tamper_isr(void);
|
|
||||||
void WEAK rtc_isr(void);
|
|
||||||
void WEAK flash_isr(void);
|
|
||||||
void WEAK rcc_isr(void);
|
|
||||||
void WEAK exti0_isr(void);
|
|
||||||
void WEAK exti1_isr(void);
|
|
||||||
void WEAK exti2_isr(void);
|
|
||||||
void WEAK exti3_isr(void);
|
|
||||||
void WEAK exti4_isr(void);
|
|
||||||
void WEAK dma1_channel1_isr(void);
|
|
||||||
void WEAK dma1_channel2_isr(void);
|
|
||||||
void WEAK dma1_channel3_isr(void);
|
|
||||||
void WEAK dma1_channel4_isr(void);
|
|
||||||
void WEAK dma1_channel5_isr(void);
|
|
||||||
void WEAK dma1_channel6_isr(void);
|
|
||||||
void WEAK dma1_channel7_isr(void);
|
|
||||||
void WEAK adc1_2_isr(void);
|
|
||||||
void WEAK usb_hp_can_tx_isr(void);
|
|
||||||
void WEAK usb_lp_can_rx0_isr(void);
|
|
||||||
void WEAK can_rx1_isr(void);
|
|
||||||
void WEAK can_sce_isr(void);
|
|
||||||
void WEAK exti9_5_isr(void);
|
|
||||||
void WEAK tim1_brk_isr(void);
|
|
||||||
void WEAK tim1_up_isr(void);
|
|
||||||
void WEAK tim1_trg_com_isr(void);
|
|
||||||
void WEAK tim1_cc_isr(void);
|
|
||||||
void WEAK tim2_isr(void);
|
|
||||||
void WEAK tim3_isr(void);
|
|
||||||
void WEAK tim4_isr(void);
|
|
||||||
void WEAK i2c1_ev_isr(void);
|
|
||||||
void WEAK i2c1_er_isr(void);
|
|
||||||
void WEAK i2c2_ev_isr(void);
|
|
||||||
void WEAK i2c2_er_isr(void);
|
|
||||||
void WEAK spi1_isr(void);
|
|
||||||
void WEAK spi2_isr(void);
|
|
||||||
void WEAK usart1_isr(void);
|
|
||||||
void WEAK usart2_isr(void);
|
|
||||||
void WEAK usart3_isr(void);
|
|
||||||
void WEAK exti15_10_isr(void);
|
|
||||||
void WEAK rtc_alarm_isr(void);
|
|
||||||
void WEAK usb_wakeup_isr(void);
|
|
||||||
void WEAK tim8_brk_isr(void);
|
|
||||||
void WEAK tim8_up_isr(void);
|
|
||||||
void WEAK tim8_trg_com_isr(void);
|
|
||||||
void WEAK tim8_cc_isr(void);
|
|
||||||
void WEAK adc3_isr(void);
|
|
||||||
void WEAK fsmc_isr(void);
|
|
||||||
void WEAK sdio_isr(void);
|
|
||||||
void WEAK tim5_isr(void);
|
|
||||||
void WEAK spi3_isr(void);
|
|
||||||
void WEAK uart4_isr(void);
|
|
||||||
void WEAK uart5_isr(void);
|
|
||||||
void WEAK tim6_isr(void);
|
|
||||||
void WEAK tim7_isr(void);
|
|
||||||
void WEAK dma2_channel1_isr(void);
|
|
||||||
void WEAK dma2_channel2_isr(void);
|
|
||||||
void WEAK dma2_channel3_isr(void);
|
|
||||||
void WEAK dma2_channel4_5_isr(void);
|
|
||||||
void WEAK dma2_channel5_isr(void);
|
|
||||||
void WEAK eth_isr(void);
|
|
||||||
void WEAK eth_wkup_isr(void);
|
|
||||||
void WEAK can2_tx_isr(void);
|
|
||||||
void WEAK can2_rx0_isr(void);
|
|
||||||
void WEAK can2_rx1_isr(void);
|
|
||||||
void WEAK can2_sce_isr(void);
|
|
||||||
void WEAK otg_fs_isr(void);
|
|
||||||
|
|
||||||
|
|
||||||
__attribute__ ((section(".vectors")))
|
|
||||||
void (*const vector_table[]) (void) = {
|
|
||||||
(void*)&_stack, /* Addr: 0x0000_0000 */
|
|
||||||
reset_handler, /* Addr: 0x0000_0004 */
|
|
||||||
nmi_handler, /* Addr: 0x0000_0008 */
|
|
||||||
hard_fault_handler, /* Addr: 0x0000_000C */
|
|
||||||
mem_manage_handler, /* Addr: 0x0000_0010 */
|
|
||||||
bus_fault_handler, /* Addr: 0x0000_0014 */
|
|
||||||
usage_fault_handler, /* Addr: 0x0000_0018 */
|
|
||||||
0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */
|
|
||||||
sv_call_handler, /* Addr: 0x0000_002C */
|
|
||||||
debug_monitor_handler, /* Addr: 0x0000_0030*/
|
|
||||||
0, /* Reserved Addr: 0x0000_00034 */
|
|
||||||
pend_sv_handler, /* Addr: 0x0000_0038 */
|
|
||||||
sys_tick_handler, /* Addr: 0x0000_003C */
|
|
||||||
wwdg_isr, /* Addr: 0x0000_0040 */
|
|
||||||
pvd_isr, /* Addr: 0x0000_0044 */
|
|
||||||
tamper_isr, /* Addr: 0x0000_0048 */
|
|
||||||
rtc_isr, /* Addr: 0x0000_004C */
|
|
||||||
flash_isr, /* Addr: 0x0000_0050 */
|
|
||||||
rcc_isr, /* Addr: 0x0000_0054 */
|
|
||||||
exti0_isr, /* Addr: 0x0000_0058 */
|
|
||||||
exti1_isr, /* Addr: 0x0000_005C */
|
|
||||||
exti2_isr, /* Addr: 0x0000_0060 */
|
|
||||||
exti3_isr, /* Addr: 0x0000_0064 */
|
|
||||||
exti4_isr, /* Addr: 0x0000_0068 */
|
|
||||||
dma1_channel1_isr, /* Addr: 0x0000_006C */
|
|
||||||
dma1_channel2_isr, /* Addr: 0x0000_0070 */
|
|
||||||
dma1_channel3_isr, /* Addr: 0x0000_0074 */
|
|
||||||
dma1_channel4_isr, /* Addr: 0x0000_0078 */
|
|
||||||
dma1_channel5_isr, /* Addr: 0x0000_007C */
|
|
||||||
dma1_channel6_isr, /* Addr: 0x0000_0080 */
|
|
||||||
dma1_channel7_isr, /* Addr: 0x0000_0084 */
|
|
||||||
adc1_2_isr, /* Addr: 0x0000_0088 */
|
|
||||||
usb_hp_can_tx_isr, /* Addr: 0x0000_008C */
|
|
||||||
usb_lp_can_rx0_isr, /* Addr: 0x0000_0090 */
|
|
||||||
can_rx1_isr, /* Addr: 0x0000_0094 */
|
|
||||||
can_sce_isr, /* Addr: 0x0000_0098 */
|
|
||||||
exti9_5_isr, /* Addr: 0x0000_009C */
|
|
||||||
tim1_brk_isr, /* Addr: 0x0000_00A0 */
|
|
||||||
tim1_up_isr, /* Addr: 0x0000_00A4 */
|
|
||||||
tim1_trg_com_isr, /* Addr: 0x0000_00A8 */
|
|
||||||
tim1_cc_isr, /* Addr: 0x0000_00AC */
|
|
||||||
tim2_isr, /* Addr: 0x0000_00B0 */
|
|
||||||
tim3_isr, /* Addr: 0x0000_00B4 */
|
|
||||||
tim4_isr, /* Addr: 0x0000_00B8 */
|
|
||||||
i2c1_ev_isr, /* Addr: 0x0000_00BC */
|
|
||||||
i2c1_er_isr, /* Addr: 0x0000_00C0 */
|
|
||||||
i2c2_ev_isr, /* Addr: 0x0000_00C4 */
|
|
||||||
i2c2_er_isr, /* Addr: 0x0000_00C8 */
|
|
||||||
spi1_isr, /* Addr: 0x0000_00CC */
|
|
||||||
spi2_isr, /* Addr: 0x0000_00D0 */
|
|
||||||
usart1_isr, /* Addr: 0x0000_00D4 */
|
|
||||||
usart2_isr, /* Addr: 0x0000_00D8 */
|
|
||||||
usart3_isr, /* Addr: 0x0000_00DC */
|
|
||||||
exti15_10_isr, /* Addr: 0x0000_00E0 */
|
|
||||||
rtc_alarm_isr, /* Addr: 0x0000_00E4 */
|
|
||||||
usb_wakeup_isr, /* Addr: 0x0000_00E8 */
|
|
||||||
tim8_brk_isr, /* Addr: 0x0000_00EC */
|
|
||||||
tim8_up_isr, /* Addr: 0x0000_00F0 */
|
|
||||||
tim8_trg_com_isr, /* Addr: 0x0000_00F4 */
|
|
||||||
tim8_cc_isr, /* Addr: 0x0000_00F8 */
|
|
||||||
adc3_isr, /* Addr: 0x0000_00FC */
|
|
||||||
fsmc_isr, /* Addr: 0x0000_0100 */
|
|
||||||
sdio_isr, /* Addr: 0x0000_0104 */
|
|
||||||
tim5_isr, /* Addr: 0x0000_0108 */
|
|
||||||
spi3_isr, /* Addr: 0x0000_010C */
|
|
||||||
uart4_isr, /* Addr: 0x0000_0110 */
|
|
||||||
uart5_isr, /* Addr: 0x0000_0114 */
|
|
||||||
tim6_isr, /* Addr: 0x0000_0118 */
|
|
||||||
tim7_isr, /* Addr: 0x0000_011C */
|
|
||||||
dma2_channel1_isr, /* Addr: 0x0000_0120 */
|
|
||||||
dma2_channel2_isr, /* Addr: 0x0000_0124 */
|
|
||||||
dma2_channel3_isr, /* Addr: 0x0000_0128 */
|
|
||||||
dma2_channel4_5_isr, /* Addr: 0x0000_012C */
|
|
||||||
dma2_channel5_isr, /* Addr: 0x0000_0130 */
|
|
||||||
eth_isr, /* Addr: 0x0000_0134 */
|
|
||||||
eth_wkup_isr, /* Addr: 0x0000_0138 */
|
|
||||||
can2_tx_isr, /* Addr: 0x0000_013C */
|
|
||||||
can2_rx0_isr, /* Addr: 0x0000_0140 */
|
|
||||||
can2_rx1_isr, /* Addr: 0x0000_0144 */
|
|
||||||
can2_sce_isr, /* Addr: 0x0000_0148 */
|
|
||||||
otg_fs_isr, /* Addr: 0x0000_014C */
|
|
||||||
};
|
|
||||||
|
|
||||||
void reset_handler(void)
|
|
||||||
{
|
|
||||||
volatile unsigned *src, *dest;
|
|
||||||
|
|
||||||
__asm__("MSR msp, %0" : : "r"(&_stack));
|
|
||||||
|
|
||||||
for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
|
|
||||||
*dest = *src;
|
|
||||||
|
|
||||||
while (dest < &_ebss)
|
|
||||||
*dest++ = 0;
|
|
||||||
|
|
||||||
/* Call the application's entry point. */
|
|
||||||
main();
|
|
||||||
}
|
|
||||||
|
|
||||||
void blocking_handler(void)
|
|
||||||
{
|
|
||||||
while (1) ;
|
|
||||||
}
|
|
||||||
|
|
||||||
void null_handler(void)
|
|
||||||
{
|
|
||||||
/* Do nothing. */
|
|
||||||
}
|
|
||||||
|
|
||||||
#pragma weak nmi_handler = null_handler
|
|
||||||
#pragma weak hard_fault_handler = blocking_handler
|
|
||||||
#pragma weak mem_manage_handler = blocking_handler
|
|
||||||
#pragma weak bus_fault_handler = blocking_handler
|
|
||||||
#pragma weak usage_fault_handler = blocking_handler
|
|
||||||
#pragma weak sv_call_handler = null_handler
|
|
||||||
#pragma weak debug_monitor_handler = null_handler
|
|
||||||
#pragma weak pend_sv_handler = null_handler
|
|
||||||
#pragma weak sys_tick_handler = null_handler
|
|
||||||
#pragma weak wwdg_isr = null_handler
|
|
||||||
#pragma weak pvd_isr = null_handler
|
|
||||||
#pragma weak tamper_isr = null_handler
|
|
||||||
#pragma weak rtc_isr = null_handler
|
|
||||||
#pragma weak flash_isr = null_handler
|
|
||||||
#pragma weak rcc_isr = null_handler
|
|
||||||
#pragma weak exti0_isr = null_handler
|
|
||||||
#pragma weak exti1_isr = null_handler
|
|
||||||
#pragma weak exti2_isr = null_handler
|
|
||||||
#pragma weak exti3_isr = null_handler
|
|
||||||
#pragma weak exti4_isr = null_handler
|
|
||||||
#pragma weak dma1_channel1_isr = null_handler
|
|
||||||
#pragma weak dma1_channel2_isr = null_handler
|
|
||||||
#pragma weak dma1_channel3_isr = null_handler
|
|
||||||
#pragma weak dma1_channel4_isr = null_handler
|
|
||||||
#pragma weak dma1_channel5_isr = null_handler
|
|
||||||
#pragma weak dma1_channel6_isr = null_handler
|
|
||||||
#pragma weak dma1_channel7_isr = null_handler
|
|
||||||
#pragma weak adc1_2_isr = null_handler
|
|
||||||
#pragma weak usb_hp_can_tx_isr = null_handler
|
|
||||||
#pragma weak usb_lp_can_rx0_isr = null_handler
|
|
||||||
#pragma weak can_rx1_isr = null_handler
|
|
||||||
#pragma weak can_sce_isr = null_handler
|
|
||||||
#pragma weak exti9_5_isr = null_handler
|
|
||||||
#pragma weak tim1_brk_isr = null_handler
|
|
||||||
#pragma weak tim1_up_isr = null_handler
|
|
||||||
#pragma weak tim1_trg_com_isr = null_handler
|
|
||||||
#pragma weak tim1_cc_isr = null_handler
|
|
||||||
#pragma weak tim2_isr = null_handler
|
|
||||||
#pragma weak tim3_isr = null_handler
|
|
||||||
#pragma weak tim4_isr = null_handler
|
|
||||||
#pragma weak i2c1_ev_isr = null_handler
|
|
||||||
#pragma weak i2c1_er_isr = null_handler
|
|
||||||
#pragma weak i2c2_ev_isr = null_handler
|
|
||||||
#pragma weak i2c2_er_isr = null_handler
|
|
||||||
#pragma weak spi1_isr = null_handler
|
|
||||||
#pragma weak spi2_isr = null_handler
|
|
||||||
#pragma weak usart1_isr = null_handler
|
|
||||||
#pragma weak usart2_isr = null_handler
|
|
||||||
#pragma weak usart3_isr = null_handler
|
|
||||||
#pragma weak exti15_10_isr = null_handler
|
|
||||||
#pragma weak rtc_alarm_isr = null_handler
|
|
||||||
#pragma weak usb_wakeup_isr = null_handler
|
|
||||||
#pragma weak tim8_brk_isr = null_handler
|
|
||||||
#pragma weak tim8_up_isr = null_handler
|
|
||||||
#pragma weak tim8_trg_com_isr = null_handler
|
|
||||||
#pragma weak tim8_cc_isr = null_handler
|
|
||||||
#pragma weak adc3_isr = null_handler
|
|
||||||
#pragma weak fsmc_isr = null_handler
|
|
||||||
#pragma weak sdio_isr = null_handler
|
|
||||||
#pragma weak tim5_isr = null_handler
|
|
||||||
#pragma weak spi3_isr = null_handler
|
|
||||||
#pragma weak uart4_isr = null_handler
|
|
||||||
#pragma weak uart5_isr = null_handler
|
|
||||||
#pragma weak tim6_isr = null_handler
|
|
||||||
#pragma weak tim7_isr = null_handler
|
|
||||||
#pragma weak dma2_channel1_isr = null_handler
|
|
||||||
#pragma weak dma2_channel2_isr = null_handler
|
|
||||||
#pragma weak dma2_channel3_isr = null_handler
|
|
||||||
#pragma weak dma2_channel4_5_isr = null_handler
|
|
||||||
#pragma weak dma2_channel5_isr
|
|
||||||
#pragma weak eth_isr = null_handler
|
|
||||||
#pragma weak eth_wkup_isr = null_handler
|
|
||||||
#pragma weak can2_tx_isr = null_handler
|
|
||||||
#pragma weak can2_rx0_isr = null_handler
|
|
||||||
#pragma weak can2_rx1_isr = null_handler
|
|
||||||
#pragma weak can2_sce_isr = null_handler
|
|
||||||
#pragma weak otg_fs_isr = null_handler
|
|
||||||
@ -28,8 +28,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
|
|||||||
-ffunction-sections -fdata-sections -MD -DSTM32F2
|
-ffunction-sections -fdata-sections -MD -DSTM32F2
|
||||||
# ARFLAGS = rcsv
|
# ARFLAGS = rcsv
|
||||||
ARFLAGS = rcs
|
ARFLAGS = rcs
|
||||||
OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \
|
OBJS = rcc.o gpio.o usart.o spi.o flash.o \
|
||||||
i2c.o systick.o exti.o scb.o timer.o assert.o
|
i2c.o exti.o timer.o
|
||||||
|
|
||||||
VPATH += ../../usb:../:../../cm3
|
VPATH += ../../usb:../:../../cm3
|
||||||
|
|
||||||
|
|||||||
@ -1,35 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <libopencm3/stm32/f2/scb.h>
|
|
||||||
|
|
||||||
void scb_reset_core(void)
|
|
||||||
{
|
|
||||||
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
|
|
||||||
}
|
|
||||||
|
|
||||||
void scb_reset_system(void)
|
|
||||||
{
|
|
||||||
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ;
|
|
||||||
}
|
|
||||||
|
|
||||||
void scb_set_priority_grouping(u32 prigroup)
|
|
||||||
{
|
|
||||||
SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
|
|
||||||
}
|
|
||||||
@ -1,336 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
|
||||||
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define WEAK __attribute__ ((weak))
|
|
||||||
|
|
||||||
/* Symbols exported by the linker script(s): */
|
|
||||||
extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
|
|
||||||
|
|
||||||
void main(void);
|
|
||||||
void reset_handler(void);
|
|
||||||
void blocking_handler(void);
|
|
||||||
void null_handler(void);
|
|
||||||
|
|
||||||
void WEAK reset_handler(void);
|
|
||||||
void WEAK nmi_handler(void);
|
|
||||||
void WEAK hard_fault_handler(void);
|
|
||||||
void WEAK mem_manage_handler(void);
|
|
||||||
void WEAK bus_fault_handler(void);
|
|
||||||
void WEAK usage_fault_handler(void);
|
|
||||||
void WEAK sv_call_handler(void);
|
|
||||||
void WEAK debug_monitor_handler(void);
|
|
||||||
void WEAK pend_sv_handler(void);
|
|
||||||
void WEAK sys_tick_handler(void);
|
|
||||||
void WEAK wwdg_isr(void);
|
|
||||||
void WEAK pvd_isr(void);
|
|
||||||
void WEAK tamp_stamp_isr(void);
|
|
||||||
void WEAK rtc_wkup_isr(void);
|
|
||||||
void WEAK flash_isr(void);
|
|
||||||
void WEAK rcc_isr(void);
|
|
||||||
void WEAK exti0_isr(void);
|
|
||||||
void WEAK exti1_isr(void);
|
|
||||||
void WEAK exti2_isr(void);
|
|
||||||
void WEAK exti3_isr(void);
|
|
||||||
void WEAK exti4_isr(void);
|
|
||||||
void WEAK dma1_stream0_isr(void);
|
|
||||||
void WEAK dma1_stream1_isr(void);
|
|
||||||
void WEAK dma1_stream2_isr(void);
|
|
||||||
void WEAK dma1_stream3_isr(void);
|
|
||||||
void WEAK dma1_stream4_isr(void);
|
|
||||||
void WEAK dma1_stream5_isr(void);
|
|
||||||
void WEAK dma1_stream6_isr(void);
|
|
||||||
void WEAK adc_isr(void);
|
|
||||||
void WEAK can1_tx_isr(void);
|
|
||||||
void WEAK can1_rx0_isr(void);
|
|
||||||
void WEAK can1_rx1_isr(void);
|
|
||||||
void WEAK can1_sce_isr(void);
|
|
||||||
void WEAK exti9_5_isr(void);
|
|
||||||
void WEAK tim1_brk_tim9_isr(void);
|
|
||||||
void WEAK tim1_up_tim10_isr(void);
|
|
||||||
void WEAK tim1_trg_com_tim11_isr(void);
|
|
||||||
void WEAK tim1_cc_isr(void);
|
|
||||||
void WEAK tim2_isr(void);
|
|
||||||
void WEAK tim3_isr(void);
|
|
||||||
void WEAK tim4_isr(void);
|
|
||||||
void WEAK i2c1_ev_isr(void);
|
|
||||||
void WEAK i2c1_er_isr(void);
|
|
||||||
void WEAK i2c2_ev_isr(void);
|
|
||||||
void WEAK i2c2_er_isr(void);
|
|
||||||
void WEAK spi1_isr(void);
|
|
||||||
void WEAK spi2_isr(void);
|
|
||||||
void WEAK usart1_isr(void);
|
|
||||||
void WEAK usart2_isr(void);
|
|
||||||
void WEAK usart3_isr(void);
|
|
||||||
void WEAK exti15_10_isr(void);
|
|
||||||
void WEAK rtc_alarm_isr(void);
|
|
||||||
void WEAK usb_fs_wkup_isr(void);
|
|
||||||
void WEAK tim8_brk_tim12_isr(void);
|
|
||||||
void WEAK tim8_up_tim13_isr(void);
|
|
||||||
void WEAK tim8_trg_com_tim14_isr(void);
|
|
||||||
void WEAK tim8_cc_isr(void);
|
|
||||||
void WEAK dma1_stream7_isr(void);
|
|
||||||
void WEAK fsmc_isr(void);
|
|
||||||
void WEAK sdio_isr(void);
|
|
||||||
void WEAK tim5_isr(void);
|
|
||||||
void WEAK spi3_isr(void);
|
|
||||||
void WEAK uart4_isr(void);
|
|
||||||
void WEAK uart5_isr(void);
|
|
||||||
void WEAK tim6_dac_isr(void);
|
|
||||||
void WEAK tim7_isr(void);
|
|
||||||
void WEAK dma2_stream0_isr(void);
|
|
||||||
void WEAK dma2_stream1_isr(void);
|
|
||||||
void WEAK dma2_stream2_isr(void);
|
|
||||||
void WEAK dma2_stream3_isr(void);
|
|
||||||
void WEAK dma2_stream4_isr(void);
|
|
||||||
void WEAK eth_isr(void);
|
|
||||||
void WEAK eth_wkup_isr(void);
|
|
||||||
void WEAK can2_tx_isr(void);
|
|
||||||
void WEAK can2_rx0_isr(void);
|
|
||||||
void WEAK can2_rx1_isr(void);
|
|
||||||
void WEAK can2_sce_isr(void);
|
|
||||||
void WEAK otg_fs_isr(void);
|
|
||||||
void WEAK dma2_stream5_isr(void);
|
|
||||||
void WEAK dma2_stream6_isr(void);
|
|
||||||
void WEAK dma2_stream7_isr(void);
|
|
||||||
void WEAK usart6_isr(void);
|
|
||||||
void WEAK i2c3_ev_isr(void);
|
|
||||||
void WEAK i2c3_er_isr(void);
|
|
||||||
void WEAK otg_hs_ep1_out_isr(void);
|
|
||||||
void WEAK otg_hs_ep1_in_isr(void);
|
|
||||||
void WEAK otg_hs_wkup_isr(void);
|
|
||||||
void WEAK otg_hs_isr(void);
|
|
||||||
void WEAK dcmi_isr(void);
|
|
||||||
void WEAK cryp_isr(void);
|
|
||||||
void WEAK hash_rng_isr(void);
|
|
||||||
|
|
||||||
__attribute__ ((section(".vectors")))
|
|
||||||
void (*const vector_table[]) (void) = {
|
|
||||||
(void *)&_stack,
|
|
||||||
reset_handler,
|
|
||||||
nmi_handler,
|
|
||||||
hard_fault_handler,
|
|
||||||
mem_manage_handler,
|
|
||||||
bus_fault_handler,
|
|
||||||
usage_fault_handler,
|
|
||||||
0, 0, 0, 0, /* Reserved */
|
|
||||||
sv_call_handler,
|
|
||||||
debug_monitor_handler,
|
|
||||||
0, /* Reserved */
|
|
||||||
pend_sv_handler,
|
|
||||||
sys_tick_handler,
|
|
||||||
wwdg_isr,
|
|
||||||
pvd_isr,
|
|
||||||
tamp_stamp_isr,
|
|
||||||
rtc_wkup_isr,
|
|
||||||
flash_isr,
|
|
||||||
rcc_isr,
|
|
||||||
exti0_isr,
|
|
||||||
exti1_isr,
|
|
||||||
exti2_isr,
|
|
||||||
exti3_isr,
|
|
||||||
exti4_isr,
|
|
||||||
dma1_stream0_isr,
|
|
||||||
dma1_stream1_isr,
|
|
||||||
dma1_stream2_isr,
|
|
||||||
dma1_stream3_isr,
|
|
||||||
dma1_stream4_isr,
|
|
||||||
dma1_stream5_isr,
|
|
||||||
dma1_stream6_isr,
|
|
||||||
adc_isr,
|
|
||||||
can1_tx_isr,
|
|
||||||
can1_rx0_isr,
|
|
||||||
can1_rx1_isr,
|
|
||||||
can1_sce_isr,
|
|
||||||
exti9_5_isr,
|
|
||||||
tim1_brk_tim9_isr,
|
|
||||||
tim1_up_tim10_isr,
|
|
||||||
tim1_trg_com_tim11_isr,
|
|
||||||
tim1_cc_isr,
|
|
||||||
tim2_isr,
|
|
||||||
tim3_isr,
|
|
||||||
tim4_isr,
|
|
||||||
i2c1_ev_isr,
|
|
||||||
i2c1_er_isr,
|
|
||||||
i2c2_ev_isr,
|
|
||||||
i2c2_er_isr,
|
|
||||||
spi1_isr,
|
|
||||||
spi2_isr,
|
|
||||||
usart1_isr,
|
|
||||||
usart2_isr,
|
|
||||||
usart3_isr,
|
|
||||||
exti15_10_isr,
|
|
||||||
rtc_alarm_isr,
|
|
||||||
usb_fs_wkup_isr,
|
|
||||||
tim8_brk_tim12_isr,
|
|
||||||
tim8_up_tim13_isr,
|
|
||||||
tim8_trg_com_tim14_isr,
|
|
||||||
tim8_cc_isr,
|
|
||||||
dma1_stream7_isr,
|
|
||||||
fsmc_isr,
|
|
||||||
sdio_isr,
|
|
||||||
tim5_isr,
|
|
||||||
spi3_isr,
|
|
||||||
uart4_isr,
|
|
||||||
uart5_isr,
|
|
||||||
tim6_dac_isr,
|
|
||||||
tim7_isr,
|
|
||||||
dma2_stream0_isr,
|
|
||||||
dma2_stream1_isr,
|
|
||||||
dma2_stream2_isr,
|
|
||||||
dma2_stream3_isr,
|
|
||||||
dma2_stream4_isr,
|
|
||||||
eth_isr,
|
|
||||||
eth_wkup_isr,
|
|
||||||
can2_tx_isr,
|
|
||||||
can2_rx0_isr,
|
|
||||||
can2_rx1_isr,
|
|
||||||
can2_sce_isr,
|
|
||||||
otg_fs_isr,
|
|
||||||
dma2_stream5_isr,
|
|
||||||
dma2_stream6_isr,
|
|
||||||
dma2_stream7_isr,
|
|
||||||
usart6_isr,
|
|
||||||
i2c3_ev_isr,
|
|
||||||
i2c3_er_isr,
|
|
||||||
otg_hs_ep1_out_isr,
|
|
||||||
otg_hs_ep1_in_isr,
|
|
||||||
otg_hs_wkup_isr,
|
|
||||||
otg_hs_isr,
|
|
||||||
dcmi_isr,
|
|
||||||
cryp_isr,
|
|
||||||
hash_rng_isr,
|
|
||||||
};
|
|
||||||
|
|
||||||
void reset_handler(void)
|
|
||||||
{
|
|
||||||
volatile unsigned *src, *dest;
|
|
||||||
|
|
||||||
__asm__("MSR msp, %0" : : "r"(&_stack));
|
|
||||||
|
|
||||||
for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
|
|
||||||
*dest = *src;
|
|
||||||
|
|
||||||
while (dest < &_ebss)
|
|
||||||
*dest++ = 0;
|
|
||||||
|
|
||||||
/* Call the application's entry point. */
|
|
||||||
main();
|
|
||||||
}
|
|
||||||
|
|
||||||
void blocking_handler(void)
|
|
||||||
{
|
|
||||||
while (1) ;
|
|
||||||
}
|
|
||||||
|
|
||||||
void null_handler(void)
|
|
||||||
{
|
|
||||||
/* Do nothing. */
|
|
||||||
}
|
|
||||||
|
|
||||||
#pragma weak nmi_handler = null_handler
|
|
||||||
#pragma weak hard_fault_handler = blocking_handler
|
|
||||||
#pragma weak mem_manage_handler = blocking_handler
|
|
||||||
#pragma weak bus_fault_handler = blocking_handler
|
|
||||||
#pragma weak usage_fault_handler = blocking_handler
|
|
||||||
#pragma weak sv_call_handler = null_handler
|
|
||||||
#pragma weak debug_monitor_handler = null_handler
|
|
||||||
#pragma weak pend_sv_handler = null_handler
|
|
||||||
#pragma weak sys_tick_handler = null_handler
|
|
||||||
#pragma weak wwdg_isr = null_handler
|
|
||||||
#pragma weak pvd_isr = null_handler
|
|
||||||
#pragma weak tamp_stamp_isr = null_handler
|
|
||||||
#pragma weak rtc_wkup_isr = null_handler
|
|
||||||
#pragma weak flash_isr = null_handler
|
|
||||||
#pragma weak rcc_isr = null_handler
|
|
||||||
#pragma weak exti0_isr = null_handler
|
|
||||||
#pragma weak exti1_isr = null_handler
|
|
||||||
#pragma weak exti2_isr = null_handler
|
|
||||||
#pragma weak exti3_isr = null_handler
|
|
||||||
#pragma weak exti4_isr = null_handler
|
|
||||||
#pragma weak dma1_stream0_isr = null_handler
|
|
||||||
#pragma weak dma1_stream1_isr = null_handler
|
|
||||||
#pragma weak dma1_stream2_isr = null_handler
|
|
||||||
#pragma weak dma1_stream3_isr = null_handler
|
|
||||||
#pragma weak dma1_stream4_isr = null_handler
|
|
||||||
#pragma weak dma1_stream5_isr = null_handler
|
|
||||||
#pragma weak dma1_stream6_isr = null_handler
|
|
||||||
#pragma weak adc_isr = null_handler
|
|
||||||
#pragma weak can1_tx_isr = null_handler
|
|
||||||
#pragma weak can1_rx0_isr = null_handler
|
|
||||||
#pragma weak can1_rx1_isr = null_handler
|
|
||||||
#pragma weak can1_sce_isr = null_handler
|
|
||||||
#pragma weak exti9_5_isr = null_handler
|
|
||||||
#pragma weak tim1_brk_tim9_isr = null_handler
|
|
||||||
#pragma weak tim1_up_tim10_isr = null_handler
|
|
||||||
#pragma weak tim1_trg_com_tim11_isr = null_handler
|
|
||||||
#pragma weak tim1_cc_isr = null_handler
|
|
||||||
#pragma weak tim2_isr = null_handler
|
|
||||||
#pragma weak tim3_isr = null_handler
|
|
||||||
#pragma weak tim4_isr = null_handler
|
|
||||||
#pragma weak i2c1_ev_isr = null_handler
|
|
||||||
#pragma weak i2c1_er_isr = null_handler
|
|
||||||
#pragma weak i2c2_ev_isr = null_handler
|
|
||||||
#pragma weak i2c2_er_isr = null_handler
|
|
||||||
#pragma weak spi1_isr = null_handler
|
|
||||||
#pragma weak spi2_isr = null_handler
|
|
||||||
#pragma weak usart1_isr = null_handler
|
|
||||||
#pragma weak usart2_isr = null_handler
|
|
||||||
#pragma weak usart3_isr = null_handler
|
|
||||||
#pragma weak exti15_10_isr = null_handler
|
|
||||||
#pragma weak rtc_alarm_isr = null_handler
|
|
||||||
#pragma weak usb_fs_wkup_isr = null_handler
|
|
||||||
#pragma weak tim8_brk_tim12_isr = null_handler
|
|
||||||
#pragma weak tim8_up_tim13_isr = null_handler
|
|
||||||
#pragma weak tim8_trg_com_tim14_isr = null_handler
|
|
||||||
#pragma weak tim8_cc_isr = null_handler
|
|
||||||
#pragma weak dma1_stream7_isr = null_handler
|
|
||||||
#pragma weak fsmc_isr = null_handler
|
|
||||||
#pragma weak sdio_isr = null_handler
|
|
||||||
#pragma weak tim5_isr = null_handler
|
|
||||||
#pragma weak spi3_isr = null_handler
|
|
||||||
#pragma weak uart4_isr = null_handler
|
|
||||||
#pragma weak uart5_isr = null_handler
|
|
||||||
#pragma weak tim6_dac_isr = null_handler
|
|
||||||
#pragma weak tim7_isr = null_handler
|
|
||||||
#pragma weak dma2_stream0_isr = null_handler
|
|
||||||
#pragma weak dma2_stream1_isr = null_handler
|
|
||||||
#pragma weak dma2_stream2_isr = null_handler
|
|
||||||
#pragma weak dma2_stream3_isr = null_handler
|
|
||||||
#pragma weak dma2_stream4_isr = null_handler
|
|
||||||
#pragma weak eth_isr = null_handler
|
|
||||||
#pragma weak eth_wkup_isr = null_handler
|
|
||||||
#pragma weak can2_tx_isr = null_handler
|
|
||||||
#pragma weak can2_rx0_isr = null_handler
|
|
||||||
#pragma weak can2_rx1_isr = null_handler
|
|
||||||
#pragma weak can2_sce_isr = null_handler
|
|
||||||
#pragma weak otg_fs_isr = null_handler
|
|
||||||
#pragma weak dma2_stream5_isr = null_handler
|
|
||||||
#pragma weak dma2_stream6_isr = null_handler
|
|
||||||
#pragma weak dma2_stream7_isr = null_handler
|
|
||||||
#pragma weak usart6_isr = null_handler
|
|
||||||
#pragma weak i2c3_ev_isr = null_handler
|
|
||||||
#pragma weak i2c3_er_isr = null_handler
|
|
||||||
#pragma weak otg_hs_ep1_out_isr = null_handler
|
|
||||||
#pragma weak otg_hs_ep1_in_isr = null_handler
|
|
||||||
#pragma weak otg_hs_wkup_isr = null_handler
|
|
||||||
#pragma weak otg_hs_isr = null_handler
|
|
||||||
#pragma weak dcmi_isr = null_handler
|
|
||||||
#pragma weak cryp_isr = null_handler
|
|
||||||
#pragma weak hash_rng_isr = null_handler
|
|
||||||
@ -29,10 +29,9 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
|
|||||||
-ffunction-sections -fdata-sections -MD -DSTM32F4
|
-ffunction-sections -fdata-sections -MD -DSTM32F4
|
||||||
# ARFLAGS = rcsv
|
# ARFLAGS = rcsv
|
||||||
ARFLAGS = rcs
|
ARFLAGS = rcs
|
||||||
OBJS = vector.o rcc.o gpio.o usart.o spi.o flash.o nvic.o \
|
OBJS = rcc.o gpio.o usart.o spi.o flash.o \
|
||||||
i2c.o systick.o exti.o scb.o pwr.o timer.o \
|
i2c.o exti.o pwr.o timer.o \
|
||||||
usb.o usb_standard.o usb_control.o usb_f107.o \
|
usb.o usb_standard.o usb_control.o usb_f107.o
|
||||||
assert.o
|
|
||||||
|
|
||||||
VPATH += ../../usb:../:../../cm3
|
VPATH += ../../usb:../:../../cm3
|
||||||
|
|
||||||
|
|||||||
@ -1,341 +0,0 @@
|
|||||||
/*
|
|
||||||
* This file is part of the libopencm3 project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
|
||||||
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
|
|
||||||
*
|
|
||||||
* This library is free software: you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
|
||||||
* the Free Software Foundation, either version 3 of the License, or
|
|
||||||
* (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This library is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU Lesser General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU Lesser General Public License
|
|
||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <libopencm3/stm32/f4/scb.h>
|
|
||||||
|
|
||||||
#define WEAK __attribute__ ((weak))
|
|
||||||
|
|
||||||
/* Symbols exported by the linker script(s): */
|
|
||||||
extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
|
|
||||||
|
|
||||||
void main(void);
|
|
||||||
void reset_handler(void);
|
|
||||||
void blocking_handler(void);
|
|
||||||
void null_handler(void);
|
|
||||||
|
|
||||||
void WEAK reset_handler(void);
|
|
||||||
void WEAK nmi_handler(void);
|
|
||||||
void WEAK hard_fault_handler(void);
|
|
||||||
void WEAK mem_manage_handler(void);
|
|
||||||
void WEAK bus_fault_handler(void);
|
|
||||||
void WEAK usage_fault_handler(void);
|
|
||||||
void WEAK sv_call_handler(void);
|
|
||||||
void WEAK debug_monitor_handler(void);
|
|
||||||
void WEAK pend_sv_handler(void);
|
|
||||||
void WEAK sys_tick_handler(void);
|
|
||||||
void WEAK wwdg_isr(void);
|
|
||||||
void WEAK pvd_isr(void);
|
|
||||||
void WEAK tamp_stamp_isr(void);
|
|
||||||
void WEAK rtc_wkup_isr(void);
|
|
||||||
void WEAK flash_isr(void);
|
|
||||||
void WEAK rcc_isr(void);
|
|
||||||
void WEAK exti0_isr(void);
|
|
||||||
void WEAK exti1_isr(void);
|
|
||||||
void WEAK exti2_isr(void);
|
|
||||||
void WEAK exti3_isr(void);
|
|
||||||
void WEAK exti4_isr(void);
|
|
||||||
void WEAK dma1_stream0_isr(void);
|
|
||||||
void WEAK dma1_stream1_isr(void);
|
|
||||||
void WEAK dma1_stream2_isr(void);
|
|
||||||
void WEAK dma1_stream3_isr(void);
|
|
||||||
void WEAK dma1_stream4_isr(void);
|
|
||||||
void WEAK dma1_stream5_isr(void);
|
|
||||||
void WEAK dma1_stream6_isr(void);
|
|
||||||
void WEAK adc_isr(void);
|
|
||||||
void WEAK can1_tx_isr(void);
|
|
||||||
void WEAK can1_rx0_isr(void);
|
|
||||||
void WEAK can1_rx1_isr(void);
|
|
||||||
void WEAK can1_sce_isr(void);
|
|
||||||
void WEAK exti9_5_isr(void);
|
|
||||||
void WEAK tim1_brk_tim9_isr(void);
|
|
||||||
void WEAK tim1_up_tim10_isr(void);
|
|
||||||
void WEAK tim1_trg_com_tim11_isr(void);
|
|
||||||
void WEAK tim1_cc_isr(void);
|
|
||||||
void WEAK tim2_isr(void);
|
|
||||||
void WEAK tim3_isr(void);
|
|
||||||
void WEAK tim4_isr(void);
|
|
||||||
void WEAK i2c1_ev_isr(void);
|
|
||||||
void WEAK i2c1_er_isr(void);
|
|
||||||
void WEAK i2c2_ev_isr(void);
|
|
||||||
void WEAK i2c2_er_isr(void);
|
|
||||||
void WEAK spi1_isr(void);
|
|
||||||
void WEAK spi2_isr(void);
|
|
||||||
void WEAK usart1_isr(void);
|
|
||||||
void WEAK usart2_isr(void);
|
|
||||||
void WEAK usart3_isr(void);
|
|
||||||
void WEAK exti15_10_isr(void);
|
|
||||||
void WEAK rtc_alarm_isr(void);
|
|
||||||
void WEAK usb_fs_wkup_isr(void);
|
|
||||||
void WEAK tim8_brk_tim12_isr(void);
|
|
||||||
void WEAK tim8_up_tim13_isr(void);
|
|
||||||
void WEAK tim8_trg_com_tim14_isr(void);
|
|
||||||
void WEAK tim8_cc_isr(void);
|
|
||||||
void WEAK dma1_stream7_isr(void);
|
|
||||||
void WEAK fsmc_isr(void);
|
|
||||||
void WEAK sdio_isr(void);
|
|
||||||
void WEAK tim5_isr(void);
|
|
||||||
void WEAK spi3_isr(void);
|
|
||||||
void WEAK uart4_isr(void);
|
|
||||||
void WEAK uart5_isr(void);
|
|
||||||
void WEAK tim6_dac_isr(void);
|
|
||||||
void WEAK tim7_isr(void);
|
|
||||||
void WEAK dma2_stream0_isr(void);
|
|
||||||
void WEAK dma2_stream1_isr(void);
|
|
||||||
void WEAK dma2_stream2_isr(void);
|
|
||||||
void WEAK dma2_stream3_isr(void);
|
|
||||||
void WEAK dma2_stream4_isr(void);
|
|
||||||
void WEAK eth_isr(void);
|
|
||||||
void WEAK eth_wkup_isr(void);
|
|
||||||
void WEAK can2_tx_isr(void);
|
|
||||||
void WEAK can2_rx0_isr(void);
|
|
||||||
void WEAK can2_rx1_isr(void);
|
|
||||||
void WEAK can2_sce_isr(void);
|
|
||||||
void WEAK otg_fs_isr(void);
|
|
||||||
void WEAK dma2_stream5_isr(void);
|
|
||||||
void WEAK dma2_stream6_isr(void);
|
|
||||||
void WEAK dma2_stream7_isr(void);
|
|
||||||
void WEAK usart6_isr(void);
|
|
||||||
void WEAK i2c3_ev_isr(void);
|
|
||||||
void WEAK i2c3_er_isr(void);
|
|
||||||
void WEAK otg_hs_ep1_out_isr(void);
|
|
||||||
void WEAK otg_hs_ep1_in_isr(void);
|
|
||||||
void WEAK otg_hs_wkup_isr(void);
|
|
||||||
void WEAK otg_hs_isr(void);
|
|
||||||
void WEAK dcmi_isr(void);
|
|
||||||
void WEAK cryp_isr(void);
|
|
||||||
void WEAK hash_rng_isr(void);
|
|
||||||
|
|
||||||
__attribute__ ((section(".vectors")))
|
|
||||||
void (*const vector_table[]) (void) = {
|
|
||||||
(void *)&_stack,
|
|
||||||
reset_handler,
|
|
||||||
nmi_handler,
|
|
||||||
hard_fault_handler,
|
|
||||||
mem_manage_handler,
|
|
||||||
bus_fault_handler,
|
|
||||||
usage_fault_handler,
|
|
||||||
0, 0, 0, 0, /* Reserved */
|
|
||||||
sv_call_handler,
|
|
||||||
debug_monitor_handler,
|
|
||||||
0, /* Reserved */
|
|
||||||
pend_sv_handler,
|
|
||||||
sys_tick_handler,
|
|
||||||
wwdg_isr,
|
|
||||||
pvd_isr,
|
|
||||||
tamp_stamp_isr,
|
|
||||||
rtc_wkup_isr,
|
|
||||||
flash_isr,
|
|
||||||
rcc_isr,
|
|
||||||
exti0_isr,
|
|
||||||
exti1_isr,
|
|
||||||
exti2_isr,
|
|
||||||
exti3_isr,
|
|
||||||
exti4_isr,
|
|
||||||
dma1_stream0_isr,
|
|
||||||
dma1_stream1_isr,
|
|
||||||
dma1_stream2_isr,
|
|
||||||
dma1_stream3_isr,
|
|
||||||
dma1_stream4_isr,
|
|
||||||
dma1_stream5_isr,
|
|
||||||
dma1_stream6_isr,
|
|
||||||
adc_isr,
|
|
||||||
can1_tx_isr,
|
|
||||||
can1_rx0_isr,
|
|
||||||
can1_rx1_isr,
|
|
||||||
can1_sce_isr,
|
|
||||||
exti9_5_isr,
|
|
||||||
tim1_brk_tim9_isr,
|
|
||||||
tim1_up_tim10_isr,
|
|
||||||
tim1_trg_com_tim11_isr,
|
|
||||||
tim1_cc_isr,
|
|
||||||
tim2_isr,
|
|
||||||
tim3_isr,
|
|
||||||
tim4_isr,
|
|
||||||
i2c1_ev_isr,
|
|
||||||
i2c1_er_isr,
|
|
||||||
i2c2_ev_isr,
|
|
||||||
i2c2_er_isr,
|
|
||||||
spi1_isr,
|
|
||||||
spi2_isr,
|
|
||||||
usart1_isr,
|
|
||||||
usart2_isr,
|
|
||||||
usart3_isr,
|
|
||||||
exti15_10_isr,
|
|
||||||
rtc_alarm_isr,
|
|
||||||
usb_fs_wkup_isr,
|
|
||||||
tim8_brk_tim12_isr,
|
|
||||||
tim8_up_tim13_isr,
|
|
||||||
tim8_trg_com_tim14_isr,
|
|
||||||
tim8_cc_isr,
|
|
||||||
dma1_stream7_isr,
|
|
||||||
fsmc_isr,
|
|
||||||
sdio_isr,
|
|
||||||
tim5_isr,
|
|
||||||
spi3_isr,
|
|
||||||
uart4_isr,
|
|
||||||
uart5_isr,
|
|
||||||
tim6_dac_isr,
|
|
||||||
tim7_isr,
|
|
||||||
dma2_stream0_isr,
|
|
||||||
dma2_stream1_isr,
|
|
||||||
dma2_stream2_isr,
|
|
||||||
dma2_stream3_isr,
|
|
||||||
dma2_stream4_isr,
|
|
||||||
eth_isr,
|
|
||||||
eth_wkup_isr,
|
|
||||||
can2_tx_isr,
|
|
||||||
can2_rx0_isr,
|
|
||||||
can2_rx1_isr,
|
|
||||||
can2_sce_isr,
|
|
||||||
otg_fs_isr,
|
|
||||||
dma2_stream5_isr,
|
|
||||||
dma2_stream6_isr,
|
|
||||||
dma2_stream7_isr,
|
|
||||||
usart6_isr,
|
|
||||||
i2c3_ev_isr,
|
|
||||||
i2c3_er_isr,
|
|
||||||
otg_hs_ep1_out_isr,
|
|
||||||
otg_hs_ep1_in_isr,
|
|
||||||
otg_hs_wkup_isr,
|
|
||||||
otg_hs_isr,
|
|
||||||
dcmi_isr,
|
|
||||||
cryp_isr,
|
|
||||||
hash_rng_isr,
|
|
||||||
};
|
|
||||||
|
|
||||||
void reset_handler(void)
|
|
||||||
{
|
|
||||||
volatile unsigned *src, *dest;
|
|
||||||
|
|
||||||
__asm__("MSR msp, %0" : : "r"(&_stack));
|
|
||||||
|
|
||||||
/* Enable access to Floating-Point coprocessor. */
|
|
||||||
SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11);
|
|
||||||
|
|
||||||
for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
|
|
||||||
*dest = *src;
|
|
||||||
|
|
||||||
while (dest < &_ebss)
|
|
||||||
*dest++ = 0;
|
|
||||||
|
|
||||||
/* Call the application's entry point. */
|
|
||||||
main();
|
|
||||||
}
|
|
||||||
|
|
||||||
void blocking_handler(void)
|
|
||||||
{
|
|
||||||
while (1) ;
|
|
||||||
}
|
|
||||||
|
|
||||||
void null_handler(void)
|
|
||||||
{
|
|
||||||
/* Do nothing. */
|
|
||||||
}
|
|
||||||
|
|
||||||
#pragma weak nmi_handler = null_handler
|
|
||||||
#pragma weak hard_fault_handler = blocking_handler
|
|
||||||
#pragma weak mem_manage_handler = blocking_handler
|
|
||||||
#pragma weak bus_fault_handler = blocking_handler
|
|
||||||
#pragma weak usage_fault_handler = blocking_handler
|
|
||||||
#pragma weak sv_call_handler = null_handler
|
|
||||||
#pragma weak debug_monitor_handler = null_handler
|
|
||||||
#pragma weak pend_sv_handler = null_handler
|
|
||||||
#pragma weak sys_tick_handler = null_handler
|
|
||||||
#pragma weak wwdg_isr = null_handler
|
|
||||||
#pragma weak pvd_isr = null_handler
|
|
||||||
#pragma weak tamp_stamp_isr = null_handler
|
|
||||||
#pragma weak rtc_wkup_isr = null_handler
|
|
||||||
#pragma weak flash_isr = null_handler
|
|
||||||
#pragma weak rcc_isr = null_handler
|
|
||||||
#pragma weak exti0_isr = null_handler
|
|
||||||
#pragma weak exti1_isr = null_handler
|
|
||||||
#pragma weak exti2_isr = null_handler
|
|
||||||
#pragma weak exti3_isr = null_handler
|
|
||||||
#pragma weak exti4_isr = null_handler
|
|
||||||
#pragma weak dma1_stream0_isr = null_handler
|
|
||||||
#pragma weak dma1_stream1_isr = null_handler
|
|
||||||
#pragma weak dma1_stream2_isr = null_handler
|
|
||||||
#pragma weak dma1_stream3_isr = null_handler
|
|
||||||
#pragma weak dma1_stream4_isr = null_handler
|
|
||||||
#pragma weak dma1_stream5_isr = null_handler
|
|
||||||
#pragma weak dma1_stream6_isr = null_handler
|
|
||||||
#pragma weak adc_isr = null_handler
|
|
||||||
#pragma weak can1_tx_isr = null_handler
|
|
||||||
#pragma weak can1_rx0_isr = null_handler
|
|
||||||
#pragma weak can1_rx1_isr = null_handler
|
|
||||||
#pragma weak can1_sce_isr = null_handler
|
|
||||||
#pragma weak exti9_5_isr = null_handler
|
|
||||||
#pragma weak tim1_brk_tim9_isr = null_handler
|
|
||||||
#pragma weak tim1_up_tim10_isr = null_handler
|
|
||||||
#pragma weak tim1_trg_com_tim11_isr = null_handler
|
|
||||||
#pragma weak tim1_cc_isr = null_handler
|
|
||||||
#pragma weak tim2_isr = null_handler
|
|
||||||
#pragma weak tim3_isr = null_handler
|
|
||||||
#pragma weak tim4_isr = null_handler
|
|
||||||
#pragma weak i2c1_ev_isr = null_handler
|
|
||||||
#pragma weak i2c1_er_isr = null_handler
|
|
||||||
#pragma weak i2c2_ev_isr = null_handler
|
|
||||||
#pragma weak i2c2_er_isr = null_handler
|
|
||||||
#pragma weak spi1_isr = null_handler
|
|
||||||
#pragma weak spi2_isr = null_handler
|
|
||||||
#pragma weak usart1_isr = null_handler
|
|
||||||
#pragma weak usart2_isr = null_handler
|
|
||||||
#pragma weak usart3_isr = null_handler
|
|
||||||
#pragma weak exti15_10_isr = null_handler
|
|
||||||
#pragma weak rtc_alarm_isr = null_handler
|
|
||||||
#pragma weak usb_fs_wkup_isr = null_handler
|
|
||||||
#pragma weak tim8_brk_tim12_isr = null_handler
|
|
||||||
#pragma weak tim8_up_tim13_isr = null_handler
|
|
||||||
#pragma weak tim8_trg_com_tim14_isr = null_handler
|
|
||||||
#pragma weak tim8_cc_isr = null_handler
|
|
||||||
#pragma weak dma1_stream7_isr = null_handler
|
|
||||||
#pragma weak fsmc_isr = null_handler
|
|
||||||
#pragma weak sdio_isr = null_handler
|
|
||||||
#pragma weak tim5_isr = null_handler
|
|
||||||
#pragma weak spi3_isr = null_handler
|
|
||||||
#pragma weak uart4_isr = null_handler
|
|
||||||
#pragma weak uart5_isr = null_handler
|
|
||||||
#pragma weak tim6_dac_isr = null_handler
|
|
||||||
#pragma weak tim7_isr = null_handler
|
|
||||||
#pragma weak dma2_stream0_isr = null_handler
|
|
||||||
#pragma weak dma2_stream1_isr = null_handler
|
|
||||||
#pragma weak dma2_stream2_isr = null_handler
|
|
||||||
#pragma weak dma2_stream3_isr = null_handler
|
|
||||||
#pragma weak dma2_stream4_isr = null_handler
|
|
||||||
#pragma weak eth_isr = null_handler
|
|
||||||
#pragma weak eth_wkup_isr = null_handler
|
|
||||||
#pragma weak can2_tx_isr = null_handler
|
|
||||||
#pragma weak can2_rx0_isr = null_handler
|
|
||||||
#pragma weak can2_rx1_isr = null_handler
|
|
||||||
#pragma weak can2_sce_isr = null_handler
|
|
||||||
#pragma weak otg_fs_isr = null_handler
|
|
||||||
#pragma weak dma2_stream5_isr = null_handler
|
|
||||||
#pragma weak dma2_stream6_isr = null_handler
|
|
||||||
#pragma weak dma2_stream7_isr = null_handler
|
|
||||||
#pragma weak usart6_isr = null_handler
|
|
||||||
#pragma weak i2c3_ev_isr = null_handler
|
|
||||||
#pragma weak i2c3_er_isr = null_handler
|
|
||||||
#pragma weak otg_hs_ep1_out_isr = null_handler
|
|
||||||
#pragma weak otg_hs_ep1_in_isr = null_handler
|
|
||||||
#pragma weak otg_hs_wkup_isr = null_handler
|
|
||||||
#pragma weak otg_hs_isr = null_handler
|
|
||||||
#pragma weak dcmi_isr = null_handler
|
|
||||||
#pragma weak cryp_isr = null_handler
|
|
||||||
#pragma weak hash_rng_isr = null_handler
|
|
||||||
@ -1,7 +1,8 @@
|
|||||||
/*
|
/*
|
||||||
* This file is part of the libopencm3 project.
|
* This file is part of the libopencm3 project.
|
||||||
*
|
*
|
||||||
* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
|
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||||
|
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
|
||||||
*
|
*
|
||||||
* This library is free software: you can redistribute it and/or modify
|
* This library is free software: you can redistribute it and/or modify
|
||||||
* it under the terms of the GNU Lesser General Public License as published by
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
@ -17,19 +18,10 @@
|
|||||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <libopencm3/stm32/f1/scb.h>
|
#include <libopencm3/cm3/scb.h>
|
||||||
|
|
||||||
void scb_reset_core(void)
|
static void pre_main(void)
|
||||||
{
|
{
|
||||||
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
|
/* Enable access to Floating-Point coprocessor. */
|
||||||
}
|
SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11);
|
||||||
|
|
||||||
void scb_reset_system(void)
|
|
||||||
{
|
|
||||||
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ;
|
|
||||||
}
|
|
||||||
|
|
||||||
void scb_set_priority_grouping(u32 prigroup)
|
|
||||||
{
|
|
||||||
SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
|
|
||||||
}
|
}
|
||||||
160
scripts/irq2nvic_h
Executable file
160
scripts/irq2nvic_h
Executable file
@ -0,0 +1,160 @@
|
|||||||
|
#!/usr/bin/env python
|
||||||
|
|
||||||
|
# This file is part of the libopencm3 project.
|
||||||
|
#
|
||||||
|
# Copyright (C) 2012 chrysn <chrysn@fsfe.org>
|
||||||
|
#
|
||||||
|
# This library is free software: you can redistribute it and/or modify
|
||||||
|
# it under the terms of the GNU Lesser General Public License as published by
|
||||||
|
# the Free Software Foundation, either version 3 of the License, or
|
||||||
|
# (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This library is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU Lesser General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU Lesser General Public License
|
||||||
|
# along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
|
||||||
|
"""Generate an nvic.h header from a small YAML file describing the interrupt
|
||||||
|
numbers.
|
||||||
|
|
||||||
|
Code generation is chosen here because the resulting C code needs to be very
|
||||||
|
repetetive (definition of the IRQ numbers, function prototypes, weak fallback
|
||||||
|
definition and vector table definition), all being very repetitive. No portable
|
||||||
|
method to achive the same thing with C preprocessor is known to the author.
|
||||||
|
(Neither is any non-portable method, for that matter.)"""
|
||||||
|
|
||||||
|
import sys
|
||||||
|
import os
|
||||||
|
import os.path
|
||||||
|
import yaml
|
||||||
|
|
||||||
|
template_nvic_h = '''\
|
||||||
|
/* This file is part of the libopencm3 project.
|
||||||
|
*
|
||||||
|
* It was generated by the irq2nvic_h script.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef {includeguard}
|
||||||
|
#define {includeguard}
|
||||||
|
|
||||||
|
#include <libopencm3/cm3/nvic.h>
|
||||||
|
|
||||||
|
/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable}
|
||||||
|
@ingroup CM3_nvic_defines
|
||||||
|
|
||||||
|
@{{*/
|
||||||
|
|
||||||
|
{irqdefinitions}
|
||||||
|
|
||||||
|
#define NVIC_IRQ_COUNT {irqcount}
|
||||||
|
|
||||||
|
/**@}}*/
|
||||||
|
|
||||||
|
#define WEAK __attribute__ ((weak))
|
||||||
|
|
||||||
|
/** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable}
|
||||||
|
@ingroup CM3_nvic_isrprototypes
|
||||||
|
|
||||||
|
@{{*/
|
||||||
|
|
||||||
|
BEGIN_DECLS
|
||||||
|
|
||||||
|
{isrprototypes}
|
||||||
|
|
||||||
|
END_DECLS
|
||||||
|
|
||||||
|
/**@}}*/
|
||||||
|
|
||||||
|
#endif /* {includeguard} */
|
||||||
|
'''
|
||||||
|
|
||||||
|
template_vector_nvic_c = '''\
|
||||||
|
/* This file is part of the libopencm3 project.
|
||||||
|
*
|
||||||
|
* It was generated by the irq2nvic_h script.
|
||||||
|
*
|
||||||
|
* This part needs to get included in the compilation unit where
|
||||||
|
* blocking_handler gets defined due to the way #pragma works.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @defgroup CM3_nvic_isrpragmas_{partname_doxygen} User interrupt service routines (ISR) defaults for {partname_humanreadable}
|
||||||
|
@ingroup CM3_nvic_isrpragmas
|
||||||
|
|
||||||
|
@{{*/
|
||||||
|
|
||||||
|
{isrpragmas}
|
||||||
|
|
||||||
|
/**@}}*/
|
||||||
|
|
||||||
|
/* Initialization template for the interrupt vector table. This definition is
|
||||||
|
* used by the startup code generator (vector.c) to set the initial values for
|
||||||
|
* the interrupt handling routines to the chip family specific _isr weak
|
||||||
|
* symbols. */
|
||||||
|
|
||||||
|
#define IRQ_HANDLERS \\
|
||||||
|
{vectortableinitialization}
|
||||||
|
'''
|
||||||
|
|
||||||
|
def convert(infile, outfile_nvic, outfile_vectornvic):
|
||||||
|
data = yaml.load(infile)
|
||||||
|
|
||||||
|
irq2name = list(enumerate(data['irqs']) if isinstance(data['irqs'], list) else data['irqs'].items())
|
||||||
|
irqnames = [v for (k,v) in irq2name]
|
||||||
|
|
||||||
|
if isinstance(data['irqs'], list):
|
||||||
|
data['irqcount'] = len(irq2name)
|
||||||
|
else:
|
||||||
|
data['irqcount'] = max(data['irqs'].keys()) + 1
|
||||||
|
|
||||||
|
data['irqdefinitions'] = "\n".join('#define NVIC_%s_IRQ %d'%(v.upper(),k) for (k,v) in irq2name)
|
||||||
|
data['isrprototypes'] = "\n".join('void WEAK %s_isr(void);'%name.lower() for name in irqnames)
|
||||||
|
data['isrpragmas'] = "\n".join('#pragma weak %s_isr = blocking_handler'%name.lower() for name in irqnames)
|
||||||
|
data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames)
|
||||||
|
|
||||||
|
outfile_nvic.write(template_nvic_h.format(**data))
|
||||||
|
outfile_vectornvic.write(template_vector_nvic_c.format(**data))
|
||||||
|
|
||||||
|
def makeparentdir(filename):
|
||||||
|
try:
|
||||||
|
os.makedirs(os.path.dirname(filename))
|
||||||
|
except OSError:
|
||||||
|
# where is my 'mkdir -p'?
|
||||||
|
pass
|
||||||
|
|
||||||
|
def needs_update(infiles, outfiles):
|
||||||
|
timestamp = lambda filename: os.stat(filename).st_mtime
|
||||||
|
return any(not os.path.exists(o) for o in outfiles) or max(map(timestamp, infiles)) > min(map(timestamp, outfiles))
|
||||||
|
|
||||||
|
def main():
|
||||||
|
if sys.argv[1] == '--remove':
|
||||||
|
remove = True
|
||||||
|
del sys.argv[1]
|
||||||
|
else:
|
||||||
|
remove = False
|
||||||
|
infile = sys.argv[1]
|
||||||
|
if not infile.startswith('./include/libopencm3/') or not infile.endswith('/irq.yaml'):
|
||||||
|
raise ValueError("Arguent must match ./include/libopencm3/**/irq.yaml")
|
||||||
|
nvic_h = infile.replace('irq.yaml', 'nvic.h')
|
||||||
|
vector_nvic_c = infile.replace('./include/libopencm3/', './lib/').replace('irq.yaml', 'vector_nvic.c')
|
||||||
|
|
||||||
|
if remove:
|
||||||
|
if os.path.exists(nvic_h):
|
||||||
|
os.unlink(nvic_h)
|
||||||
|
if os.path.exists(vector_nvic_c):
|
||||||
|
os.unlink(vector_nvic_c)
|
||||||
|
sys.exit(0)
|
||||||
|
|
||||||
|
if not needs_update([__file__, infile], [nvic_h, vector_nvic_c]):
|
||||||
|
sys.exit(0)
|
||||||
|
|
||||||
|
makeparentdir(nvic_h)
|
||||||
|
makeparentdir(vector_nvic_c)
|
||||||
|
|
||||||
|
convert(open(infile), open(nvic_h, 'w'), open(vector_nvic_c, 'w'))
|
||||||
|
|
||||||
|
if __name__ == "__main__":
|
||||||
|
main()
|
||||||
Loading…
x
Reference in New Issue
Block a user