diff --git a/src/target/adiv5.c b/src/target/adiv5.c
index a0e5ff39..38f38e4e 100644
--- a/src/target/adiv5.c
+++ b/src/target/adiv5.c
@@ -216,7 +216,7 @@ static const struct {
 
 extern bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base);
 
-void adiv5_dp_ref(ADIv5_DP_t *dp)
+static void adiv5_dp_ref(ADIv5_DP_t *dp)
 {
 	dp->refcnt++;
 }
@@ -226,7 +226,7 @@ void adiv5_ap_ref(ADIv5_AP_t *ap)
 	ap->refcnt++;
 }
 
-void adiv5_dp_unref(ADIv5_DP_t *dp)
+static void adiv5_dp_unref(ADIv5_DP_t *dp)
 {
 	if (--(dp->refcnt) == 0)
 		free(dp);
diff --git a/src/target/adiv5.h b/src/target/adiv5.h
index d05f6144..65f47197 100644
--- a/src/target/adiv5.h
+++ b/src/target/adiv5.h
@@ -186,9 +186,7 @@ void adiv5_dp_init(ADIv5_DP_t *dp);
 void adiv5_dp_write(ADIv5_DP_t *dp, uint16_t addr, uint32_t value);
 
 ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel);
-void adiv5_dp_ref(ADIv5_DP_t *dp);
 void adiv5_ap_ref(ADIv5_AP_t *ap);
-void adiv5_dp_unref(ADIv5_DP_t *dp);
 void adiv5_ap_unref(ADIv5_AP_t *ap);
 
 void adiv5_ap_write(ADIv5_AP_t *ap, uint16_t addr, uint32_t value);
diff --git a/src/target/cortexm.c b/src/target/cortexm.c
index 1b7ae7f1..b81b4d1d 100644
--- a/src/target/cortexm.c
+++ b/src/target/cortexm.c
@@ -53,11 +53,12 @@ const struct command_s cortexm_cmd_list[] = {
 static void cortexm_regs_read(target *t, void *data);
 static void cortexm_regs_write(target *t, const void *data);
 static uint32_t cortexm_pc_read(target *t);
-ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max);
-ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max);
+static ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max);
+static ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max);
 
 static void cortexm_reset(target *t);
 static enum target_halt_reason cortexm_halt_poll(target *t, target_addr *watch);
+static void cortexm_halt_resume(target *t, bool step);
 static void cortexm_halt_request(target *t);
 static int cortexm_fault_unwind(target *t);
 
@@ -549,7 +550,7 @@ int cortexm_mem_write_sized(
 	return target_check_error(t);
 }
 
-int dcrsr_regnum(target *t, unsigned reg)
+static int dcrsr_regnum(target *t, unsigned reg)
 {
 	if (reg < sizeof(regnum_cortex_m) / 4) {
 		return regnum_cortex_m[reg];
@@ -561,7 +562,7 @@ int dcrsr_regnum(target *t, unsigned reg)
 		return -1;
 	}
 }
-ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max)
+static ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max)
 {
 	if (max < 4)
 		return -1;
@@ -571,7 +572,7 @@ ssize_t cortexm_reg_read(target *t, int reg, void *data, size_t max)
 	return 4;
 }
 
-ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max)
+static ssize_t cortexm_reg_write(target *t, int reg, const void *data, size_t max)
 {
 	if (max < 4)
 		return -1;
@@ -713,7 +714,7 @@ static enum target_halt_reason cortexm_halt_poll(target *t, target_addr *watch)
 	return TARGET_HALT_BREAKPOINT;
 }
 
-void cortexm_halt_resume(target *t, bool step)
+static void cortexm_halt_resume(target *t, bool step)
 {
 	struct cortexm_priv *priv = t->priv;
 	uint32_t dhcsr = CORTEXM_DHCSR_DBGKEY | CORTEXM_DHCSR_C_DEBUGEN;
diff --git a/src/target/cortexm.h b/src/target/cortexm.h
index 927d9d66..01077620 100644
--- a/src/target/cortexm.h
+++ b/src/target/cortexm.h
@@ -175,7 +175,6 @@ ADIv5_AP_t *cortexm_ap(target *t);
 
 bool cortexm_attach(target *t);
 void cortexm_detach(target *t);
-void cortexm_halt_resume(target *t, bool step);
 int cortexm_run_stub(target *t, uint32_t loadaddr,
                      uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3);
 int cortexm_mem_write_sized(
diff --git a/src/target/lmi.c b/src/target/lmi.c
index 54cd19ce..14ae3495 100644
--- a/src/target/lmi.c
+++ b/src/target/lmi.c
@@ -104,7 +104,7 @@ bool lmi_probe(target *t)
 	return false;
 }
 
-int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
+static int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
 {
 	target  *t = f->t;
 
@@ -128,7 +128,7 @@ int lmi_flash_erase(struct target_flash *f, target_addr addr, size_t len)
 	return 0;
 }
 
-int lmi_flash_write(struct target_flash *f,
+static int lmi_flash_write(struct target_flash *f,
                     target_addr dest, const void *src, size_t len)
 {
 	target  *t = f->t;
diff --git a/src/target/samd.c b/src/target/samd.c
index 3507d020..2a5c7e03 100644
--- a/src/target/samd.c
+++ b/src/target/samd.c
@@ -329,7 +329,7 @@ samd20_revB_detach(target *t)
 static void
 samd20_revB_halt_resume(target *t, bool step)
 {
-	cortexm_halt_resume(t, step);
+	target_halt_resume(t, step);
 
 	/* ---- Additional ---- */
 	/* Exit extended reset */
diff --git a/src/target/stm32f4.c b/src/target/stm32f4.c
index 4f874f63..68b37cdc 100644
--- a/src/target/stm32f4.c
+++ b/src/target/stm32f4.c
@@ -518,7 +518,7 @@ static bool stm32f4_cmd_erase_mass(target *t, int argc, const char **argv)
  * * Documentation for F413 with OPTCR default = 0ffffffed seems wrong!
  */
 
-bool optcr_mask(target *t, uint32_t *val)
+static bool optcr_mask(target *t, uint32_t *val)
 {
 	switch (t->idcode) {
 	case ID_STM32F20X: