From a1bd228c87d1b73f6cfecf000eec0a8765a11b01 Mon Sep 17 00:00:00 2001 From: Piotr Esden-Tempski Date: Fri, 28 Jan 2011 15:11:52 -0800 Subject: [PATCH] Replaced OC mode selection with an enum, makes it simpler to use. --- .../stm32/stm32-h103/pwm_6step/pwm_6step.c | 6 +- include/libopencm3/stm32/timer.h | 16 ++- lib/stm32/timer.c | 110 +++++++++++++++++- 3 files changed, 122 insertions(+), 10 deletions(-) diff --git a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c index b35a4ba1..d769e3a4 100644 --- a/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c +++ b/examples/stm32/stm32-h103/pwm_6step/pwm_6step.c @@ -104,7 +104,7 @@ void tim_setup(void) timer_disable_oc_clear(TIM1, TIM_OC1); timer_enable_oc_preload(TIM1, TIM_OC1); timer_set_oc_slow_mode(TIM1, TIM_OC1); - timer_set_oc_mode(TIM1, TIM_OC1, TIM_CCMR1_OC1M_PWM1); + timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); /* Configure OC1. */ timer_set_oc_polarity_high(TIM1, TIM_OC1); @@ -131,7 +131,7 @@ void tim_setup(void) timer_disable_oc_clear(TIM1, TIM_OC2); timer_enable_oc_preload(TIM1, TIM_OC2); timer_set_oc_slow_mode(TIM1, TIM_OC2); - timer_set_oc_mode(TIM1, TIM_OC2, TIM_CCMR1_OC2M_PWM1); + timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); /* Configure OC2. */ timer_set_oc_polarity_high(TIM1, TIM_OC2); @@ -158,7 +158,7 @@ void tim_setup(void) timer_disable_oc_clear(TIM1, TIM_OC3); timer_enable_oc_preload(TIM1, TIM_OC3); timer_set_oc_slow_mode(TIM1, TIM_OC3); - timer_set_oc_mode(TIM1, TIM_OC3, TIM_CCMR2_OC3M_PWM1); + timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); /* Configure OC3. */ timer_set_oc_polarity_high(TIM1, TIM_OC3); diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index 603a97c5..1cd5d0ef 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -828,7 +828,7 @@ /* --- TIMx convenience defines -------------------------------------------- */ -/* Capture Compare channel designators */ +/* Output Compare channel designators */ enum tim_oc_id { TIM_OC1=0, TIM_OC1N, @@ -839,6 +839,18 @@ enum tim_oc_id { TIM_OC4, }; +/* Output Compare mode designators */ +enum tim_oc_mode { + TIM_OCM_FROZEN, + TIM_OCM_ACTIVE, + TIM_OCM_INACTIVE, + TIM_OCM_TOGGLE, + TIM_OCM_FORCE_LOW, + TIM_OCM_FORCE_HIGH, + TIM_OCM_PWM1, + TIM_OCM_PWM2, +}; + /* --- TIM functions ------------------------------------------------------- */ void timer_set_mode(u32 timer_peripheral, u8 clock_div, u8 alignment, u8 direction); @@ -872,7 +884,7 @@ void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, u32 mode); +void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode); void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id); diff --git a/lib/stm32/timer.c b/lib/stm32/timer.c index 152b69f6..25001a1a 100644 --- a/lib/stm32/timer.c +++ b/lib/stm32/timer.c @@ -268,32 +268,132 @@ void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id) } } -void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, u32 mode) +void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode) { switch (oc_id) { case TIM_OC1: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK; TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC1S_OUT; TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1M_MASK; - TIM_CCMR1(timer_peripheral) |= mode; + switch (oc_mode) { + case TIM_OCM_FROZEN: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FROZEN; + break; + case TIM_OCM_ACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_ACTIVE; + break; + case TIM_OCM_INACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_INACTIVE; + break; + case TIM_OCM_TOGGLE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_TOGGLE; + break; + case TIM_OCM_FORCE_LOW: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW; + break; + case TIM_OCM_FORCE_HIGH: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_HIGH; + break; + case TIM_OCM_PWM1: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1; + break; + case TIM_OCM_PWM2: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM2; + break; + } break; case TIM_OC2: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK; TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC2S_OUT; TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2M_MASK; - TIM_CCMR1(timer_peripheral) |= mode; + switch (oc_mode) { + case TIM_OCM_FROZEN: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FROZEN; + break; + case TIM_OCM_ACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_ACTIVE; + break; + case TIM_OCM_INACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_INACTIVE; + break; + case TIM_OCM_TOGGLE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_TOGGLE; + break; + case TIM_OCM_FORCE_LOW: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW; + break; + case TIM_OCM_FORCE_HIGH: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_HIGH; + break; + case TIM_OCM_PWM1: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1; + break; + case TIM_OCM_PWM2: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM2; + break; + } break; case TIM_OC3: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK; TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC3S_OUT; TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK; - TIM_CCMR2(timer_peripheral) |= mode; + switch (oc_mode) { + case TIM_OCM_FROZEN: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN; + break; + case TIM_OCM_ACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE; + break; + case TIM_OCM_INACTIVE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE; + break; + case TIM_OCM_TOGGLE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_TOGGLE; + break; + case TIM_OCM_FORCE_LOW: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW; + break; + case TIM_OCM_FORCE_HIGH: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_HIGH; + break; + case TIM_OCM_PWM1: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1; + break; + case TIM_OCM_PWM2: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM2; + break; + } break; case TIM_OC4: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK; TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC4S_OUT; TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK; - TIM_CCMR2(timer_peripheral) |= mode; + switch (oc_mode) { + case TIM_OCM_FROZEN: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN; + break; + case TIM_OCM_ACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE; + break; + case TIM_OCM_INACTIVE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE; + break; + case TIM_OCM_TOGGLE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_TOGGLE; + break; + case TIM_OCM_FORCE_LOW: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW; + break; + case TIM_OCM_FORCE_HIGH: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_HIGH; + break; + case TIM_OCM_PWM1: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1; + break; + case TIM_OCM_PWM2: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM2; + break; + } break; case TIM_OC1N: case TIM_OC2N: