Added basic NVIC register defs and functions.
This commit is contained in:
Piotr Esden-Tempski
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6fe7e25a8a
commit
a38fc2c3a2
@ -32,5 +32,6 @@
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#include <libopenstm32/flash.h>
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#include <libopenstm32/usb.h>
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#include <libopenstm32/usb_desc.h>
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#include <libopenstm32/nvic.h>
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#endif
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@ -20,6 +20,43 @@
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#ifndef LIBOPENSTM32_MEMORYMAP_H
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#define LIBOPENSTM32_MEMORYMAP_H
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/* --- ARM Cortex-M3 specific definitions ---------------------------------- */
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/* Private peripheral bus - Internal */
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#define PPBI_BASE 0xE0000000
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#define ITM_BASE (PPBI_BASE + 0x0000)
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#define DWT_BASE (PPBI_BASE + 0x1000)
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#define FPB_BASE (PPBI_BASE + 0x2000)
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/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
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#define SCS_BASE (PPBI_BASE + 0xE000)
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/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
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/* --- ITM: Instrumentation Trace Macrocell --- */
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/* TODO */
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/* --- DWT: Data Watchpoint and Trace unit --- */
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/* TODO */
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/* --- FPB: Flash Patch and Breakpoint unit --- */
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/* TODO */
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/* --- SCS: System Control Space --- */
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/* ITR: Interrupt Type Register */
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#define ITR_BASE (SCS_BASE + 0x0000)
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/* SYS_TICK: System Timer */
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#define SYS_TICK_BASE (SCS_BASE + 0x0010)
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/* NVIC: Nested Vector Interrupt Controller */
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#define NVIC_BASE (SCS_BASE + 0x0100)
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/* SCB: System Control Block */
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#define SCB_BASE (SCS_BASE + 0x0D00)
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/* STE: Software Trigger Interrupt Register */
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#define STIR_BASE (SCS_BASE + 0x0F00)
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/* ID: ID space */
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#define ID_BASE (SCS_BASE + 0x0FD0)
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/* --- STM32 specific peripheral definitions ------------------------------- */
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/* Memory map for all busses */
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#define PERIPH_BASE 0x40000000
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#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
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116
include/libopenstm32/nvic.h
Normal file
116
include/libopenstm32/nvic.h
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@ -0,0 +1,116 @@
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/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENSTM32_NVIC_H
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#define LIBOPENSTM32_NVIC_H
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#include <libopenstm32.h>
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/* --- NVIC Registers ------------------------------------------------------ */
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/* ISER: Interrupt Set Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4))
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/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
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/* ICER: Interrupt Clear Enable Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4))
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/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
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/* ISPR: Interrupt Set Priority Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4))
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/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
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/* ICPR: Interrupt Clear Priority Registers */
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/* Note: 8 32bit Registers */
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#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4))
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/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
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/* IABR: Interrupt Active Bit Register */
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/* Note: 8 32bit Registers */
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#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4))
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/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
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/* IPR: Interrupt Priority Registers */
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/* Note: 240 8bit Registers */
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#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id)
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/* STIR: Software Trigger Interrupt Register */
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#define NVIC_STIR MMIO32(STIR_BASE)
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/* --- SCB: Registers ------------------------------------------------------ */
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/* CPUID: CPUID base register */
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#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
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/* ICSR: Interrupt Control State Register */
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#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
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/* VTOR: Vector Table Offset Register */
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#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
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/* AIRCR: Application Interrupt and Reset Control Register */
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#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
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/* SCR: System Control Register */
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#define SCB_SCR MMIO32(SCB_BASE + 0x10)
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/* CCR: Configuration Control Register */
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#define SCB_CCR MMIO32(SCB_BASE + 0x14)
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/* SHP: System Handler Priority Registers */
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/* Note: 12 8bit registers */
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#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
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/* SHCSR: System Handler Control and State Register */
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#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
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/* CFSR: Configurable Fault Status Registers */
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#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
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/* HFSR: Hard Fault Status Register */
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#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
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/* DFSR: Debug Fault Status Register */
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#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
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/* MMFAR: Memory Manage Fault Address Register */
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#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
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/* BFAR: Bus Fault Address Register */
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#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
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/* AFSR: Auxiliary Fault Status Register */
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#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
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/* --- NVIC functions ------------------------------------------------------ */
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void nvic_enable_irq(s32 irqn);
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void nvic_disable_irq(s32 irqn);
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s32 nvic_get_pending_irq(s32 irqn);
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void nvic_set_pending_irq(s32 irqn);
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void nvic_clear_pending_irq(s32 irqn);
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s32 nvic_get_active(s32 irqn);
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#endif /* LIBOPENSTM32_NVIC_H */
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@ -27,7 +27,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../include -fno-common \
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-mcpu=cortex-m3 -mthumb -Wstrict-prototypes
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# ARFLAGS = rcsv
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ARFLAGS = rcs
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OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o
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OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o
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# Be silent per default, but 'make V=1' will show all compiler calls.
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ifneq ($(V),1)
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