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mean 2022-04-02 15:58:18 +02:00 committed by Rachel Mant
parent fb216a2a98
commit a3feae60aa

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@ -39,8 +39,7 @@ static volatile uint32_t magic,sr,ct;
\fn ch32f1_add_flash \fn ch32f1_add_flash
\brief "fast" flash driver for CH32F10x chips \brief "fast" flash driver for CH32F10x chips
*/ */
static void ch32f1_add_flash(target *t, static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t erasesize)
uint32_t addr, size_t length, size_t erasesize)
{ {
struct target_flash *f = calloc(1, sizeof(*f)); struct target_flash *f = calloc(1, sizeof(*f));
if (!f) { /* calloc failed: heap exhaustion */ if (!f) { /* calloc failed: heap exhaustion */
@ -133,16 +132,14 @@ bool ch32f1_probe(target *t)
t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff; t->idcode = target_mem_read32(t, DBGMCU_IDCODE) & 0xfff;
if ((t->cpuid & CPUID_PARTNO_MASK) != CORTEX_M3) if ((t->cpuid & CPUID_PARTNO_MASK) != CORTEX_M3)
return false; return false;
if(t->idcode !=0x410) // only ch32f103 if(t->idcode !=0x410) { // only ch32f103
{
return false; return false;
} }
// try to flock // try to flock
ch32f1_flash_lock(t); ch32f1_flash_lock(t);
// if this fails it is not a CH32 chip // if this fails it is not a CH32 chip
if(ch32f1_flash_unlock(t)) if(ch32f1_flash_unlock(t)) {
{
return false; return false;
} }
@ -171,14 +168,12 @@ int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len)
// Make sure we have 2 wait states, prefetch disabled // Make sure we have 2 wait states, prefetch disabled
//target_mem_write32(t, FLASH_ACR , 2); //target_mem_write32(t, FLASH_ACR , 2);
if (ch32f1_flash_unlock(t)) if (ch32f1_flash_unlock(t)) {
{
ERROR_CH("CH32: Unlock failed\n"); ERROR_CH("CH32: Unlock failed\n");
return -1; return -1;
} }
// Fast Erase 128 bytes pages (ch32 mode) // Fast Erase 128 bytes pages (ch32 mode)
while(len) while(len) {
{
SET_CR(FLASH_CR_FTER_CH32);// CH32 PAGE_ER SET_CR(FLASH_CR_FTER_CH32);// CH32 PAGE_ER
/* write address to FMA */ /* write address to FMA */
target_mem_write32(t, FLASH_AR , addr); target_mem_write32(t, FLASH_AR , addr);
@ -197,8 +192,7 @@ int ch32f1_flash_erase (struct target_flash *f, target_addr addr, size_t len)
} }
sr = target_mem_read32(t, FLASH_SR); sr = target_mem_read32(t, FLASH_SR);
ch32f1_flash_lock(t); ch32f1_flash_lock(t);
if ((sr & SR_ERROR_MASK)) if ((sr & SR_ERROR_MASK)) {
{
ERROR_CH("ch32f1 flash erase error 0x%" PRIx32 "\n", sr); ERROR_CH("ch32f1 flash erase error 0x%" PRIx32 "\n", sr);
return -1; return -1;
} }
@ -220,8 +214,7 @@ static bool waitFlashReady(target *t,uint32_t adr)
// these are the data from the previous operation and they could be ffff) // these are the data from the previous operation and they could be ffff)
uint32_t ff; uint32_t ff;
for(int i=0;i<32;i++) ff=target_mem_read32(t,adr); for(int i=0;i<32;i++) ff=target_mem_read32(t,adr);
if(ff!=0xffffffffUL) if(ff!=0xffffffffUL) {
{
ERROR_CH("ch32f1 Not erased properly at %x or flash access issue\n",adr); ERROR_CH("ch32f1 Not erased properly at %x or flash access issue\n",adr);
return false; return false;
} }
@ -279,8 +272,7 @@ static int ch32f1_flash_write(struct target_flash *f,
while(length>0) while(length>0)
{ {
if(ch32f1_flash_unlock(t)) if(ch32f1_flash_unlock(t)) {
{
ERROR_CH("ch32f1 cannot fast unlock\n"); ERROR_CH("ch32f1 cannot fast unlock\n");
return -1; return -1;
} }
@ -289,18 +281,15 @@ static int ch32f1_flash_write(struct target_flash *f,
// Buffer reset... // Buffer reset...
ch32_buffer_clear(t); ch32_buffer_clear(t);
// Load 128 bytes to buffer // Load 128 bytes to buffer
if(!waitFlashReady(t,dest)) if(!waitFlashReady(t,dest)) {
{
return -1; return -1;
} }
for(int i=0;i<8;i++) for(int i=0;i<8;i++) {
{ if(upload(t,dest,src, 16*i)) {
if(upload(t,dest,src, 16*i))
{
ERROR_CH("Cannot upload to buffer\n"); ERROR_CH("Cannot upload to buffer\n");
return -1;
} }
} }
// write buffer // write buffer
SET_CR(FLASH_CR_FTPG_CH32); SET_CR(FLASH_CR_FTPG_CH32);
target_mem_write32(t, FLASH_AR, dest); // 10 target_mem_write32(t, FLASH_AR, dest); // 10
@ -321,8 +310,7 @@ static int ch32f1_flash_write(struct target_flash *f,
sr = target_mem_read32(t, FLASH_SR); // 13 sr = target_mem_read32(t, FLASH_SR); // 13
ch32f1_flash_lock(t); ch32f1_flash_lock(t);
if ((sr & SR_ERROR_MASK) ) if ((sr & SR_ERROR_MASK) ) {
{
ERROR_CH("ch32f1 flash write error 0x%" PRIx32 "\n", sr); ERROR_CH("ch32f1 flash write error 0x%" PRIx32 "\n", sr);
return -1; return -1;
} }