efm32 tinygecko gpio: implemented all the bit values
along with the actual implementation comes a first attempt to better structure the doxygen groups. putting all the groups in a bigger one makes it easier to reference them from the file itself, and makes the structure clearer on the module page.
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@ -24,11 +24,8 @@
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* This corresponds to the description in d0034_efm32tg_reference_manual.pdf
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* section 28.
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*
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* @see GPIO_registers
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* @see GPIO_MODE_values
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* @see EFM32TG_GPIO
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*/
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/* FIXME: i'd prefer not to @see CMU_registers but have some direct link placed
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* automatically from a file to its groups */
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#ifndef LIBOPENCM3_EFM32_TINYGECKO_GPIO_H
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#define LIBOPENCM3_EFM32_TINYGECKO_GPIO_H
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@ -36,6 +33,12 @@
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/efm32/memorymap.h>
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/** Register definitions and register value definitions for the GPIO subsystem
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*
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* @defgroup EFM32TG_GPIO EFM32 Tiny Gecko GPIO registers and values
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* @{
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*/
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/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 28.4
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*
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* The bulk of the registers defined here (like GPIO_PA_CTRL) will not be used
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@ -43,7 +46,7 @@
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*
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* @todo This section could profit from bit-banding.
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*
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* @defgroup GPIO_registers GPIO registers
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* @defgroup EFM32TG_GPIO_registers EFM32 Tiny Gecko GPIO registers
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* @{
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*/
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#define GPIO_Px_CTRL_OFFSET 0x000
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@ -141,8 +144,29 @@
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/** @} */
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/** These are the modes defined for the MODEx fields in the MODEL/MODEH
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* registers.
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/** Bit states for the GPIO_Px_CTRL register
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*
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* They are named as in d0034_efm32tg_reference_manual.pdf's section
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* 28.5.1.
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*
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* @defgroup EFM32TG_GPIO_Px_CTRL_bits EFM32 Tiny Gecko GPIO Px CTRL bits
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* @{
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*/
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#define GPIO_CTRL_DRIVEMODE_STANDARD 0 /**< 6mA drive current */
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#define GPIO_CTRL_DRIVEMODE_LOWEST 1 /**< 0.5mA drive current */
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#define GPIO_CTRL_DRIVEMODE_HIGH 2 /**< 20mA drive current */
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#define GPIO_CTRL_DRIVEMODE_LOW 3 /**< 2mA drive current */
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/** @} */
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/** These are the modes defined for the MODEx fields in the GPIO_Px_MODEL and
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* GPIO_Px_MODEH registers.
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*
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* These bit state definitions are not localized, meaning that they have to be
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* bitshifted by multiples of 4 to configure other pins than 0; configurations
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* for pins 0 to 7 go to GPIO_Px_MODEL (shifted by 4*pin), configurations for
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* pins 8 to 15 go to GPIO_Px_MODEH (shifted by 4*(pin-8)).
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*
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* For example, to set the mode for the 3rd pin of port A to pushpull, set
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* `GPIO_PA_MODEL = GPIO_MODE_PUSHPULL << (3*4);`.
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@ -154,7 +178,7 @@
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* 28.5.2/28.5.3. For explanations of what they really do, rather see section
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* 28.3.1.
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*
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* @defgroup GPIO_MODE_values GPIO MODE values
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* @defgroup EFM32TG_GPIO_MODE_values EFM32 Tiny Gecko GPIO MODE values
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* @{
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*/
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@ -177,6 +201,165 @@
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/** @} */
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/** These are the modes defined for the EXTIPSELx fields in the GPIO_EXTIPSELL
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* and GPIO_EXTIPSELH registers.
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*
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* These bit state definitions are not localized, meaning that they have to be
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* bitshifted by multiples of 4 to configure other pins than 0; configurations
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* for pins 0 to 7 go to GPIO_EXTIPSELL (shifted by 4*pin), configurations for
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* pins 8 to 15 go to GPIO_EXTIPSELH (shifted by 4*(pin-8)).
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*
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* They are named as in d0034_efm32tg_reference_manual.pdf's sections
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* 28.5.10/28.5.11. For explanations of what they do, rather see section
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* 28.3.5.
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*
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* @defgroup EFM32TG_GPIO_EXTIP_values EFM32 Tiny Gecko GPIO EXTIPSEL values
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* @{
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*/
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#define GPIO_EXTIPSEL_PORTA 0 /**< Port A pin x selected for external interrupt x */
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#define GPIO_EXTIPSEL_PORTB 1 /**< Port B pin x selected for external interrupt x */
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#define GPIO_EXTIPSEL_PORTC 2 /**< Port C pin x selected for external interrupt x */
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#define GPIO_EXTIPSEL_PORTD 3 /**< Port D pin x selected for external interrupt x */
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#define GPIO_EXTIPSEL_PORTE 4 /**< Port E pin x selected for external interrupt x */
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#define GPIO_EXTIPSEL_PORTF 5 /**< Port F pin x selected for external interrupt x */
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/** @} */
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/** Bit states for the GPIO_ROUTE register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.18 for definitions, and
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* 28.3.4.1 for explanations.
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*
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* @defgroup EFM32TG_GPIO_ROUTE_bits EFM32 Tiny Gecko GPIO ROUTE bits
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* @{
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*/
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#define GPIO_ROUTE_SWLOCATION_MASK (0x03<<8)
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#define GPIO_ROUTE_SWLOCATION_LOC0 (0<<8) /**< Route SW pins to location 0 (see chip data sheet for exact pins */
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#define GPIO_ROUTE_SWLOCATION_LOC1 (1<<8) /**< Route SW pins to location 1 (see chip data sheet for exact pins */
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#define GPIO_ROUTE_SWLOCATION_LOC2 (2<<8) /**< Route SW pins to location 2 (see chip data sheet for exact pins */
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#define GPIO_ROUTE_SWLOCATION_LOC3 (3<<8) /**< Route SW pins to location 3 (see chip data sheet for exact pins */
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#define GPIO_ROUTE_SWOPEN (1<<2) /**< Serial Wire Viewer Output pin enabled */
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#define GPIO_ROUTE_SWDIOPEN (1<<1) /**< Serial Wire Data pin enabled */
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#define GPIO_ROUTE_SWCLKPEN (1<<0) /**< Serial Wire Clock pin enabled */
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/** @} */
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/** Bit states for the GPIO_INSENSE register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.19 for definitions, and
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* 28.3.7 for details.
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*
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* @defgroup EFM32TG_GPIO_INSENSE_bits EFM32 Tiny Gecko GPIO INSENSE bits
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* @{
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*/
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#define GPIO_INSENSE_PRS (1<<1) /**< Input sensing for PRS enabled */
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#define GPIO_INSENSE_INT (1<<0) /**< Input sensing for interrupts enabled */
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/** @} */
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/** Values for the GPIO_LOCK register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.20 for definitions, and
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* 28.3.1.1 for explanations.
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*
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* @defgroup EFM32TG_GPIO_LOCK_values EFM32 Tiny Gecko GPIO LOCK bits
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* @{
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*/
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#define GPIO_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */
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#define GPIO_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */
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#define GPIO_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock down GPIO */
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#define GPIO_LOCK_SET_UNLOCKED 0xa543 /**< Write this to the LOCK register to unlock the GPIO */
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/** @} */
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/** Bit states for the GPIO_CTRL register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.21 for definitions, and
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* 28.3.4 for explanations.
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*
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* @defgroup EFM32TG_GPIO_CTRL_bits EFM32 Tiny Gecko GPIO CTRL bits
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* @{
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*/
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#define GPIO_CTRL_EM4RET (1<<0) /**< Retention of states in EM4 */
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/** @} */
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/** Bit states for the GPIO_CMD register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.22 for definitions and
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* figure 28.5 in case you wonder if that register is mentioned anywhere else
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* at all.
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*
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* @defgroup EFM32TG_GPIO_CMD_bits EFM32 Tiny Gecko GPIO CMD bits
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* @{
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*/
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#define GPIO_CMD_EM4WUCLR (1<<0) /**< Write this flag to clear EM4 wakeup requests */
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/** @} */
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/** Bit states for the GPIO_EM4WUEN register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.23 for definitions, and
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* 28.3.2 for explanations.
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*
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* @defgroup EFM32TG_GPIO_EM4WUEN_bits EFM32 Tiny Gecko GPIO EM4WUEN bits
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* @{
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*/
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#define GPIO_EM4WUEN_A0 0x01 /**< Wake up from EM4 on A0 activity */
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#define GPIO_EM4WUEN_A6 0x02 /**< Wake up from EM4 on A6 activity */
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#define GPIO_EM4WUEN_C9 0x04 /**< Wake up from EM4 on C9 activity */
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#define GPIO_EM4WUEN_F1 0x08 /**< Wake up from EM4 on F1 activity */
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#define GPIO_EM4WUEN_F3 0x10 /**< Wake up from EM4 on F3 activity */
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#define GPIO_EM4WUEN_E13 0x20 /**< Wake up from EM4 on E13 activity */
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/** @} */
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/** Bit states for the GPIO_EM4WUPOL register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.24 for definitions, and
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* 28.3.2 for explanations.
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*
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* @defgroup EFM32TG_GPIO_EM4WUPOL_bits EFM32 Tiny Gecko GPIO EM4WUPOL bits
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* @{
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*/
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#define GPIO_EM4WUPOL_A0 0x01 /**< High wake up from EM4 on A0 */
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#define GPIO_EM4WUPOL_A6 0x02 /**< High wake up from EM4 on A6 */
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#define GPIO_EM4WUPOL_C9 0x04 /**< High wake up from EM4 on C9 */
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#define GPIO_EM4WUPOL_F1 0x08 /**< High wake up from EM4 on F1 */
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#define GPIO_EM4WUPOL_F3 0x10 /**< High wake up from EM4 on F3 */
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#define GPIO_EM4WUPOL_E13 0x20 /**< High wake up from EM4 on E13 */
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/** @} */
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/** Bit states for the GPIO_EM4WUCAUSE register
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*
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* See d0034_efm32tg_reference_manual.pdf section 28.5.25 for definitions, and
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* 28.3.2 for explanations.
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*
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* @defgroup EFM32TG_GPIO_EM4WUCAUSE_bits EFM32 Tiny Gecko GPIO EM4WUCAUSE bits
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* @{
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*/
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#define GPIO_EM4WUCAUSE_A0 0x01 /**< Woke up from EM4 on A0 */
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#define GPIO_EM4WUCAUSE_A6 0x02 /**< Woke up from EM4 on A6 */
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#define GPIO_EM4WUCAUSE_C9 0x04 /**< Woke up from EM4 on C9 */
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#define GPIO_EM4WUCAUSE_F1 0x08 /**< Woke up from EM4 on F1 */
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#define GPIO_EM4WUCAUSE_F3 0x10 /**< Woke up from EM4 on F3 */
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#define GPIO_EM4WUCAUSE_E13 0x20 /**< Woke up from EM4 on E13 */
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/** @} */
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/** @} */
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//void gpio_set(u32 gpioport, u16 gpios);
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//void gpio_clear(u32 gpioport, u16 gpios);
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//void gpio_toggle(u32 gpioport, u16 gpios);
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