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stm32f4: rcc: drop 48 & 120 MHz configs

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48Mhz has no purpose other than to be a naiive method of haivng working
USB.  120MHz never had any purpose, other than to match the f2 code it
was copied from.  Drop them both.  Remaining configs are all max speeds
for various F4 parts.  Lower speeds are all custom
This commit is contained in:
Karl Palsson 2019-06-02 10:50:10 +00:00
parent 1d68c299e8
commit a9dde2832e
2 changed files with 0 additions and 172 deletions
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2
include/libopencm3/stm32/f4/rcc.h
View File

@ -770,9 +770,7 @@ extern uint32_t rcc_apb2_frequency;
/* --- Function prototypes ------------------------------------------------- */
enum rcc_clock_3v3 {
RCC_CLOCK_3V3_48MHZ,
RCC_CLOCK_3V3_84MHZ,
RCC_CLOCK_3V3_120MHZ,
RCC_CLOCK_3V3_168MHZ,
RCC_CLOCK_3V3_180MHZ,
RCC_CLOCK_3V3_END

170
lib/stm32/f4/rcc.c
View File

@ -50,23 +50,6 @@ uint32_t rcc_apb1_frequency = 16000000;
uint32_t rcc_apb2_frequency = 16000000;
const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 16,
.plln = 96,
.pllp = 2,
.pllq = 2,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_1WS,
.ahb_frequency = 48000000,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 84MHz */
.pllm = 16,
.plln = 336,
@ -84,23 +67,6 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 120MHz */
.pllm = 16,
.plln = 240,
.pllp = 2,
.pllq = 5,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_3WS,
.ahb_frequency = 120000000,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 16,
.plln = 336,
@ -138,23 +104,6 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
};
const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 8,
.plln = 96,
.pllp = 2,
.pllq = 2,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_1WS,
.ahb_frequency = 48000000,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 84MHz */
.pllm = 8,
.plln = 336,
@ -172,23 +121,6 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 120MHz */
.pllm = 8,
.plln = 240,
.pllp = 2,
.pllq = 5,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_3WS,
.ahb_frequency = 120000000,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 8,
.plln = 336,
@ -226,23 +158,6 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
};
const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 12,
.plln = 96,
.pllp = 2,
.pllq = 2,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_1WS,
.ahb_frequency = 48000000,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 84MHz */
.pllm = 12,
.plln = 336,
@ -260,23 +175,6 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 120MHz */
.pllm = 12,
.plln = 240,
.pllp = 2,
.pllq = 5,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_3WS,
.ahb_frequency = 120000000,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 12,
.plln = 336,
@ -314,23 +212,6 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
};
const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 16,
.plln = 96,
.pllp = 2,
.pllq = 2,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_1WS,
.ahb_frequency = 48000000,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 84MHz */
.pllm = 16,
.plln = 336,
@ -348,23 +229,6 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 120MHz */
.pllm = 16,
.plln = 240,
.pllp = 2,
.pllq = 5,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_3WS,
.ahb_frequency = 120000000,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 16,
.plln = 336,
@ -402,23 +266,6 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
};
const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 25,
.plln = 96,
.pllp = 2,
.pllq = 2,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_1WS,
.ahb_frequency = 48000000,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 84MHz */
.pllm = 25,
.plln = 336,
@ -436,23 +283,6 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
{ /* 120MHz */
.pllm = 25,
.plln = 240,
.pllp = 2,
.pllq = 5,
.pllr = 0,
.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
FLASH_ACR_LATENCY_3WS,
.ahb_frequency = 120000000,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 25,
.plln = 336,