From ab9e425272da388def7d17ce322deaf343295d50 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 May 2018 21:28:11 +0000 Subject: [PATCH] stm32f3: rcc: add hse preconfigurations Just a single 8Mhz in, 72mhz (max) out, which suits the f3 discovery boards for instance. --- include/libopencm3/stm32/f3/rcc.h | 16 +++++++++++----- lib/stm32/f3/rcc.c | 18 +++++++++++++++++- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/include/libopencm3/stm32/f3/rcc.h b/include/libopencm3/stm32/f3/rcc.h index e8627e98..0e1b38c0 100644 --- a/include/libopencm3/stm32/f3/rcc.h +++ b/include/libopencm3/stm32/f3/rcc.h @@ -413,11 +413,16 @@ extern uint32_t rcc_apb2_frequency; /* --- Function prototypes ------------------------------------------------- */ -enum rcc_clock { - RCC_CLOCK_48MHZ, - RCC_CLOCK_64MHZ, - RCC_CLOCK_END +enum rcc_clock_hsi { + RCC_CLOCK_HSI_48MHZ, + RCC_CLOCK_HSI_64MHZ, /* Max from HSI */ + RCC_CLOCK_HSI_END }; +enum rcc_clock_hse8 { + RCC_CLOCK_HSE8_72MHZ, + RCC_CLOCK_HSE8_END +}; + struct rcc_clock_scale { uint8_t pllsrc; @@ -434,7 +439,8 @@ struct rcc_clock_scale { uint32_t apb2_frequency; }; -extern const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END]; +extern const struct rcc_clock_scale rcc_configs[RCC_CLOCK_HSI_END]; +extern const struct rcc_clock_scale rcc_hse8mhz_configs[RCC_CLOCK_HSE8_END]; enum rcc_osc { RCC_PLL, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI diff --git a/lib/stm32/f3/rcc.c b/lib/stm32/f3/rcc.c index 8cd5cbf5..0fdb9a48 100644 --- a/lib/stm32/f3/rcc.c +++ b/lib/stm32/f3/rcc.c @@ -44,7 +44,7 @@ uint32_t rcc_ahb_frequency = 8000000; uint32_t rcc_apb1_frequency = 8000000; uint32_t rcc_apb2_frequency = 8000000; -const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = { +const struct rcc_clock_scale rcc_hsi_configs[] = { { /* 48MHz */ .pllmul = RCC_CFGR_PLLMUL_MUL12, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, @@ -69,6 +69,22 @@ const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = { } }; +const struct rcc_clock_scale rcc_hse8mhz_configs[] = { + { + .pllsrc = RCC_CFGR_PLLSRC_HSE_PREDIV, + .pllmul = RCC_CFGR_PLLMUL_MUL9, + .plldiv = RCC_CFGR2_PREDIV_NODIV, + .usbdiv1 = false, + .flash_waitstates = 2, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE1_DIV_2, + .ppre2 = RCC_CFGR_PPRE2_DIV_NONE, + .ahb_frequency = 72e6, + .apb1_frequency = 32e6, + .apb2_frequency = 72e6, + } +}; + void rcc_osc_ready_int_clear(enum rcc_osc osc) { switch (osc) {