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[f4] Added a 25mhz clock

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Freek van Tienen 2014-05-08 10:02:18 +02:00 committed by Frantisek Burian
parent 67f4f50a94
commit ac8ac8c64d
2 changed files with 45 additions and 0 deletions
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1
include/libopencm3/stm32/f4/rcc.h
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@ -506,6 +506,7 @@ typedef struct {
extern const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END];
extern const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END];
extern const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END];
extern const clock_scale_t hse_25mhz_3v3[CLOCK_3V3_END];
enum rcc_osc {
PLL, HSE, HSI, LSE, LSI

44
lib/stm32/f4/rcc.c
View File

@ -180,6 +180,50 @@ const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = {
},
};
const clock_scale_t hse_25mhz_3v3[CLOCK_3V3_END] = {
{ /* 48MHz */
.pllm = 25,
.plln = 96,
.pllp = 2,
.pllq = 2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 12000000,
.apb2_frequency = 24000000,
},
{ /* 120MHz */
.pllm = 25,
.plln = 240,
.pllp = 2,
.pllq = 5,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.power_save = 1,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_3WS,
.apb1_frequency = 30000000,
.apb2_frequency = 60000000,
},
{ /* 168MHz */
.pllm = 25,
.plln = 336,
.pllp = 2,
.pllq = 7,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE_DIV_4,
.ppre2 = RCC_CFGR_PPRE_DIV_2,
.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
FLASH_ACR_LATENCY_5WS,
.apb1_frequency = 42000000,
.apb2_frequency = 84000000,
},
};
void rcc_osc_ready_int_clear(enum rcc_osc osc)
{
switch (osc) {