From b1e5c77e1d2be23490f0f0134028c0987a65004f Mon Sep 17 00:00:00 2001 From: Jared Boone Date: Thu, 11 Oct 2012 16:29:27 -0700 Subject: [PATCH] New SGPIO field #defines, generated from sgpio.csv. --- include/libopencm3/lpc43xx/sgpio.h | 1617 ++++++++++++++++++++++++++++ 1 file changed, 1617 insertions(+) diff --git a/include/libopencm3/lpc43xx/sgpio.h b/include/libopencm3/lpc43xx/sgpio.h index cee08d8e..ddb61380 100644 --- a/include/libopencm3/lpc43xx/sgpio.h +++ b/include/libopencm3/lpc43xx/sgpio.h @@ -333,6 +333,1623 @@ LGPL License Terms @ref lgpl_license /* Input bit match interrupt set status */ #define SGPIO_SET_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF74) +/* --- Common register fields ----------------------------------- */ +/* TODO: Generate this stuff with the gen.py script as well! */ + +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) + +#define SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) + +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_MASK (1 << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE(x) ((x) << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) + +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) + +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) + +#define SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) + +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) + +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) + +#define SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG_CONCAT_ENABLE_MASK (1 << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) +#define SGPIO_MUX_CFG_CONCAT_ENABLE(x) ((x) << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) + +#define SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_MASK (1 << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_MASK (1 << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_MASK (1 << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_MASK (1 << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(x) ((x) << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_MASK (1 << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(x) ((x) << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) + +#define SGPIO_POS_POS_SHIFT (0) +#define SGPIO_POS_POS_MASK (0xff << SGPIO_POS_POS_SHIFT) +#define SGPIO_POS_POS(x) ((x) << SGPIO_POS_POS_SHIFT) + +#define SGPIO_POS_POS_RESET_SHIFT (8) +#define SGPIO_POS_POS_RESET_MASK (0xff << SGPIO_POS_POS_RESET_SHIFT) +#define SGPIO_POS_POS_RESET(x) ((x) << SGPIO_POS_POS_RESET_SHIFT) + +/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ + +/* --- SGPIO_OUT_MUX_CFG0 values -------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG0_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG1 values -------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG1_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG2 values -------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG2_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG3 values -------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG3_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG4 values -------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG4_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG5 values -------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG5_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG6 values -------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG6_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG7 values -------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG7_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG8 values -------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG8_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG9 values -------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG9_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG10 values ------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG10_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG11 values ------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG11_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG12 values ------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG12_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG13 values ------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG13_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG14 values ------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG14_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT) + +/* --- SGPIO_OUT_MUX_CFG15 values ------------------------------- */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG15_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT) + +/* --- SGPIO_MUX_CFG0 values ------------------------------------ */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG0_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG0_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG0_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG0_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG0_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG0_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG0_CONCAT_ENABLE (1 << SGPIO_MUX_CFG0_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG0_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG0_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG1 values ------------------------------------ */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG1_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG1_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG1_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG1_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG1_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG1_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG1_CONCAT_ENABLE (1 << SGPIO_MUX_CFG1_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG1_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG1_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG2 values ------------------------------------ */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG2_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG2_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG2_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG2_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG2_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG2_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG2_CONCAT_ENABLE (1 << SGPIO_MUX_CFG2_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG2_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG2_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG3 values ------------------------------------ */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG3_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG3_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG3_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG3_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG3_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG3_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG3_CONCAT_ENABLE (1 << SGPIO_MUX_CFG3_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG3_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG3_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG4 values ------------------------------------ */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG4_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG4_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG4_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG4_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG4_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG4_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG4_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG4_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG4_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG4_CONCAT_ENABLE (1 << SGPIO_MUX_CFG4_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG4_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG4_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG4_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG4_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG4_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG5 values ------------------------------------ */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG5_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG5_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG5_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG5_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG5_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG5_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG5_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG5_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG5_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG5_CONCAT_ENABLE (1 << SGPIO_MUX_CFG5_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG5_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG5_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG5_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG5_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG5_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG6 values ------------------------------------ */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG6_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG6_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG6_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG6_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG6_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG6_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG6_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG6_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG6_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG6_CONCAT_ENABLE (1 << SGPIO_MUX_CFG6_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG6_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG6_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG6_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG6_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG6_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG7 values ------------------------------------ */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG7_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG7_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG7_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG7_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG7_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG7_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG7_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG7_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG7_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG7_CONCAT_ENABLE (1 << SGPIO_MUX_CFG7_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG7_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG7_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG7_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG7_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG7_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG8 values ------------------------------------ */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG8_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG8_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG8_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG8_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG8_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG8_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG8_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG8_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG8_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG8_CONCAT_ENABLE (1 << SGPIO_MUX_CFG8_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG8_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG8_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG8_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG8_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG8_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG9 values ------------------------------------ */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG9_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG9_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG9_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG9_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG9_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG9_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG9_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG9_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG9_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG9_CONCAT_ENABLE (1 << SGPIO_MUX_CFG9_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG9_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG9_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG9_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG9_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG9_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG10 values ----------------------------------- */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG10_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG10_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG10_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG10_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG10_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG10_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG10_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG10_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG10_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG10_CONCAT_ENABLE (1 << SGPIO_MUX_CFG10_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG10_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG10_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG10_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG10_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG10_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG11 values ----------------------------------- */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG11_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG11_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG11_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG11_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG11_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG11_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG11_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG11_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG11_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG11_CONCAT_ENABLE (1 << SGPIO_MUX_CFG11_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG11_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG11_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG11_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG11_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG11_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG12 values ----------------------------------- */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG12_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG12_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG12_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG12_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG12_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG12_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG12_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG12_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG12_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG12_CONCAT_ENABLE (1 << SGPIO_MUX_CFG12_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG12_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG12_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG12_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG12_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG12_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG13 values ----------------------------------- */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG13_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG13_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG13_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG13_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG13_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG13_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG13_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG13_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG13_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG13_CONCAT_ENABLE (1 << SGPIO_MUX_CFG13_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG13_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG13_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG13_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG13_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG13_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG14 values ----------------------------------- */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG14_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG14_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG14_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG14_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG14_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG14_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG14_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG14_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG14_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG14_CONCAT_ENABLE (1 << SGPIO_MUX_CFG14_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG14_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG14_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG14_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG14_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG14_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_MUX_CFG15 values ----------------------------------- */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFG15_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG15_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG15_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFG15_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG15_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG15_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG15_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG15_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFG15_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG15_CONCAT_ENABLE (1 << SGPIO_MUX_CFG15_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFG15_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG15_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG15_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG15_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG15_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG0 values ------------------------------ */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG1 values ------------------------------ */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG1_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG2 values ------------------------------ */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG2_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG3 values ------------------------------ */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG3_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG4 values ------------------------------ */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG4_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG5 values ------------------------------ */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG5_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG6 values ------------------------------ */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG6_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG7 values ------------------------------ */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG7_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG8 values ------------------------------ */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG8_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG9 values ------------------------------ */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG9_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG10 values ----------------------------- */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG10_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG11 values ----------------------------- */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG11_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG12 values ----------------------------- */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG12_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG13 values ----------------------------- */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG13_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG14 values ----------------------------- */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG14_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG15 values ----------------------------- */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG15_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_SHIFT) + +/* --- SGPIO_POS0 values ---------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS0_POS_SHIFT (0) +#define SGPIO_POS0_POS_MASK (0xff << SGPIO_POS0_POS_SHIFT) +#define SGPIO_POS0_POS(x) ((x) << SGPIO_POS0_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS0_POS_RESET_SHIFT (8) +#define SGPIO_POS0_POS_RESET_MASK (0xff << SGPIO_POS0_POS_RESET_SHIFT) +#define SGPIO_POS0_POS_RESET(x) ((x) << SGPIO_POS0_POS_RESET_SHIFT) + +/* --- SGPIO_POS1 values ---------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS1_POS_SHIFT (0) +#define SGPIO_POS1_POS_MASK (0xff << SGPIO_POS1_POS_SHIFT) +#define SGPIO_POS1_POS(x) ((x) << SGPIO_POS1_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS1_POS_RESET_SHIFT (8) +#define SGPIO_POS1_POS_RESET_MASK (0xff << SGPIO_POS1_POS_RESET_SHIFT) +#define SGPIO_POS1_POS_RESET(x) ((x) << SGPIO_POS1_POS_RESET_SHIFT) + +/* --- SGPIO_POS2 values ---------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS2_POS_SHIFT (0) +#define SGPIO_POS2_POS_MASK (0xff << SGPIO_POS2_POS_SHIFT) +#define SGPIO_POS2_POS(x) ((x) << SGPIO_POS2_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS2_POS_RESET_SHIFT (8) +#define SGPIO_POS2_POS_RESET_MASK (0xff << SGPIO_POS2_POS_RESET_SHIFT) +#define SGPIO_POS2_POS_RESET(x) ((x) << SGPIO_POS2_POS_RESET_SHIFT) + +/* --- SGPIO_POS3 values ---------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS3_POS_SHIFT (0) +#define SGPIO_POS3_POS_MASK (0xff << SGPIO_POS3_POS_SHIFT) +#define SGPIO_POS3_POS(x) ((x) << SGPIO_POS3_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS3_POS_RESET_SHIFT (8) +#define SGPIO_POS3_POS_RESET_MASK (0xff << SGPIO_POS3_POS_RESET_SHIFT) +#define SGPIO_POS3_POS_RESET(x) ((x) << SGPIO_POS3_POS_RESET_SHIFT) + +/* --- SGPIO_POS4 values ---------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS4_POS_SHIFT (0) +#define SGPIO_POS4_POS_MASK (0xff << SGPIO_POS4_POS_SHIFT) +#define SGPIO_POS4_POS(x) ((x) << SGPIO_POS4_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS4_POS_RESET_SHIFT (8) +#define SGPIO_POS4_POS_RESET_MASK (0xff << SGPIO_POS4_POS_RESET_SHIFT) +#define SGPIO_POS4_POS_RESET(x) ((x) << SGPIO_POS4_POS_RESET_SHIFT) + +/* --- SGPIO_POS5 values ---------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS5_POS_SHIFT (0) +#define SGPIO_POS5_POS_MASK (0xff << SGPIO_POS5_POS_SHIFT) +#define SGPIO_POS5_POS(x) ((x) << SGPIO_POS5_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS5_POS_RESET_SHIFT (8) +#define SGPIO_POS5_POS_RESET_MASK (0xff << SGPIO_POS5_POS_RESET_SHIFT) +#define SGPIO_POS5_POS_RESET(x) ((x) << SGPIO_POS5_POS_RESET_SHIFT) + +/* --- SGPIO_POS6 values ---------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS6_POS_SHIFT (0) +#define SGPIO_POS6_POS_MASK (0xff << SGPIO_POS6_POS_SHIFT) +#define SGPIO_POS6_POS(x) ((x) << SGPIO_POS6_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS6_POS_RESET_SHIFT (8) +#define SGPIO_POS6_POS_RESET_MASK (0xff << SGPIO_POS6_POS_RESET_SHIFT) +#define SGPIO_POS6_POS_RESET(x) ((x) << SGPIO_POS6_POS_RESET_SHIFT) + +/* --- SGPIO_POS7 values ---------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS7_POS_SHIFT (0) +#define SGPIO_POS7_POS_MASK (0xff << SGPIO_POS7_POS_SHIFT) +#define SGPIO_POS7_POS(x) ((x) << SGPIO_POS7_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS7_POS_RESET_SHIFT (8) +#define SGPIO_POS7_POS_RESET_MASK (0xff << SGPIO_POS7_POS_RESET_SHIFT) +#define SGPIO_POS7_POS_RESET(x) ((x) << SGPIO_POS7_POS_RESET_SHIFT) + +/* --- SGPIO_POS8 values ---------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS8_POS_SHIFT (0) +#define SGPIO_POS8_POS_MASK (0xff << SGPIO_POS8_POS_SHIFT) +#define SGPIO_POS8_POS(x) ((x) << SGPIO_POS8_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS8_POS_RESET_SHIFT (8) +#define SGPIO_POS8_POS_RESET_MASK (0xff << SGPIO_POS8_POS_RESET_SHIFT) +#define SGPIO_POS8_POS_RESET(x) ((x) << SGPIO_POS8_POS_RESET_SHIFT) + +/* --- SGPIO_POS9 values ---------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS9_POS_SHIFT (0) +#define SGPIO_POS9_POS_MASK (0xff << SGPIO_POS9_POS_SHIFT) +#define SGPIO_POS9_POS(x) ((x) << SGPIO_POS9_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS9_POS_RESET_SHIFT (8) +#define SGPIO_POS9_POS_RESET_MASK (0xff << SGPIO_POS9_POS_RESET_SHIFT) +#define SGPIO_POS9_POS_RESET(x) ((x) << SGPIO_POS9_POS_RESET_SHIFT) + +/* --- SGPIO_POS10 values --------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS10_POS_SHIFT (0) +#define SGPIO_POS10_POS_MASK (0xff << SGPIO_POS10_POS_SHIFT) +#define SGPIO_POS10_POS(x) ((x) << SGPIO_POS10_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS10_POS_RESET_SHIFT (8) +#define SGPIO_POS10_POS_RESET_MASK (0xff << SGPIO_POS10_POS_RESET_SHIFT) +#define SGPIO_POS10_POS_RESET(x) ((x) << SGPIO_POS10_POS_RESET_SHIFT) + +/* --- SGPIO_POS11 values --------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS11_POS_SHIFT (0) +#define SGPIO_POS11_POS_MASK (0xff << SGPIO_POS11_POS_SHIFT) +#define SGPIO_POS11_POS(x) ((x) << SGPIO_POS11_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS11_POS_RESET_SHIFT (8) +#define SGPIO_POS11_POS_RESET_MASK (0xff << SGPIO_POS11_POS_RESET_SHIFT) +#define SGPIO_POS11_POS_RESET(x) ((x) << SGPIO_POS11_POS_RESET_SHIFT) + +/* --- SGPIO_POS12 values --------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS12_POS_SHIFT (0) +#define SGPIO_POS12_POS_MASK (0xff << SGPIO_POS12_POS_SHIFT) +#define SGPIO_POS12_POS(x) ((x) << SGPIO_POS12_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS12_POS_RESET_SHIFT (8) +#define SGPIO_POS12_POS_RESET_MASK (0xff << SGPIO_POS12_POS_RESET_SHIFT) +#define SGPIO_POS12_POS_RESET(x) ((x) << SGPIO_POS12_POS_RESET_SHIFT) + +/* --- SGPIO_POS13 values --------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS13_POS_SHIFT (0) +#define SGPIO_POS13_POS_MASK (0xff << SGPIO_POS13_POS_SHIFT) +#define SGPIO_POS13_POS(x) ((x) << SGPIO_POS13_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS13_POS_RESET_SHIFT (8) +#define SGPIO_POS13_POS_RESET_MASK (0xff << SGPIO_POS13_POS_RESET_SHIFT) +#define SGPIO_POS13_POS_RESET(x) ((x) << SGPIO_POS13_POS_RESET_SHIFT) + +/* --- SGPIO_POS14 values --------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS14_POS_SHIFT (0) +#define SGPIO_POS14_POS_MASK (0xff << SGPIO_POS14_POS_SHIFT) +#define SGPIO_POS14_POS(x) ((x) << SGPIO_POS14_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS14_POS_RESET_SHIFT (8) +#define SGPIO_POS14_POS_RESET_MASK (0xff << SGPIO_POS14_POS_RESET_SHIFT) +#define SGPIO_POS14_POS_RESET(x) ((x) << SGPIO_POS14_POS_RESET_SHIFT) + +/* --- SGPIO_POS15 values --------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POS15_POS_SHIFT (0) +#define SGPIO_POS15_POS_MASK (0xff << SGPIO_POS15_POS_SHIFT) +#define SGPIO_POS15_POS(x) ((x) << SGPIO_POS15_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POS15_POS_RESET_SHIFT (8) +#define SGPIO_POS15_POS_RESET_MASK (0xff << SGPIO_POS15_POS_RESET_SHIFT) +#define SGPIO_POS15_POS_RESET(x) ((x) << SGPIO_POS15_POS_RESET_SHIFT) + /**@}*/ #endif