add memory map and irq table for sam3s and sam3u devices

Makefile

@@ -38,7 +38,7 @@ SRCLIBDIR:= $(realpath lib)
 
 TARGETS:= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/l1 lpc13xx lpc17xx \
 	  lpc43xx/m4 lpc43xx/m0 lm3s lm4f \
-	  efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg sam/3x sam/3n
+	  efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg sam/3x sam/3n sam/3s sam/3u
 
 # Be silent per default, but 'make V=1' will show all compiler calls.
 ifneq ($(V),1)

include/libopencm3/dispatch/nvic.h

@@ -33,6 +33,10 @@
 #	include <libopencm3/sam/3x/nvic.h>
 #elif defined(SAM3N)
 #	include <libopencm3/sam/3n/nvic.h>
+#elif defined(SAM3S)
+#	include <libopencm3/sam/3s/nvic.h>
+#elif defined(SAM3U)
+#	include <libopencm3/sam/3u/nvic.h>
 
 #elif defined(LM3S) || defined(LM4F)
 /* Yes, we use the same interrupt table for both LM3S and LM4F */

include/libopencm3/sam/3s/irq.json

@@ -0,0 +1,42 @@
+{
+    "irqs": [
+        "supc",
+        "rstc",
+        "rtc",
+        "rtt",
+        "wdt",
+        "pmc",
+        "eefc",
+        "reserved0",
+        "uart0",
+        "uart1",
+        "smc",
+        "pioa",
+        "piob",
+        "pioc",
+        "usart0",
+        "usart1",
+        "usart2",
+        "reserved1",
+        "hsmci",
+        "twi0",
+        "twi1",
+        "spi",
+        "ssc",
+        "tc0",
+        "tc1",
+        "tc2",
+        "tc3",
+        "tc4",
+        "tc5",
+        "adc",
+        "dacc",
+        "pwm",
+        "crccu",
+        "acc",
+        "udp"
+    ],
+    "partname_humanreadable": "Atmel SAM3S series",
+    "partname_doxygen": "SAM3S",
+    "includeguard": "LIBOPENCM3_SAM3S_NVIC_H"
+}

include/libopencm3/sam/3s/memorymap.h

@@ -0,0 +1,66 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
+ * Copyright (C) 2014 Felix Held <felix-libopencm3@felixheld.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SAM3S_MEMORYMAP_H
+#define SAM3S_MEMORYMAP_H
+
+#include <libopencm3/cm3/common.h>
+
+/* --- SAM3S peripheral space -------------------------------------------- */
+#define HSMCI_BASE			(0x40000000U)
+#define SSC_BASE			(0x40004000U)
+#define SPI_BASE			(0x40008000U)
+#define TC0_BASE			(0x40010000U)
+#define TC1_BASE			(0x40010040U)
+#define TC2_BASE			(0x40010080U)
+#define TC3_BASE			(0x40014000U)
+#define TC4_BASE			(0x40014040U)
+#define TC5_BASE			(0x40014080U)
+#define TWI0_BASE			(0x40018000U)
+#define TWI1_BASE			(0x4001C000U)
+#define PWM_BASE			(0x40020000U)
+#define USART0_BASE			(0x40024000U)
+#define USART1_BASE			(0x40028000U)
+#define USART2_BASE			(0x4002C000U)
+#define UDP_BASE			(0x40034000U)
+#define ADC_BASE			(0x40038000U)
+#define DACC_BASE			(0x4003C000U)
+#define ACC_BASE			(0x40040000U)
+#define CRCCU_BASE			(0x40044000U)
+
+/* --- SAM3S system controller space ------------------------------------- */
+#define SMC_BASE			(0x400E0000U)
+#define MATRIX_BASE			(0x400E0200U)
+#define PMC_BASE			(0x400E0400U)
+#define UART0_BASE			(0x400E0600U)
+#define CHIPID_BASE			(0x400E0740U)
+#define UART1_BASE			(0x400E0800U)
+#define EEFC_BASE			(0x400E0A00U)
+#define PIOA_BASE			(0x400E0E00U)
+#define PIOB_BASE			(0x400E1000U)
+#define PIOC_BASE			(0x400E1200U)
+#define RSTC_BASE			(0x400E1400U)
+#define SUPC_BASE			(0x400E1410U)
+#define RTT_BASE			(0x400E1430U)
+#define WDT_BASE			(0x400E1450U)
+#define RTC_BASE			(0x400E1460U)
+#define GPBR_BASE			(0x400E1490U)
+
+#endif

include/libopencm3/sam/3u/irq.json

@@ -0,0 +1,37 @@
+{
+    "irqs": [
+        "supc",
+        "rstc",
+        "rtc",
+        "rtt",
+        "wdt",
+        "pmc",
+        "eefc0",
+        "eefc1",
+        "uart",
+        "smc",
+        "pioa",
+        "piob",
+        "pioc",
+        "usart0",
+        "usart1",
+        "usart2",
+        "usart3",
+        "hsmci",
+        "twi0",
+        "twi1",
+        "spi",
+        "ssc",
+        "tc0",
+        "tc1",
+        "tc2",
+        "pwm",
+        "adc12b",
+        "adc",
+        "dmac",
+        "udphs"
+    ],
+    "partname_humanreadable": "Atmel SAM3U series",
+    "partname_doxygen": "SAM3U",
+    "includeguard": "LIBOPENCM3_SAM3U_NVIC_H"
+}

include/libopencm3/sam/3u/memorymap.h

@@ -0,0 +1,63 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
+ * Copyright (C) 2014 Felix Held <felix-libopencm3@felixheld.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SAM3U_MEMORYMAP_H
+#define SAM3U_MEMORYMAP_H
+
+#include <libopencm3/cm3/common.h>
+
+/* --- SAM3U peripheral space -------------------------------------------- */
+#define HSMCI_BASE			(0x40000000U)
+#define SSC_BASE			(0x40004000U)
+#define SPI_BASE			(0x40008000U)
+#define TC0_BASE			(0x40080000U)
+#define TC1_BASE			(0x40080040U)
+#define TC2_BASE			(0x40080080U)
+#define TWI0_BASE			(0x40084000U)
+#define TWI1_BASE			(0x40088000U)
+#define PWM_BASE			(0x4008C000U)
+#define USART0_BASE			(0x40090000U)
+#define USART1_BASE			(0x40094000U)
+#define USART2_BASE			(0x40098000U)
+#define USART3_BASE			(0x4009C000U)
+#define UDPHS_BASE			(0x400A4000U)
+#define ADC12B_BASE			(0x400A8000U)
+#define ADC_BASE			(0x400AC000U)
+#define DMAC_BASE			(0x400B0000U)
+
+/* --- SAM3U system controller space ------------------------------------- */
+#define SMC_BASE			(0x400E0000U)
+#define MATRIX_BASE			(0x400E0200U)
+#define PMC_BASE			(0x400E0400U)
+#define UART_BASE			(0x400E0600U)
+#define CHIPID_BASE			(0x400E0740U)
+#define EEFC0_BASE			(0x400E0800U)
+#define EEFC1_BASE			(0x400E0A00U)
+#define PIOA_BASE			(0x400E0C00U)
+#define PIOB_BASE			(0x400E0E00U)
+#define PIOC_BASE			(0x400E1000U)
+#define RSTC_BASE			(0x400E1200U)
+#define SUPC_BASE			(0x400E1210U)
+#define RTT_BASE			(0x400E1230U)
+#define WDT_BASE			(0x400E1250U)
+#define RTC_BASE			(0x400E1260U)
+#define GPBR_BASE			(0x400E1290U)
+
+#endif

include/libopencm3/sam/eefc.h

@@ -71,10 +71,10 @@
 
 static inline void eefc_set_latency(uint8_t wait)
 {
-#if defined(SAM3X)
+#if defined(SAM3X) || defined(SAM3U)
 	EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
 	EEFC_FMR(EEFC1) = (EEFC_FMR(EEFC1) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
-#elif defined(SAM3N)
+#elif defined(SAM3N) || defined(SAM3S)
 	EEFC_FMR(EEFC) = (EEFC_FMR(EEFC) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
 #endif
 }

include/libopencm3/sam/memorymap.h

@@ -24,6 +24,10 @@
 #	include <libopencm3/sam/3x/memorymap.h>
 #elif defined(SAM3N)
 #	include <libopencm3/sam/3n/memorymap.h>
+#elif defined(SAM3S)
+#	include <libopencm3/sam/3s/memorymap.h>
+#elif defined(SAM3U)
+#	include <libopencm3/sam/3u/memorymap.h>
 #else
 #	error "Processor family not defined."
 #endif

lib/dispatch/vector_nvic.c

@@ -33,6 +33,10 @@
 #	include "../sam/3x/vector_nvic.c"
 #elif defined(SAM3N)
 #	include "../sam/3n/vector_nvic.c"
+#elif defined(SAM3S)
+#	include "../sam/3s/vector_nvic.c"
+#elif defined(SAM3U)
+#	include "../sam/3u/vector_nvic.c"
 
 #elif defined(LM3S) || defined(LM4F)
 /* Yes, we use the same interrupt table for both LM3S and LM4F */

lib/sam/3s/Makefile

@@ -0,0 +1,37 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2014 Felix Held <felix-libopencm3@felixheld.de>
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library.  If not, see <http://www.gnu.org/licenses/>.
+##
+
+LIBNAME		= libopencm3_sam3s
+
+PREFIX		?= arm-none-eabi
+
+CC		= $(PREFIX)-gcc
+AR		= $(PREFIX)-ar
+CFLAGS		= -Os -g -Wall -Wextra -I../../../include -fno-common \
+		  -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \
+		  -ffunction-sections -fdata-sections -MD -DSAM3S
+# ARFLAGS	= rcsv
+ARFLAGS		= rcs
+OBJS		= gpio.o pmc.o usart.o
+
+VPATH += ../../usb:../../cm3:../common
+
+include ../../Makefile.include
+

lib/sam/3s/libopencm3_sam3s.ld

@@ -0,0 +1,106 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Generic linker script for STM32 targets using libopencm3. */
+
+/* Memory regions must be defined in the ld script which includes this one. */
+
+/* Enforce emmition of the vector table. */
+EXTERN (vector_table)
+
+/* Define the entry point of the output file. */
+ENTRY(reset_handler)
+
+/* Define sections. */
+SECTIONS
+{
+	.text : {
+		*(.vectors)	/* Vector table */
+		*(.text*)	/* Program code */
+		. = ALIGN(4);
+		*(.rodata*)	/* Read-only data */
+		. = ALIGN(4);
+	} >rom
+
+	/* C++ Static constructors/destructors, also used for __attribute__
+	 * ((constructor)) and the likes */
+	.preinit_array : {
+		. = ALIGN(4);
+		__preinit_array_start = .;
+		KEEP (*(.preinit_array))
+		__preinit_array_end = .;
+	} >rom
+	.init_array : {
+		. = ALIGN(4);
+		__init_array_start = .;
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		__init_array_end = .;
+	} >rom
+	.fini_array : {
+		. = ALIGN(4);
+		__fini_array_start = .;
+		KEEP (*(.fini_array))
+		KEEP (*(SORT(.fini_array.*)))
+		__fini_array_end = .;
+	} >rom
+
+	/*
+	 * Another section used by C++ stuff, appears when using newlib with
+	 * 64bit (long long) printf support
+	 */
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >rom
+	.ARM.exidx : {
+		__exidx_start = .;
+		*(.ARM.exidx*)
+		__exidx_end = .;
+	} >rom
+
+	. = ALIGN(4);
+	_etext = .;
+
+	.data : {
+		_data = .;
+		*(.data*)	/* Read-write initialized data */
+		. = ALIGN(4);
+		_edata = .;
+	} >ram AT >rom
+	_data_loadaddr = LOADADDR(.data);
+
+	.bss : {
+		*(.bss*)	/* Read-write zero initialized data */
+		*(COMMON)
+		. = ALIGN(4);
+		_ebss = .;
+	} >ram
+
+	/*
+	 * The .eh_frame section appears to be used for C++ exception handling.
+	 * You may need to fix this if you're using C++.
+	 */
+	/DISCARD/ : { *(.eh_frame) }
+
+	. = ALIGN(4);
+	end = .;
+}
+
+PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
+

lib/sam/3u/Makefile

@@ -0,0 +1,37 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+## Copyright (C) 2014 Felix Held <felix-libopencm3@felixheld.de>
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library.  If not, see <http://www.gnu.org/licenses/>.
+##
+
+LIBNAME		= libopencm3_sam3u
+
+PREFIX		?= arm-none-eabi
+
+CC		= $(PREFIX)-gcc
+AR		= $(PREFIX)-ar
+CFLAGS		= -Os -g -Wall -Wextra -I../../../include -fno-common \
+		  -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \
+		  -ffunction-sections -fdata-sections -MD -DSAM3U
+# ARFLAGS	= rcsv
+ARFLAGS		= rcs
+OBJS		= gpio.o pmc.o usart.o
+
+VPATH += ../../usb:../../cm3:../common
+
+include ../../Makefile.include
+

lib/sam/3u/libopencm3_sam3u.ld

@@ -0,0 +1,106 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Generic linker script for STM32 targets using libopencm3. */
+
+/* Memory regions must be defined in the ld script which includes this one. */
+
+/* Enforce emmition of the vector table. */
+EXTERN (vector_table)
+
+/* Define the entry point of the output file. */
+ENTRY(reset_handler)
+
+/* Define sections. */
+SECTIONS
+{
+	.text : {
+		*(.vectors)	/* Vector table */
+		*(.text*)	/* Program code */
+		. = ALIGN(4);
+		*(.rodata*)	/* Read-only data */
+		. = ALIGN(4);
+	} >rom
+
+	/* C++ Static constructors/destructors, also used for __attribute__
+	 * ((constructor)) and the likes */
+	.preinit_array : {
+		. = ALIGN(4);
+		__preinit_array_start = .;
+		KEEP (*(.preinit_array))
+		__preinit_array_end = .;
+	} >rom
+	.init_array : {
+		. = ALIGN(4);
+		__init_array_start = .;
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		__init_array_end = .;
+	} >rom
+	.fini_array : {
+		. = ALIGN(4);
+		__fini_array_start = .;
+		KEEP (*(.fini_array))
+		KEEP (*(SORT(.fini_array.*)))
+		__fini_array_end = .;
+	} >rom
+
+	/*
+	 * Another section used by C++ stuff, appears when using newlib with
+	 * 64bit (long long) printf support
+	 */
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >rom
+	.ARM.exidx : {
+		__exidx_start = .;
+		*(.ARM.exidx*)
+		__exidx_end = .;
+	} >rom
+
+	. = ALIGN(4);
+	_etext = .;
+
+	.data : {
+		_data = .;
+		*(.data*)	/* Read-write initialized data */
+		. = ALIGN(4);
+		_edata = .;
+	} >ram AT >rom
+	_data_loadaddr = LOADADDR(.data);
+
+	.bss : {
+		*(.bss*)	/* Read-write zero initialized data */
+		*(COMMON)
+		. = ALIGN(4);
+		_ebss = .;
+	} >ram
+
+	/*
+	 * The .eh_frame section appears to be used for C++ exception handling.
+	 * You may need to fix this if you're using C++.
+	 */
+	/DISCARD/ : { *(.eh_frame) }
+
+	. = ALIGN(4);
+	end = .;
+}
+
+PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
+