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Add register #defines for all available USARTs/UARTs.

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This commit is contained in:
Uwe Hermann 2009-07-22 16:48:55 +02:00
parent 6db6d5b49c
commit b6a4976495
1 changed files with 56 additions and 8 deletions
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64
include/libopenstm32/usart.h
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@ -24,17 +24,65 @@
/* --- USART registers ----------------------------------------------------- */
#define USART_SR MMIO32(USART_BASE + 0x00)
#define USART_DR MMIO32(USART_BASE + 0x04)
#define USART_BRR MMIO32(USART_BASE + 0x08)
#define USART_CR1 MMIO32(USART_BASE + 0x0c)
#define USART_CR2 MMIO32(USART_BASE + 0x10)
#define USART_CR3 MMIO32(USART_BASE + 0x14)
#define USART_GTPR MMIO32(USART_BASE + 0x18)
/* Status register (USARTx_SR) */
#define USART_SR(usart) MMIO32(usart_base + 0x00)
#define USART1_SR USART_SR(USART1_BASE)
#define USART2_SR USART_SR(USART2_BASE)
#define USART3_SR USART_SR(USART3_BASE)
#define UART4_SR USART_SR(UART4_BASE)
#define UART5_SR USART_SR(UART5_BASE)
/* Data register (USARTx_DR) */
#define USART_DR(usart) MMIO32(usart_base + 0x04)
#define USART1_DR USART_DR(USART1_BASE)
#define USART2_DR USART_DR(USART2_BASE)
#define USART3_DR USART_DR(USART3_BASE)
#define UART4_DR USART_DR(UART4_BASE)
#define UART5_DR USART_DR(UART5_BASE)
/* Baud rate register (USARTx_BRR) */
#define USART_BRR(usart) MMIO32(usart_base + 0x08)
#define USART1_BRR USART_BRR(USART1_BASE)
#define USART2_BRR USART_BRR(USART2_BASE)
#define USART3_BRR USART_BRR(USART3_BASE)
#define UART4_BRR USART_BRR(UART4_BASE)
#define UART5_BRR USART_BRR(UART5_BASE)
/* Control register 1 (USARTx_CR1) */
#define USART_CR1(usart) MMIO32(usart_base + 0x0c)
#define USART1_CR1 USART_CR1(USART1_BASE)
#define USART2_CR1 USART_CR1(USART2_BASE)
#define USART3_CR1 USART_CR1(USART3_BASE)
#define UART4_CR1 USART_CR1(UART4_BASE)
#define UART5_CR1 USART_CR1(UART5_BASE)
/* Control register 2 (USARTx_CR2) */
#define USART_CR2(usart) MMIO32(usart_base + 0x10)
#define USART1_CR2 USART_CR2(USART1_BASE)
#define USART2_CR2 USART_CR2(USART2_BASE)
#define USART3_CR2 USART_CR2(USART3_BASE)
#define UART4_CR2 USART_CR2(UART4_BASE)
#define UART5_CR2 USART_CR2(UART5_BASE)
/* Control register 3 (USARTx_CR3) */
#define USART_CR3(usart) MMIO32(usart_base + 0x14)
#define USART1_CR3 USART_CR3(USART1_BASE)
#define USART2_CR3 USART_CR3(USART2_BASE)
#define USART3_CR3 USART_CR3(USART3_BASE)
#define UART4_CR3 USART_CR3(UART4_BASE)
#define UART5_CR3 USART_CR3(UART5_BASE)
/* Guard time and prescaler register (USARTx_GTPR) */
#define USART_GTPR(usart) MMIO32(usart_base + 0x18)
#define USART1_GTPR USART_GTPR(USART1_BASE)
#define USART2_GTPR USART_GTPR(USART2_BASE)
#define USART3_GTPR USART_GTPR(USART3_BASE)
#define UART4_GTPR USART_GTPR(UART4_BASE)
#define UART5_GTPR USART_GTPR(UART5_BASE)
/* --- RCC_SR values ------------------------------------------------------- */
#define SR_CTS (1 << 9)
#define SR_CTS (1 << 9) /* N/A on UART4/5 */
#define SR_LBD (1 << 8)
#define SR_TXE (1 << 7)
#define SR_TC (1 << 6)