stm32f7: flash: added proper support
This commit is contained in:
Matthew Lai
Karl Palsson
parent
ab9e425272
commit
ba0e0424b5
@ -1,19 +1,23 @@
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/** @defgroup flash_defines FLASH Defines
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*
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* @ingroup STM32F7xx_defines
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*
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* @brief Defined Constants and Types for the STM32F7xx FLASH Memory
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*
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* @version 1.0.0
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*
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* @date 14 January 2014
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*
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* LGPL License Terms @ref lgpl_license
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*/
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#ifndef LIBOPENCM3_FLASH_H
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#define LIBOPENCM3_FLASH_H
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/** @addtogroup flash_defines
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*
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* @author @htmlonly © @endhtmlonly 2017
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* Matthew Lai <m@matthewlai.ca>
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* @author @htmlonly © @endhtmlonly 2010
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* Thomas Otto <tommi@viadmin.org>
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* @author @htmlonly © @endhtmlonly 2010
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* Mark Butler <mbutler@physics.otago.ac.nz>
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*
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2017 Matthew Lai <m@matthewlai.ca>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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@ -28,10 +32,156 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_FLASH_H
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#define LIBOPENCM3_FLASH_H
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/*
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* For details see:
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* PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming
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* September 2011, Doc ID 018520 Rev 1
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* https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf
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*/
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#include <libopencm3/stm32/common/flash_common_f24.h>
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/*
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* Differences between F7 and F4:
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* 1. icache and dcache are now combined into a unified ART cache. The CPU has
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* its own d/i-caches, but those are unrelated to this. They are on the
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* AXIM bus.
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* 2. There's an OPTCR1 is now used for boot addresses. Write protect bits
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* are in OPTCR. Why does F4 have 2 copies of nWRP?
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* 3. Latency field in FLASH_ACR is now 4 bits. Some CPU frequencies supported
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* by F7 require more than 7 wait states.
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* 4. FLASH_SR_PGSERR (programming sequence error) is now FLASH_SR_ERSERR (
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* erase sequence error).
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* 5. FLASH_SR_BSY field is now read-only. Seems to also be read-only in F4?
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* Why did we have a clear busy flag function?
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* 6. There are now two watchdogs - IWDG (independent watchdog) and WWDG (
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* window watchdog).
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*/
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/**@{*/
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/* --- FLASH registers ----------------------------------------------------- */
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#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
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#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
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#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
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#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
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#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
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#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
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#define FLASH_OPTCR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
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/* --- FLASH Keys -----------------------------------------------------------*/
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#define FLASH_KEYR_KEY1 0x45670123UL
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#define FLASH_KEYR_KEY2 0xcdef89abUL
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#define FLASH_OPTKEYR_KEY1 0x08192a3bUL
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#define FLASH_OPTKEYR_KEY2 0x4c5d6e7fUL
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/* --- FLASH_ACR values ---------------------------------------------------- */
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#define FLASH_ACR_ARTRST (1 << 11)
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#define FLASH_ACR_ARTEN (1 << 9)
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#define FLASH_ACR_PRFTEN (1 << 8)
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#define FLASH_ACR_LATENCY_MASK 0x0f
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/* --- FLASH_SR values ----------------------------------------------------- */
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#define FLASH_SR_BSY (1 << 16)
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#define FLASH_SR_ERSERR (1 << 7)
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#define FLASH_SR_PGPERR (1 << 6)
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#define FLASH_SR_PGAERR (1 << 5)
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#define FLASH_SR_WRPERR (1 << 4)
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#define FLASH_SR_OPERR (1 << 1)
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#define FLASH_SR_EOP (1 << 0)
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/* --- FLASH_CR values ----------------------------------------------------- */
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#define FLASH_CR_LOCK (1 << 31)
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#define FLASH_CR_ERRIE (1 << 25)
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#define FLASH_CR_EOPIE (1 << 24)
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#define FLASH_CR_STRT (1 << 16)
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#define FLASH_CR_PROGRAM_MASK 0x3
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#define FLASH_CR_PROGRAM_SHIFT 8
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/** @defgroup flash_cr_program_width Flash programming width
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@ingroup flash_group
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@{*/
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#define FLASH_CR_PROGRAM_X8 0
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#define FLASH_CR_PROGRAM_X16 1
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#define FLASH_CR_PROGRAM_X32 2
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#define FLASH_CR_PROGRAM_X64 3
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/**@}*/
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#define FLASH_CR_SNB_SHIFT 3
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#define FLASH_CR_SNB_MASK 0x1f
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#define FLASH_CR_MER (1 << 2)
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#define FLASH_CR_SER (1 << 1)
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#define FLASH_CR_PG (1 << 0)
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/* --- FLASH_OPTCR values -------------------------------------------------- */
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#define FLASH_OPTCR_IWDG_STOP (1 << 31)
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#define FLASH_OPTCR_IWDG_STDBY (1 << 30)
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#define FLASH_OPTCR_NWRP_SHIFT 16
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#define FLASH_OPTCR_NWRP_MASK 0xff
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#define FLASH_OPTCR_RDP_SHIFT 8
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#define FLASH_OPTCR_RDP_MASK 0xff
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#define FLASH_OPTCR_NRST_STDBY (1 << 7)
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#define FLASH_OPTCR_NRST_STOP (1 << 6)
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#define FLASH_OPTCR_IWDG_SW (1 << 5)
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#define FLASH_OPTCR_WWDG_SW (1 << 4)
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#define FLASH_OPTCR_BOR_LEV_MASK 3
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#define FLASH_OPTCR_BOR_LEV_SHIFT 2
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#define FLASH_OPTCR_BOR_LEV_3 0x00
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#define FLASH_OPTCR_BOR_LEV_2 0x01
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#define FLASH_OPTCR_BOR_LEV_1 0x02
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#define FLASH_OPTCR_BOR_OFF 0x03
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#define FLASH_OPTCR_OPTSTRT (1 << 1)
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#define FLASH_OPTCR_OPTLOCK (1 << 0)
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/* --- FLASH_OPTCR1 values ------------------------------------------------- */
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#define FLASH_OPTCR1_BOOT_ADD1_MASK 0xffff
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#define FLASH_OPTCR1_BOOT_ADD1_SHIFT 16
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#define FLASH_OPTCR1_BOOT_ADD0_MASK 0xffff
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#define FLASH_OPTCR1_BOOT_ADD0_SHIFT 0
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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void flash_set_ws(uint32_t ws);
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void flash_unlock(void);
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void flash_lock(void);
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void flash_clear_pgperr_flag(void);
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void flash_clear_eop_flag(void);
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void flash_wait_for_last_operation(void);
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void flash_unlock_option_bytes(void);
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void flash_lock_option_bytes(void);
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void flash_clear_erserr_flag(void);
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void flash_clear_wrperr_flag(void);
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void flash_clear_pgaerr_flag(void);
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void flash_art_enable(void);
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void flash_art_disable(void);
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void flash_prefetch_enable(void);
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void flash_prefetch_disable(void);
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void flash_art_reset(void);
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void flash_clear_status_flags(void);
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void flash_erase_all_sectors(uint32_t program_size);
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void flash_erase_sector(uint8_t sector, uint32_t program_size);
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void flash_program_double_word(uint32_t address, uint64_t data);
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void flash_program_word(uint32_t address, uint32_t data);
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void flash_program_half_word(uint32_t address, uint16_t data);
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void flash_program_byte(uint32_t address, uint8_t data);
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void flash_program(uint32_t address, uint8_t *data, uint32_t len);
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void flash_program_option_bytes(uint32_t data);
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END_DECLS
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/**@}*/
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#endif
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@ -615,7 +615,7 @@ struct rcc_clock_scale {
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uint16_t plln;
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uint8_t pllp;
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uint8_t pllq;
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uint32_t flash_config;
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uint32_t flash_waitstates;
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uint8_t hpre;
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uint8_t ppre1;
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uint8_t ppre2;
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@ -42,9 +42,10 @@ TGT_CFLAGS += $(STANDARD_FLAGS)
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ARFLAGS = rcs
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OBJS = pwr.o rcc.o gpio.o gpio_common_all.o gpio_common_f0234.o
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OBJS = flash.o pwr.o rcc.o
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OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o
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OBJS += rcc_common_all.o flash_common_f234.o flash_common_f24.o
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OBJS += rcc_common_all.o
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OBJS += rng_common_v1.o
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479
lib/stm32/f7/flash.c
Normal file
479
lib/stm32/f7/flash.c
Normal file
@ -0,0 +1,479 @@
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/** @addtogroup flash_file
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*
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2017 Matthew Lai @m@matthewlai.ca>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/flash.h>
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/*---------------------------------------------------------------------------*/
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/** @brief Set the Program Parallelism Size
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Set the programming word width. Note carefully the power supply voltage
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restrictions under which the different word sizes may be used. See the
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programming manual for more information.
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@param[in] psize The programming word width one of: @ref flash_cr_program_width
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*/
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static inline void flash_set_program_size(uint32_t psize)
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{
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FLASH_CR &= ~(FLASH_CR_PROGRAM_MASK << FLASH_CR_PROGRAM_SHIFT);
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FLASH_CR |= psize << FLASH_CR_PROGRAM_SHIFT;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Issue Pipeline Stall
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Issue a pipeline stall to make sure all write operations completed.
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RM0385: After performing a data write operation and before polling the BSY bit
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to be cleared, the software can issue a DSB instruction to guarantee the
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completion of a previous data write operation.
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*/
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static inline void flash_pipeline_stall(void)
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{
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__asm__ volatile("dsb":::"memory");
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set the Number of Wait States
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Used to match the system clock to the FLASH memory access time. See the
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programming manual for more information on clock speed ranges. The latency must
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be changed to the appropriate value <b>before</b> any increase in clock
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speed, or <b>after</b> any decrease in clock speed.
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@param[in] ws values from @ref flash_latency.
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*/
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void flash_set_ws(uint32_t ws)
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{
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uint32_t reg32;
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reg32 = FLASH_ACR;
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reg32 &= ~(FLASH_ACR_LATENCY_MASK);
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reg32 |= ws;
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FLASH_ACR = reg32;
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/* Wait until the new wait states take effect.
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* RM0385: Check that the new number of wait states is taken into
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* account to access the Flash memory by reading the FLASH_ACR register.
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*/
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while ((FLASH_ACR & FLASH_ACR_LATENCY_MASK) != ws);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Unlock the Flash Program and Erase Controller
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This enables write access to the Flash memory. It is locked by default on
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reset.
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*/
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void flash_unlock(void)
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{
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/* Clear the unlock sequence state. */
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FLASH_CR |= FLASH_CR_LOCK;
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/* Authorize the FPEC access. */
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FLASH_KEYR = FLASH_KEYR_KEY1;
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FLASH_KEYR = FLASH_KEYR_KEY2;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Lock the Flash Program and Erase Controller
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Used to prevent spurious writes to FLASH.
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*/
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void flash_lock(void)
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{
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FLASH_CR |= FLASH_CR_LOCK;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Clear the Programming Error Status Flag
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*/
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void flash_clear_pgperr_flag(void)
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{
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FLASH_SR |= FLASH_SR_PGPERR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Clear the End of Operation Status Flag
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*/
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void flash_clear_eop_flag(void)
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{
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FLASH_SR |= FLASH_SR_EOP;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Wait until Last Operation has Ended
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This loops indefinitely until an operation (write or erase) has completed by
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testing the busy flag.
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*/
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void flash_wait_for_last_operation(void)
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{
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flash_pipeline_stall();
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while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Unlock the Option Byte Access
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This enables write access to the option bytes. It is locked by default on
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reset.
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*/
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void flash_unlock_option_bytes(void)
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{
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/* Clear the unlock state. */
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FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
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/* Unlock option bytes. */
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FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
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FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Lock the Option Byte Access
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This disables write access to the option bytes. It is locked by default on
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reset.
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*/
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void flash_lock_option_bytes(void)
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{
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FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Clear the Erase Sequence Error Flag
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This flag is set when an erase operation is performed with control register has
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not been correctly set.
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*/
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void flash_clear_erserr_flag(void)
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{
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FLASH_SR |= FLASH_SR_ERSERR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Clear the Programming Alignment Error Flag
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*/
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void flash_clear_pgaerr_flag(void)
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{
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FLASH_SR |= FLASH_SR_PGAERR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Clear the Write Protect Error Flag
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*/
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void flash_clear_wrperr_flag(void)
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{
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FLASH_SR |= FLASH_SR_WRPERR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable the ART Cache
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*/
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void flash_art_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_ARTEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable the FLASH Prefetch Buffer
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This buffer is used for instruction fetches and is enabled by default after
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reset.
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Note carefully the clock restrictions under which the prefetch buffer may be
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enabled or disabled. Changes are normally made while the clock is running in
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the power-on low frequency mode before being set to a higher speed mode.
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See the reference manual for details.
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*/
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void flash_prefetch_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_PRFTEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Disable the FLASH Prefetch Buffer
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Note carefully the clock restrictions under which the prefetch buffer may be
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set to disabled. See the reference manual for details.
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*/
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void flash_prefetch_disable(void)
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{
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FLASH_ACR &= ~FLASH_ACR_PRFTEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Reset the ART Cache
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The ART cache must be disabled for this to have effect.
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*/
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void flash_art_reset(void)
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{
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FLASH_ACR |= FLASH_ACR_ARTRST;
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}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Clear All Status Flags
|
||||
|
||||
Program error, end of operation, write protect error.
|
||||
*/
|
||||
|
||||
void flash_clear_status_flags(void)
|
||||
{
|
||||
flash_clear_erserr_flag();
|
||||
flash_clear_pgaerr_flag();
|
||||
flash_clear_wrperr_flag();
|
||||
flash_clear_pgperr_flag();
|
||||
flash_clear_eop_flag();
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Erase All FLASH
|
||||
|
||||
This performs all operations necessary to erase all sectors in the FLASH
|
||||
memory.
|
||||
|
||||
@param program_size: 0 (8-bit), 1 (16-bit), 2 (32-bit), 3 (64-bit)
|
||||
*/
|
||||
|
||||
void flash_erase_all_sectors(uint32_t program_size)
|
||||
{
|
||||
flash_wait_for_last_operation();
|
||||
flash_set_program_size(program_size);
|
||||
|
||||
FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
|
||||
FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
|
||||
|
||||
flash_wait_for_last_operation();
|
||||
FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Erase a Sector of FLASH
|
||||
|
||||
This performs all operations necessary to erase a sector in FLASH memory.
|
||||
The page should be checked to ensure that it was properly erased. A sector must
|
||||
first be fully erased before attempting to program it.
|
||||
|
||||
See the reference manual or the FLASH programming manual for details.
|
||||
|
||||
@param[in] sector (0 - 11 for some parts, 0-23 on others)
|
||||
@param program_size: 0 (8-bit), 1 (16-bit), 2 (32-bit), 3 (64-bit)
|
||||
*/
|
||||
|
||||
void flash_erase_sector(uint8_t sector, uint32_t program_size)
|
||||
{
|
||||
flash_wait_for_last_operation();
|
||||
flash_set_program_size(program_size);
|
||||
|
||||
FLASH_CR &= ~(FLASH_CR_SNB_MASK << FLASH_CR_SNB_SHIFT);
|
||||
FLASH_CR |= (sector & FLASH_CR_SNB_MASK) << FLASH_CR_SNB_SHIFT;
|
||||
FLASH_CR |= FLASH_CR_SER;
|
||||
FLASH_CR |= FLASH_CR_STRT;
|
||||
|
||||
flash_wait_for_last_operation();
|
||||
FLASH_CR &= ~FLASH_CR_SER;
|
||||
FLASH_CR &= ~(FLASH_CR_SNB_MASK << FLASH_CR_SNB_SHIFT);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Program a 64 bit Word to FLASH
|
||||
|
||||
This performs all operations necessary to program a 64 bit word to FLASH memory.
|
||||
The program error flag should be checked separately for the event that memory
|
||||
was not properly erased.
|
||||
|
||||
@param[in] address Starting address in Flash.
|
||||
@param[in] data Double word to write
|
||||
*/
|
||||
|
||||
void flash_program_double_word(uint32_t address, uint64_t data)
|
||||
{
|
||||
/* Ensure that all flash operations are complete. */
|
||||
flash_wait_for_last_operation();
|
||||
flash_set_program_size(FLASH_CR_PROGRAM_X64);
|
||||
|
||||
/* Enable writes to flash. */
|
||||
FLASH_CR |= FLASH_CR_PG;
|
||||
|
||||
/* Program the double_word. */
|
||||
MMIO64(address) = data;
|
||||
|
||||
/* Wait for the write to complete. */
|
||||
flash_wait_for_last_operation();
|
||||
|
||||
/* Disable writes to flash. */
|
||||
FLASH_CR &= ~FLASH_CR_PG;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Program a 32 bit Word to FLASH
|
||||
|
||||
This performs all operations necessary to program a 32 bit word to FLASH memory.
|
||||
The program error flag should be checked separately for the event that memory
|
||||
was not properly erased.
|
||||
|
||||
@param[in] address Starting address in Flash.
|
||||
@param[in] data word to write
|
||||
*/
|
||||
|
||||
void flash_program_word(uint32_t address, uint32_t data)
|
||||
{
|
||||
/* Ensure that all flash operations are complete. */
|
||||
flash_wait_for_last_operation();
|
||||
flash_set_program_size(FLASH_CR_PROGRAM_X32);
|
||||
|
||||
/* Enable writes to flash. */
|
||||
FLASH_CR |= FLASH_CR_PG;
|
||||
|
||||
/* Program the word. */
|
||||
MMIO32(address) = data;
|
||||
|
||||
/* Wait for the write to complete. */
|
||||
flash_wait_for_last_operation();
|
||||
|
||||
/* Disable writes to flash. */
|
||||
FLASH_CR &= ~FLASH_CR_PG;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Program a Half Word to FLASH
|
||||
|
||||
This performs all operations necessary to program a 16 bit word to FLASH memory.
|
||||
The program error flag should be checked separately for the event that memory
|
||||
was not properly erased.
|
||||
|
||||
@param[in] address Starting address in Flash.
|
||||
@param[in] data half word to write
|
||||
*/
|
||||
|
||||
void flash_program_half_word(uint32_t address, uint16_t data)
|
||||
{
|
||||
flash_wait_for_last_operation();
|
||||
flash_set_program_size(FLASH_CR_PROGRAM_X16);
|
||||
|
||||
FLASH_CR |= FLASH_CR_PG;
|
||||
|
||||
MMIO16(address) = data;
|
||||
|
||||
flash_wait_for_last_operation();
|
||||
|
||||
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Program an 8 bit Byte to FLASH
|
||||
|
||||
This performs all operations necessary to program an 8 bit byte to FLASH memory.
|
||||
The program error flag should be checked separately for the event that memory
|
||||
was not properly erased.
|
||||
|
||||
@param[in] address Starting address in Flash.
|
||||
@param[in] data byte to write
|
||||
*/
|
||||
|
||||
void flash_program_byte(uint32_t address, uint8_t data)
|
||||
{
|
||||
flash_wait_for_last_operation();
|
||||
flash_set_program_size(FLASH_CR_PROGRAM_X8);
|
||||
|
||||
FLASH_CR |= FLASH_CR_PG;
|
||||
|
||||
MMIO8(address) = data;
|
||||
|
||||
flash_wait_for_last_operation();
|
||||
|
||||
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Program a Data Block to FLASH
|
||||
|
||||
This programs an arbitrary length data block to FLASH memory. All the addresses
|
||||
written to must have been erased (by calling flash_erase_sector).
|
||||
The program error flag should be checked separately for the event that memory
|
||||
was not properly erased.
|
||||
|
||||
@param[in] address Starting address in Flash.
|
||||
@param[in] data Pointer to start of data block.
|
||||
@param[in] len Length of data block.
|
||||
*/
|
||||
|
||||
void flash_program(uint32_t address, uint8_t *data, uint32_t len)
|
||||
{
|
||||
/* TODO: Use dword and word size program operations where possible for
|
||||
* turbo speed.
|
||||
*/
|
||||
uint32_t i;
|
||||
for (i = 0; i < len; i++) {
|
||||
flash_program_byte(address+i, data[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Program the Option Bytes
|
||||
|
||||
This performs all operations necessary to program the option bytes.
|
||||
The option bytes do not need to be erased first.
|
||||
|
||||
@param[in] data value to be programmed.
|
||||
*/
|
||||
|
||||
void flash_program_option_bytes(uint32_t data)
|
||||
{
|
||||
flash_wait_for_last_operation();
|
||||
|
||||
if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK) {
|
||||
flash_unlock_option_bytes();
|
||||
}
|
||||
|
||||
FLASH_OPTCR = data & ~0x3;
|
||||
FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte prog. */
|
||||
flash_wait_for_last_operation();
|
||||
}
|
||||
/**@}*/
|
||||
@ -13,13 +13,12 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
|
||||
.plln = 432,
|
||||
.pllp = 2,
|
||||
.pllq = 9,
|
||||
.flash_config = FLASH_ACR_ICEN | FLASH_ACR_DCEN |
|
||||
FLASH_ACR_LATENCY_7WS,
|
||||
.hpre = RCC_CFGR_HPRE_DIV_NONE,
|
||||
.ppre1 = RCC_CFGR_PPRE_DIV_4,
|
||||
.ppre2 = RCC_CFGR_PPRE_DIV_2,
|
||||
.vos_scale = PWR_SCALE1,
|
||||
.overdrive = 1,
|
||||
.flash_waitstates = 7,
|
||||
.apb1_frequency = 108000000,
|
||||
.apb2_frequency = 216000000,
|
||||
},
|
||||
@ -328,7 +327,9 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
|
||||
rcc_wait_for_osc_ready(RCC_PLL);
|
||||
|
||||
/* Configure flash settings. */
|
||||
flash_set_ws(clock->flash_config);
|
||||
flash_set_ws(clock->flash_waitstates);
|
||||
flash_art_enable();
|
||||
flash_prefetch_enable();
|
||||
|
||||
/* Select PLL as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user