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stm32l0: rcc: Add clock struct setup helper

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Based on l1, l4 and friends.
This commit is contained in:
Karl Palsson 2017-05-01 23:17:31 +00:00
parent f594ddb395
commit bc898d1f92
2 changed files with 67 additions and 1 deletions
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20
include/libopencm3/stm32/l0/rcc.h
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@ -40,6 +40,9 @@
#ifndef LIBOPENCM3_RCC_H #ifndef LIBOPENCM3_RCC_H
#define LIBOPENCM3_RCC_H #define LIBOPENCM3_RCC_H
#include <stdbool.h>
#include <stdint.h>
#include <libopencm3/stm32/pwr.h>
/* --- RCC registers ------------------------------------------------------- */ /* --- RCC registers ------------------------------------------------------- */
@ -496,6 +499,21 @@
#define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0) #define RCC_CSR_LSION (1 << 0)
struct rcc_clock_scale {
uint8_t pll_mul;
uint16_t pll_div;
uint8_t pll_source;
uint8_t flash_waitstates;
enum pwr_vos_scale voltage_scale;
uint8_t hpre;
uint8_t ppre1;
uint8_t ppre2;
// FIXME enum pwr_vos_scale voltage_scale;
uint32_t ahb_frequency;
uint32_t apb1_frequency;
uint32_t apb2_frequency;
uint8_t msi_range;
};
/* --- Variable definitions ------------------------------------------------ */ /* --- Variable definitions ------------------------------------------------ */
extern uint32_t rcc_ahb_frequency; extern uint32_t rcc_ahb_frequency;
@ -672,7 +690,7 @@ void rcc_set_pll_divider(uint32_t factor);
void rcc_set_ppre2(uint32_t ppre2); void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1); void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre); void rcc_set_hpre(uint32_t hpre);
/* TODO */ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock);
END_DECLS END_DECLS

48
lib/stm32/l0/rcc.c
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@ -35,8 +35,15 @@
/**@{*/ /**@{*/
#include <libopencm3/cm3/assert.h> #include <libopencm3/cm3/assert.h>
#include <libopencm3/stm32/flash.h>
#include <libopencm3/stm32/pwr.h>
#include <libopencm3/stm32/rcc.h> #include <libopencm3/stm32/rcc.h>
/* Set the default clock frequencies after reset. */
uint32_t rcc_ahb_frequency = 2097000;
uint32_t rcc_apb1_frequency = 2097000;
uint32_t rcc_apb2_frequency = 2097000;
void rcc_osc_on(enum rcc_osc osc) void rcc_osc_on(enum rcc_osc osc)
{ {
switch (osc) { switch (osc) {
@ -371,5 +378,46 @@ void rcc_set_hpre(uint32_t hpre)
RCC_CFGR = reg | (hpre << RCC_CFGR_HPRE_SHIFT); RCC_CFGR = reg | (hpre << RCC_CFGR_HPRE_SHIFT);
} }
/**
* Set up sysclock with PLL from HSI16
* @param clock full struct with desired parameters
*/
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
/* Turn on the appropriate source for the PLL */
if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
} else {
rcc_osc_on(RCC_HSI16);
rcc_wait_for_osc_ready(RCC_HSI16);
}
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
rcc_periph_clock_enable(RCC_PWR);
pwr_set_vos_scale(clock->voltage_scale);
rcc_osc_off(RCC_PLL);
while (rcc_is_osc_ready(RCC_PLL));
flash_prefetch_enable();
flash_set_ws(clock->flash_waitstates);
/* Set up the PLL */
rcc_set_pll_multiplier(clock->pll_mul);
rcc_set_pll_divider(clock->pll_div);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
rcc_set_sysclk_source(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
}
/**@}*/ /**@}*/