diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h
index a59c4202..05a4d168 100644
--- a/include/libopencm3/stm32/i2c.h
+++ b/include/libopencm3/stm32/i2c.h
@@ -322,7 +322,8 @@ LGPL License Terms @ref lgpl_license
 
 /* DUTY: Fast Mode Duty Cycle */
 #define I2C_CCR_DUTY			(1 << 14)
-
+#define I2C_CCR_DUTY_DIV2		0
+#define I2C_CCR_DUTY_16_DIV_9		1
 /* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
 
 /*
@@ -359,6 +360,7 @@ void i2c_peripheral_enable(u32 i2c);
 void i2c_peripheral_disable(u32 i2c);
 void i2c_send_start(u32 i2c);
 void i2c_send_stop(u32 i2c);
+void i2c_clear_stop(u32 i2c);
 void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
 void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
 void i2c_set_fast_mode(u32 i2c);
@@ -368,6 +370,18 @@ void i2c_set_ccr(u32 i2c, u16 freq);
 void i2c_set_trise(u32 i2c, u16 trise);
 void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
 void i2c_send_data(u32 i2c, u8 data);
+uint8_t i2c_get_data(u32 i2c);
+void i2c_enable_interrupt(u32 i2c, u32 interrupt);
+void i2c_disable_interrupt(u32 i2c, u32 interrupt);
+void i2c_enable_ack(u32 i2c);
+void i2c_disable_ack(u32 i2c);
+void i2c_nack_next(u32 i2c);
+void i2c_nack_current(u32 i2c);
+void i2c_set_dutycycle(u32 i2c, u32 dutycycle);
+void i2c_enable_dma(u32 i2c);
+void i2c_disable_dma(u32 i2c);
+void i2c_set_dma_last_transfer(u32 i2c);
+void i2c_clear_dma_last_transfer(u32 i2c);
 
 END_DECLS
 
diff --git a/lib/stm32/i2c.c b/lib/stm32/i2c.c
index e1d3a095..e1e62533 100644
--- a/lib/stm32/i2c.c
+++ b/lib/stm32/i2c.c
@@ -124,6 +124,18 @@ void i2c_send_stop(u32 i2c)
 	I2C_CR1(i2c) |= I2C_CR1_STOP;
 }
 
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Clear Stop Flag.
+
+Clear the "Send Stop" flag in the I2C config register
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+*/
+void i2c_clear_stop(u32 i2c)
+{
+	I2C_CR1(i2c) &= ~I2C_CR1_STOP;
+}
+
 /*-----------------------------------------------------------------------------*/
 /** @brief I2C Set the 7 bit Slave Address for the Peripheral.
 
@@ -269,5 +281,84 @@ void i2c_send_data(u32 i2c, u8 data)
 	I2C_DR(i2c) = data;
 }
 
-/**@}*/
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Get Data.
 
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+*/
+uint8_t i2c_get_data(u32 i2c)
+{
+	return (I2C_DR(i2c) & 0xff);
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Enable Interrupt
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+@param[in] interrupt Unsigned int32. Interrupt to enable.
+*/
+void i2c_enable_interrupt(u32 i2c, u32 interrupt)
+{
+	I2C_CR2(i2c) |= interrupt;
+}
+
+/*-----------------------------------------------------------------------------*/
+/** @brief I2C Disable Interrupt
+
+@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+@param[in] interrupt Unsigned int32. Interrupt to disable.
+*/
+void i2c_disable_interrupt(u32 i2c, u32 interrupt)
+{
+	I2C_CR2(i2c) &= ~interrupt;
+}
+
+void i2c_enable_ack(u32 i2c)
+{
+	I2C_CR1(i2c) |= I2C_CR1_ACK;
+}
+
+void i2c_disable_ack(u32 i2c)
+{
+	I2C_CR1(i2c) &= ~I2C_CR1_ACK;
+}
+
+void i2c_nack_next(u32 i2c)
+{
+	I2C_CR1(i2c) |= I2C_CR1_POS;
+}
+
+void i2c_nack_current(u32 i2c)
+{
+	I2C_CR1(i2c) &= ~I2C_CR1_POS;
+}
+
+void i2c_set_dutycycle(u32 i2c, u32 dutycycle)
+{
+	if (dutycycle == I2C_CCR_DUTY_DIV2)
+		I2C_CCR(i2c) &= ~I2C_CCR_DUTY;
+	else
+		I2C_CCR(i2c) |= I2C_CCR_DUTY;
+}
+
+void i2c_enable_dma(u32 i2c)
+{
+	I2C_CR2(i2c) |= I2C_CR2_DMAEN;
+}
+
+void i2c_disable_dma(u32 i2c)
+{
+	I2C_CR2(i2c) &= ~I2C_CR2_DMAEN;
+}
+
+void i2c_set_dma_last_transfer(u32 i2c)
+{
+	I2C_CR2(i2c) |= I2C_CR2_LAST;
+}
+
+void i2c_clear_dma_last_transfer(u32 i2c)
+{
+	I2C_CR2(i2c) &= ~I2C_CR2_LAST;
+}
+
+/**@}*/