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Some random cosmetic changes and additional comments.

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This commit is contained in:
Uwe Hermann 2009-07-25 02:35:46 +02:00
parent 5ba3aae7d7
commit c26541c4c5
3 changed files with 60 additions and 28 deletions
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76
include/libopenstm32/gpio.h
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@ -22,6 +22,8 @@
#include <libopenstm32.h> #include <libopenstm32.h>
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */ /* GPIO port base addresses (for convenience) */
#define GPIOA GPIO_PORT_A_BASE #define GPIOA GPIO_PORT_A_BASE
#define GPIOB GPIO_PORT_B_BASE #define GPIOB GPIO_PORT_B_BASE
@ -31,6 +33,27 @@
#define GPIOF GPIO_PORT_F_BASE #define GPIOF GPIO_PORT_F_BASE
#define GPIOG GPIO_PORT_G_BASE #define GPIOG GPIO_PORT_G_BASE
/* GPIO number definitions (for convenience) */
#define GPIO0 (1 << 0)
#define GPIO1 (1 << 1)
#define GPIO2 (1 << 2)
#define GPIO3 (1 << 3)
#define GPIO4 (1 << 4)
#define GPIO5 (1 << 5)
#define GPIO6 (1 << 6)
#define GPIO7 (1 << 7)
#define GPIO8 (1 << 8)
#define GPIO9 (1 << 9)
#define GPIO10 (1 << 10)
#define GPIO11 (1 << 11)
#define GPIO12 (1 << 12)
#define GPIO13 (1 << 13)
#define GPIO14 (1 << 14)
#define GPIO15 (1 << 15)
#define GPIO_ALL 0xffff
/* --- GPIO registers ------------------------------------------------------ */
/* Port configuration register low (GPIOx_CRL) */ /* Port configuration register low (GPIOx_CRL) */
#define GPIO_CRL(port) MMIO32(port + 0x00) #define GPIO_CRL(port) MMIO32(port + 0x00)
#define GPIOA_CRL GPIO_CRL(GPIOA) #define GPIOA_CRL GPIO_CRL(GPIOA)
@ -101,41 +124,48 @@
#define GPIOF_LCKR GPIO_LCKR(GPIOF) #define GPIOF_LCKR GPIO_LCKR(GPIOF)
#define GPIOG_LCKR GPIO_LCKR(GPIOG) #define GPIOG_LCKR GPIO_LCKR(GPIOG)
/* Output mode (MODE[1:0]) values */ /* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
#define GPIO_MODE_INPUT 0x00 /* Default */
#define GPIO_MODE_OUTPUT_10_MHZ 0x01
#define GPIO_MODE_OUTPUT_2_MHZ 0x02
#define GPIO_MODE_OUTPUT_50_MHZ 0x03
/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */ /* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
#define GPIO_CNF_INPUT_ANALOG 0x00 #define GPIO_CNF_INPUT_ANALOG 0x00
#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */ #define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */
#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02 #define GPIO_CNF_INPUT_PULL_UPDOWN 0x02
/* Output mode (MODE[1:0]) values */
#define GPIO_MODE_INPUT 0x00 /* Default */
#define GPIO_MODE_OUTPUT_10_MHZ 0x01
#define GPIO_MODE_OUTPUT_2_MHZ 0x02
#define GPIO_MODE_OUTPUT_50_MHZ 0x03
/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */ /* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
#define GPIO_CNF_OUTPUT_PUSHPULL 0x00 #define GPIO_CNF_OUTPUT_PUSHPULL 0x00
#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01 #define GPIO_CNF_OUTPUT_OPENDRAIN 0x01
#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02 #define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02
#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03 #define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03
/* GPIO number definitions (just for convenience) */ /* --- GPIO_IDR values ----------------------------------------------------- */
#define GPIO0 (1 << 0)
#define GPIO1 (1 << 1) /* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */
#define GPIO2 (1 << 2)
#define GPIO3 (1 << 3) /* --- GPIO_ODR values ----------------------------------------------------- */
#define GPIO4 (1 << 4)
#define GPIO5 (1 << 5) /* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */
#define GPIO6 (1 << 6)
#define GPIO7 (1 << 7) /* --- GPIO_BSRR values ---------------------------------------------------- */
#define GPIO8 (1 << 8)
#define GPIO9 (1 << 9) /* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */
#define GPIO10 (1 << 10) /* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */
#define GPIO11 (1 << 11)
#define GPIO12 (1 << 12) /* --- GPIO_BRR values ----------------------------------------------------- */
#define GPIO13 (1 << 13)
#define GPIO14 (1 << 14) /* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */
#define GPIO15 (1 << 15)
#define GPIO_ALL 0xffff /* --- GPIO_LCKR values ---------------------------------------------------- */
#define GPIO_LCKK (1 << 16)
/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */
/* --- Function prototypes ------------------------------------------------- */
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios); void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
void gpio_set(u32 gpioport, u16 gpios); void gpio_set(u32 gpioport, u16 gpios);

2
include/libopenstm32/rcc.h
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@ -359,6 +359,8 @@
#define PREDIV2_DIV15 0xe #define PREDIV2_DIV15 0xe
#define PREDIV2_DIV16 0xf #define PREDIV2_DIV16 0xf
/* --- Function prototypes ------------------------------------------------- */
typedef enum { typedef enum {
PLL, HSE, HSI, LSE, LSI PLL, HSE, HSI, LSE, LSI
} osc_t; } osc_t;

10
include/libopenstm32/usart.h
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@ -24,11 +24,11 @@
/* --- Convenience macros -------------------------------------------------- */ /* --- Convenience macros -------------------------------------------------- */
#define USART1 USART1_BASE #define USART1 USART1_BASE
#define USART2 USART2_BASE #define USART2 USART2_BASE
#define USART3 USART3_BASE #define USART3 USART3_BASE
#define UART4 UART4_BASE #define UART4 UART4_BASE
#define UART5 UART5_BASE #define UART5 UART5_BASE
/* --- USART registers ----------------------------------------------------- */ /* --- USART registers ----------------------------------------------------- */