stm32f7: rcc: initial clock config for disco board
Add clock config for the 25MHz crystal found on the discovery board. Verified to work on the STM32F7-Disco. Reviewed-by: Karl Palsson <karlp@tweak.net.au> Modified namespaces and types->structs to avoid namespace pollution as was fixed for other families in: 3a7cbec7: stm32l/stm32f: name space standardization [BREAKING]
This commit is contained in:
Sync
Karl Palsson
parent
3fc0c9d001
commit
c285bcb493
37
include/libopencm3/stm32/f7/flash.h
Normal file
37
include/libopencm3/stm32/f7/flash.h
Normal file
@ -0,0 +1,37 @@
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/** @defgroup flash_defines FLASH Defines
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*
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* @ingroup STM32F7xx_defines
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*
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* @brief Defined Constants and Types for the STM32F7xx FLASH Memory
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*
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* @version 1.0.0
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*
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* @date 14 January 2014
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_FLASH_H
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#define LIBOPENCM3_FLASH_H
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#include <libopencm3/stm32/common/flash_common_f24.h>
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#endif
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@ -595,6 +595,39 @@
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#define RCC_DCKCFGR2_UART1SEL_MASK 0x3
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#define RCC_DCKCFGR2_UART1SEL_SHIFT 0
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extern uint32_t rcc_ahb_frequency;
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extern uint32_t rcc_apb1_frequency;
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extern uint32_t rcc_apb2_frequency;
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enum rcc_clock_3v3 {
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RCC_CLOCK_3V3_216MHZ,
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RCC_CLOCK_3V3_END
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};
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struct rcc_clock_scale {
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uint8_t pllm;
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uint16_t plln;
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uint8_t pllp;
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uint8_t pllq;
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uint32_t flash_config;
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uint8_t hpre;
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uint8_t ppre1;
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uint8_t ppre2;
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uint8_t power_save;
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uint32_t apb1_frequency;
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uint32_t apb2_frequency;
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};
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extern const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END];
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enum rcc_osc {
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RCC_PLL,
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RCC_HSE,
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RCC_HSI,
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RCC_LSE,
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RCC_LSI
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};
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#define _REG_BIT(base, bit) (((base) << 5) + (bit))
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enum rcc_periph_clken {
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@ -870,7 +903,31 @@ enum rcc_periph_rst {
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#include <libopencm3/stm32/common/rcc_common_all.h>
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BEGIN_DECLS
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void rcc_osc_ready_int_clear(enum rcc_osc osc);
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void rcc_osc_ready_int_enable(enum rcc_osc osc);
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void rcc_osc_ready_int_disable(enum rcc_osc osc);
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int rcc_osc_ready_int_flag(enum rcc_osc osc);
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void rcc_css_int_clear(void);
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int rcc_css_int_flag(void);
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void rcc_wait_for_sysclk_status(enum rcc_osc osc);
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void rcc_osc_on(enum rcc_osc osc);
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void rcc_osc_off(enum rcc_osc osc);
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void rcc_css_enable(void);
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void rcc_css_disable(void);
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void rcc_osc_bypass_enable(enum rcc_osc osc);
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void rcc_osc_bypass_disable(enum rcc_osc osc);
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void rcc_set_sysclk_source(uint32_t clk);
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void rcc_set_pll_source(uint32_t pllsrc);
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void rcc_set_ppre2(uint32_t ppre2);
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void rcc_set_ppre1(uint32_t ppre1);
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void rcc_set_hpre(uint32_t hpre);
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void rcc_set_rtcpre(uint32_t rtcpre);
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void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
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uint32_t pllq);
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void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
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uint32_t pllq);
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uint32_t rcc_system_clock_source(void);
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void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock);
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END_DECLS
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#endif
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@ -30,6 +30,8 @@
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# include <libopencm3/stm32/f3/flash.h>
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#elif defined(STM32F4)
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# include <libopencm3/stm32/f4/flash.h>
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#elif defined(STM32F7)
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# include <libopencm3/stm32/f7/flash.h>
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#elif defined(STM32L1)
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# include <libopencm3/stm32/l1/flash.h>
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#elif defined(STM32L4)
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@ -42,7 +42,7 @@ ARFLAGS = rcs
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OBJS = rcc.o gpio.o gpio_common_all.o gpio_common_f0234.o
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OBJS += rcc_common_all.o
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OBJS += rcc_common_all.o flash_common_f234.o flash_common_f24.o
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OBJS += rng_common_v1.o
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@ -1,11 +1,378 @@
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/flash.h>
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uint32_t rcc_ahb_frequency = 16000000;
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uint32_t rcc_apb1_frequency = 16000000;
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uint32_t rcc_apb2_frequency = 16000000;
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const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
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{ /* 216MHz */
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.pllm = 25,
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.plln = 432,
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.pllp = 2,
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.pllq = 9,
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.hpre = RCC_CFGR_HPRE_DIV_NONE,
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.ppre1 = RCC_CFGR_PPRE_DIV_4,
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.ppre2 = RCC_CFGR_PPRE_DIV_2,
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.flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE |
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FLASH_ACR_LATENCY_7WS,
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.apb1_frequency = 108000000,
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.apb2_frequency = 216000000,
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},
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};
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case RCC_HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case RCC_HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case RCC_LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case RCC_LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case RCC_HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case RCC_HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case RCC_HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case RCC_HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case RCC_LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case RCC_LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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cm3_assert_not_reached();
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case RCC_HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case RCC_HSI:
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
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break;
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case RCC_LSE:
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while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
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break;
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case RCC_LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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}
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}
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void rcc_wait_for_sysclk_status(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
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break;
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case RCC_HSE:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
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break;
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case RCC_HSI:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_osc_bypass_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case RCC_LSE:
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RCC_BDCR |= RCC_BDCR_LSEBYP;
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break;
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case RCC_PLL:
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case RCC_HSI:
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case RCC_LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_osc_bypass_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case RCC_LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEBYP;
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break;
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case RCC_PLL:
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case RCC_HSI:
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case RCC_LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_set_sysclk_source(uint32_t clk)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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RCC_CFGR = (reg32 | clk);
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}
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void rcc_set_pll_source(uint32_t pllsrc)
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{
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uint32_t reg32;
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reg32 = RCC_PLLCFGR;
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reg32 &= ~(1 << 22);
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RCC_PLLCFGR = (reg32 | (pllsrc << 22));
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}
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void rcc_set_ppre2(uint32_t ppre2)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
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RCC_CFGR = (reg32 | (ppre2 << 13));
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}
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void rcc_set_ppre1(uint32_t ppre1)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
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RCC_CFGR = (reg32 | (ppre1 << 10));
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}
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
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RCC_CFGR = (reg32 | (hpre << 4));
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}
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void rcc_set_rtcpre(uint32_t rtcpre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
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RCC_CFGR = (reg32 | (rtcpre << 16));
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}
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void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
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uint32_t pllq)
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{
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RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
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(plln << RCC_PLLCFGR_PLLN_SHIFT) |
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(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
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(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
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}
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void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
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uint32_t pllq)
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{
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RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
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(plln << RCC_PLLCFGR_PLLN_SHIFT) |
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(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
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RCC_PLLCFGR_PLLSRC |
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(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
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}
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uint32_t rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return (RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK;
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}
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void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(RCC_HSI);
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rcc_wait_for_osc_ready(RCC_HSI);
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/* Select HSI as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
|
||||
|
||||
/* Enable external high-speed oscillator 8MHz. */
|
||||
rcc_osc_on(RCC_HSE);
|
||||
rcc_wait_for_osc_ready(RCC_HSE);
|
||||
|
||||
/* Enable/disable high performance mode */
|
||||
/* if (!clock->power_save) {
|
||||
pwr_set_vos_scale(SCALE1);
|
||||
} else {
|
||||
pwr_set_vos_scale(SCALE2);
|
||||
}
|
||||
*/
|
||||
/*
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(clock->hpre);
|
||||
rcc_set_ppre1(clock->ppre1);
|
||||
rcc_set_ppre2(clock->ppre2);
|
||||
|
||||
rcc_set_main_pll_hse(clock->pllm, clock->plln,
|
||||
clock->pllp, clock->pllq);
|
||||
|
||||
/* Enable PLL oscillator and wait for it to stabilize. */
|
||||
rcc_osc_on(RCC_PLL);
|
||||
rcc_wait_for_osc_ready(RCC_PLL);
|
||||
|
||||
/* Configure flash settings. */
|
||||
flash_set_ws(clock->flash_config);
|
||||
|
||||
/* Select PLL as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
|
||||
|
||||
/* Wait for PLL clock to be selected. */
|
||||
rcc_wait_for_sysclk_status(RCC_PLL);
|
||||
|
||||
/* Set the peripheral clock frequencies used. */
|
||||
rcc_apb1_frequency = clock->apb1_frequency;
|
||||
rcc_apb2_frequency = clock->apb2_frequency;
|
||||
|
||||
/* Disable internal high-speed oscillator. */
|
||||
rcc_osc_off(RCC_HSI);
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user