From c2c2ac766bdc615ee1b1658af739e0b06614d8f3 Mon Sep 17 00:00:00 2001
From: Frantisek Burian <BuFran@seznam.cz>
Date: Thu, 6 Feb 2014 13:37:22 +0100
Subject: [PATCH] [eth/phy] Updated style

---
 include/libopencm3/ethernet/mac_stm32fxx7.h | 21 ++++++-
 include/libopencm3/ethernet/phy.h           | 62 +++++++++++++--------
 2 files changed, 59 insertions(+), 24 deletions(-)

diff --git a/include/libopencm3/ethernet/mac_stm32fxx7.h b/include/libopencm3/ethernet/mac_stm32fxx7.h
index 40bd87c8..bac5e72f 100644
--- a/include/libopencm3/ethernet/mac_stm32fxx7.h
+++ b/include/libopencm3/ethernet/mac_stm32fxx7.h
@@ -38,9 +38,16 @@
 #include <libopencm3/stm32/memorymap.h>
 #include <libopencm3/cm3/common.h>
 
+/*****************************************************************************/
+/* Module definitions                                                        */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* Register definitions                                                      */
+/*****************************************************************************/
+
 /**@{*/
 
-/* Ethernet MAC registers */
 #define ETH_MACCR			MMIO32(ETHERNET_BASE + 0x00)
 #define ETH_MACFFR			MMIO32(ETHERNET_BASE + 0x04)
 #define ETH_MACHTHR			MMIO32(ETHERNET_BASE + 0x08)
@@ -115,6 +122,10 @@
 #define	ETH_DES6(base)			ETH_DES(6, base)
 #define	ETH_DES7(base)			ETH_DES(7, base)
 
+/*****************************************************************************/
+/* Register values                                                           */
+/*****************************************************************************/
+
 /*---------------------------------------------------------------------------*/
 /* MACCR --------------------------------------------------------------------*/
 
@@ -697,6 +708,10 @@
 #define ETH_RDES4_PFT			(1<<12)
 #define ETH_RDES4_PV			(1<<13)
 
+/*****************************************************************************/
+/* API definitions                                                           */
+/*****************************************************************************/
+
 enum eth_clk {
 	ETH_CLK_025_035MHZ = ETH_MACMIIAR_CR_HCLK_DIV_16,
 	ETH_CLK_035_060MHZ = ETH_MACMIIAR_CR_HCLK_DIV_26,
@@ -705,6 +720,10 @@ enum eth_clk {
 	ETH_CLK_150_168MHZ = ETH_MACMIIAR_CR_HCLK_DIV_102,
 };
 
+/*****************************************************************************/
+/* API Functions                                                             */
+/*****************************************************************************/
+
 BEGIN_DECLS
 
 void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data);
diff --git a/include/libopencm3/ethernet/phy.h b/include/libopencm3/ethernet/phy.h
index 0dc9c51d..11ab185b 100755
--- a/include/libopencm3/ethernet/phy.h
+++ b/include/libopencm3/ethernet/phy.h
@@ -37,32 +37,44 @@
 
 /**@{*/
 
-/* Registers */
+/*****************************************************************************/
+/* Register definitions                                                      */
+/*****************************************************************************/
 
-#define PHY_REG_BCR         0x00
-#define PHY_REG_BSR         0x01
-#define PHY_REG_ID1         0x02
-#define PHY_REG_ID2         0x03
-#define PHY_REG_ANTX        0x04
-#define PHY_REG_ANRX        0x05
-#define PHY_REG_ANEXP       0x06
-#define PHY_REG_ANNPTX      0x07
-#define PHY_REG_ANNPRX      0x08
+#define PHY_REG_BCR			0x00
+#define PHY_REG_BSR			0x01
+#define PHY_REG_ID1			0x02
+#define PHY_REG_ID2			0x03
+#define PHY_REG_ANTX			0x04
+#define PHY_REG_ANRX			0x05
+#define PHY_REG_ANEXP			0x06
+#define PHY_REG_ANNPTX			0x07
+#define PHY_REG_ANNPRX			0x08
 
-#define PHY_REG_BCR_COLTEST     (1<<7)
-#define PHY_REG_BCR_FD          (1<<8)
-#define PHY_REG_BCR_ANRST       (1<<9)
-#define PHY_REG_BCR_ISOLATE     (1<<10)
-#define PHY_REG_BCR_POWERDN     (1<<11)
-#define PHY_REG_BCR_AN          (1<<12)
-#define PHY_REG_BCR_100M        (1<<13)
-#define PHY_REG_BCR_LOOPBACK    (1<<14)
-#define PHY_REG_BCR_RESET       (1<<15)
+/*****************************************************************************/
+/* Register values                                                           */
+/*****************************************************************************/
 
-#define PHY_REG_BSR_JABBER      (1<<1)
-#define PHY_REG_BSR_UP          (1<<2)
-#define PHY_REG_BSR_FAULT       (1<<4)
-#define PHY_REG_BSR_ANDONE      (1<<5)
+#define PHY_REG_BCR_COLTEST		(1 << 7)
+#define PHY_REG_BCR_FD			(1 << 8)
+#define PHY_REG_BCR_ANRST		(1 << 9)
+#define PHY_REG_BCR_ISOLATE		(1 << 10)
+#define PHY_REG_BCR_POWERDN		(1 << 11)
+#define PHY_REG_BCR_AN			(1 << 12)
+#define PHY_REG_BCR_100M		(1 << 13)
+#define PHY_REG_BCR_LOOPBACK		(1 << 14)
+#define PHY_REG_BCR_RESET		(1 << 15)
+
+#define PHY_REG_BSR_JABBER		(1 << 1)
+#define PHY_REG_BSR_UP			(1 << 2)
+#define PHY_REG_BSR_FAULT		(1 << 4)
+#define PHY_REG_BSR_ANDONE		(1 << 5)
+
+
+
+/*****************************************************************************/
+/* API definitions                                                           */
+/*****************************************************************************/
 
 #define PHY0 0
 #define PHY1 1
@@ -79,6 +91,10 @@ enum phy_status {
 	LINK_FD_10000M,
 };
 
+/*****************************************************************************/
+/* API Functions                                                             */
+/*****************************************************************************/
+
 BEGIN_DECLS
 
 void phy_reset(uint8_t phy);