From c49f505df4205e166a184de8063eb1702813cf46 Mon Sep 17 00:00:00 2001
From: Piotr Esden-Tempski <piotr@esden.net>
Date: Tue, 28 Feb 2012 11:28:29 -0800
Subject: [PATCH] Added spi reset convenience function.

---
 include/libopencm3/stm32/spi.h |  1 +
 lib/stm32/spi.c                | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+)

diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h
index e44127c5..8dc1622e 100644
--- a/include/libopencm3/stm32/spi.h
+++ b/include/libopencm3/stm32/spi.h
@@ -297,6 +297,7 @@
 
 /* --- Function prototypes ------------------------------------------------- */
 
+void spi_reset(u32 spi_peripheral);
 int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
 void spi_enable(u32 spi);
 void spi_disable(u32 spi);
diff --git a/lib/stm32/spi.c b/lib/stm32/spi.c
index 87392c06..c97837c2 100644
--- a/lib/stm32/spi.c
+++ b/lib/stm32/spi.c
@@ -32,6 +32,24 @@
  *  reg16 = spi_read(SPI1);		// 16-bit read
  */
 
+void spi_reset(u32 spi_peripheral)
+{
+	switch (spi_peripheral) {
+	case SPI1:
+		rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST);
+		rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_SPI1RST);
+		break;
+	case SPI2:
+		rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB2RSTR_SPI2RST);
+		rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB2RSTR_SPI2RST);
+		break;
+	case SPI3:
+		rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB2RSTR_SPI3RST);
+		rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB2RSTR_SPI3RST);
+		break;
+	}
+}
+
 int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst)
 {
 	u32 reg32 = 0;