style: fix some of the easier style bugs

No real changes.

include/libopencm3/lm3s/usart.h

@@ -82,27 +82,27 @@
 /* Bits [3:0] - Reserved */
 
 enum usart_stopbits {
-    USART_STOPBITS_1,
+	USART_STOPBITS_1,
-    USART_STOPBITS_1_5,
+	USART_STOPBITS_1_5,
-    USART_STOPBITS_2,
+	USART_STOPBITS_2,
 };
 
 enum usart_parity {
-    USART_PARITY_NONE,
+	USART_PARITY_NONE,
-    USART_PARITY_ODD,
+	USART_PARITY_ODD,
-    USART_PARITY_EVEN,
+	USART_PARITY_EVEN,
 };
 
 enum usart_mode {
-    USART_MODE_DISABLED,
+	USART_MODE_DISABLED,
-    USART_MODE_RX,
+	USART_MODE_RX,
-    USART_MODE_TX,
+	USART_MODE_TX,
-    USART_MODE_TX_RX,
+	USART_MODE_TX_RX,
 };
 
 enum usart_flowcontrol {
-    USART_FLOWCONTROL_NONE,
+	USART_FLOWCONTROL_NONE,
-    USART_FLOWCONTROL_RTS_CTS,
+	USART_FLOWCONTROL_RTS_CTS,
 };
 
 void usart_send(uint32_t usart, uint16_t data);

include/libopencm3/sam/d/port.h

@@ -23,8 +23,8 @@
 
 /* --- Convenience macros ------------------------------------------------ */
 
-#define PORTA				PORT_BASE + 0
+#define PORTA				(PORT_BASE + 0)
-#define PORTB				PORT_BASE + 0x80
+#define PORTB				(PORT_BASE + 0x80)
 
 /* --- PORT registers ----------------------------------------------------- */
 

include/libopencm3/stm32/common/adc_common_v2_multi.h

@@ -37,7 +37,7 @@ specific memorymap.h header before including this header file.*/
 
 /*
  * The adc v2 peripheral optionally supports per channel sampling, injected
- * sequences, watchdogs, offsets and other "advanced" features, and is 
+ * sequences, watchdogs, offsets and other "advanced" features, and is
  * found on the (so far) F3 and L4,
  * or only a much "simpler" version as found on (so far) f0 and l0.
  */

include/libopencm3/stm32/common/adc_common_v2_single.h

@@ -31,10 +31,10 @@ specific memorymap.h header before including this header file.*/
 
 /*
  * The adc v2 peripheral optionally supports per channel sampling, injected
- * sequences, watchdogs, offsets and other "advanced" features, and is 
+ * sequences, watchdogs, offsets and other "advanced" features, and is
  * found on the (so far) F3 and L4,
  * or only a much "simpler" version as found on (so far) f0 and l0.
- */ 
+ */
 
 /** @cond */
 #ifdef LIBOPENCM3_ADC_H

include/libopencm3/stm32/f0/adc.h

@@ -182,7 +182,7 @@ void adc_disable_vbat_sensor(void);
 void adc_calibrate_start(uint32_t adc)
 	LIBOPENCM3_DEPRECATED("see adc_calibrate/_async");
 void adc_calibrate_wait_finish(uint32_t adc)
-	LIBOPENCM3_DEPRECATED("see adc_is_calibrating"); ;
+	LIBOPENCM3_DEPRECATED("see adc_is_calibrating");
 
 /* Analog Watchdog */
 void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);

include/libopencm3/stm32/f1/adc.h

@@ -413,7 +413,7 @@ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger);
 void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger);
 void adc_reset_calibration(uint32_t adc);
 void adc_calibration(uint32_t adc)
-	LIBOPENCM3_DEPRECATED("see adc_calibrate/_async");;
+	LIBOPENCM3_DEPRECATED("see adc_calibrate/_async");
 void adc_calibrate_async(uint32_t adc);
 bool adc_is_calibrating(uint32_t adc);
 void adc_calibrate(uint32_t adc);

include/libopencm3/stm32/f4/memorymap.h

@@ -146,7 +146,7 @@
 /* Address: 0x80000000 */
 #define FMC_BANK3			(PERIPH_BASE_AHB3 + 0x20000000U)
 /* Address: 0x90000000 */
-#define QUADSPI_BANK 			(PERIPH_BASE_AHB3 + 0x30000000U)
+#define QUADSPI_BANK			(PERIPH_BASE_AHB3 + 0x30000000U)
 #define FSMC_BASE			(PERIPH_BASE_AHB3 + 0x40000000U)
 #define FMC_BASE			(PERIPH_BASE_AHB3 + 0x40000000U)
 #define QUADSPI_BASE			(PERIPH_BASE_AHB3 + 0x40001000U)

lib/lm3s/usart.c

@@ -38,12 +38,12 @@ void usart_send_blocking(uint32_t usart, uint16_t data)
 
 bool usart_is_recv_ready(uint32_t usart)
 {
-	return((USART_FR(usart) & USART_FR_RXFE) == 0);
+	return ((USART_FR(usart) & USART_FR_RXFE) == 0);
 }
 
 bool usart_is_send_ready(uint32_t usart)
 {
-	return((USART_FR(usart) & USART_FR_BUSY) == 0);
+	return ((USART_FR(usart) & USART_FR_BUSY) == 0);
 }
 
 uint16_t usart_recv_blocking(uint32_t usart)
@@ -84,5 +84,5 @@ void usart_clear_tx_interrupt(uint32_t usart)
 
 bool usart_get_interrupt_source(uint32_t usart, uint32_t flag)
 {
-    return ((USART_RIS(usart) & flag) != 0);
+	return ((USART_RIS(usart) & flag) != 0);
 }

lib/stm32/common/adc_common_v2.c

@@ -82,7 +82,7 @@ void adc_power_on_async(uint32_t adc)
  */
 bool adc_is_power_on(uint32_t adc)
 {
-	return (ADC_ISR(adc) & ADC_ISR_ADRDY);
+	return ADC_ISR(adc) & ADC_ISR_ADRDY;
 }
 
 /**
@@ -112,7 +112,7 @@ void adc_power_off_async(uint32_t adc)
 
 	uint32_t checks = ADC_CR_ADSTART;
 	uint32_t stops = ADC_CR_ADSTP;
-#if defined (ADC_CR_JADSTART)
+#if defined(ADC_CR_JADSTART)
 	checks |= ADC_CR_JADSTART;
 	stops |= ADC_CR_JADSTP;
 #endif
@@ -130,7 +130,7 @@ void adc_power_off_async(uint32_t adc)
  */
 bool adc_is_power_off(uint32_t adc)
 {
-	return (!(ADC_CR(adc) & ADC_CR_ADEN));
+	return !(ADC_CR(adc) & ADC_CR_ADEN);
 }
 
 /**
@@ -164,7 +164,7 @@ void adc_calibrate_async(uint32_t adc)
  */
 bool adc_is_calibrating(uint32_t adc)
 {
-	return (ADC_CR(adc) & ADC_CR_ADCAL);
+	return ADC_CR(adc) & ADC_CR_ADCAL;
 }
 
 /**

lib/stm32/common/adc_common_v2_multi.c

@@ -128,4 +128,5 @@ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
 	ADC_SQR4(adc) = reg32_4;
 }
 
-/**@}*/
+/**@}*/
+

lib/stm32/common/pwr_common_l01.c

@@ -44,4 +44,5 @@ void pwr_set_vos_scale(enum pwr_vos_scale scale)
 	PWR_CR = reg;
 }
 
-/**@}*/
+/**@}*/
+

lib/stm32/common/usart_common_v2.c

@@ -30,8 +30,8 @@
 /*---------------------------------------------------------------------------*/
 /** @brief USART enable data inversion
 
- Logical data from the data register are send/received in negative/inverse logic.
+ Logical data from the data register are send/received in negative/inverse
- (1=L, 0=H). The parity bit is also inverted.
+ logic. (1=L, 0=H). The parity bit is also inverted.
 
  @note This bit field can only be written when the USART is disabled.
 

lib/stm32/desig.c

@@ -36,7 +36,7 @@ void desig_get_unique_id_as_string(char *string,
 {
 	int i, len;
 	uint32_t dev_id_buf[3];
-	uint8_t *device_id = (uint8_t*)dev_id_buf;
+	uint8_t *device_id = (uint8_t *)dev_id_buf;
 	const char chars[] = "0123456789ABCDEF";
 
 	desig_get_unique_id(dev_id_buf);

lib/stm32/f0/rcc.c

@@ -206,19 +206,19 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
 {
 	switch (osc) {
 	case RCC_HSI48:
-		return (RCC_CR2 & RCC_CR2_HSI48RDY);
+		return RCC_CR2 & RCC_CR2_HSI48RDY;
 	case RCC_HSI14:
-		return (RCC_CR2 & RCC_CR2_HSI14RDY);
+		return RCC_CR2 & RCC_CR2_HSI14RDY;
 	case RCC_HSI:
-		return (RCC_CR & RCC_CR_HSIRDY);
+		return RCC_CR & RCC_CR_HSIRDY;
 	case RCC_HSE:
-		return (RCC_CR & RCC_CR_HSERDY);
+		return RCC_CR & RCC_CR_HSERDY;
 	case RCC_PLL:
-		return (RCC_CR & RCC_CR_PLLRDY);
+		return RCC_CR & RCC_CR_PLLRDY;
 	case RCC_LSE:
-		return (RCC_BDCR & RCC_BDCR_LSERDY);
+		return RCC_BDCR & RCC_BDCR_LSERDY;
 	case RCC_LSI:
-		return (RCC_CSR & RCC_CSR_LSIRDY);
+		return RCC_CSR & RCC_CSR_LSIRDY;
 	}
 	return false;
 }

lib/stm32/f1/rcc.c

@@ -221,19 +221,19 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
 {
 	switch (osc) {
 	case RCC_PLL:
-		return (RCC_CR & RCC_CR_PLLRDY);
+		return RCC_CR & RCC_CR_PLLRDY;
 	case RCC_PLL2:
-		return (RCC_CR & RCC_CR_PLL2RDY);
+		return RCC_CR & RCC_CR_PLL2RDY;
 	case RCC_PLL3:
-		return (RCC_CR & RCC_CR_PLL3RDY);
+		return RCC_CR & RCC_CR_PLL3RDY;
 	case RCC_HSE:
-		return (RCC_CR & RCC_CR_HSERDY);
+		return RCC_CR & RCC_CR_HSERDY;
 	case RCC_HSI:
-		return (RCC_CR & RCC_CR_HSIRDY);
+		return RCC_CR & RCC_CR_HSIRDY;
 	case RCC_LSE:
-		return (RCC_BDCR & RCC_BDCR_LSERDY);
+		return RCC_BDCR & RCC_BDCR_LSERDY;
 	case RCC_LSI:
-		return (RCC_CSR & RCC_CSR_LSIRDY);
+		return RCC_CSR & RCC_CSR_LSIRDY;
 	}
 	return false;
 }

lib/stm32/f2/rcc.c

@@ -164,15 +164,15 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
 {
 	switch (osc) {
 	case RCC_PLL:
-		return (RCC_CR & RCC_CR_PLLRDY);
+		return RCC_CR & RCC_CR_PLLRDY;
 	case RCC_HSE:
-		return (RCC_CR & RCC_CR_HSERDY);
+		return RCC_CR & RCC_CR_HSERDY;
 	case RCC_HSI:
-		return (RCC_CR & RCC_CR_HSIRDY);
+		return RCC_CR & RCC_CR_HSIRDY;
 	case RCC_LSE:
-		return (RCC_BDCR & RCC_BDCR_LSERDY);
+		return RCC_BDCR & RCC_BDCR_LSERDY;
 	case RCC_LSI:
-		return (RCC_CSR & RCC_CSR_LSIRDY);
+		return RCC_CSR & RCC_CSR_LSIRDY;
 	}
 	return false;
 }

lib/stm32/f3/rcc.c

@@ -180,15 +180,15 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
 {
 	switch (osc) {
 	case RCC_PLL:
-		return (RCC_CR & RCC_CR_PLLRDY);
+		return RCC_CR & RCC_CR_PLLRDY;
 	case RCC_HSE:
-		return (RCC_CR & RCC_CR_HSERDY);
+		return RCC_CR & RCC_CR_HSERDY;
 	case RCC_HSI:
-		return (RCC_CR & RCC_CR_HSIRDY);
+		return RCC_CR & RCC_CR_HSIRDY;
 	case RCC_LSE:
-		return (RCC_BDCR & RCC_BDCR_LSERDY);
+		return RCC_BDCR & RCC_BDCR_LSERDY;
 	case RCC_LSI:
-		return (RCC_CSR & RCC_CSR_LSIRDY);
+		return RCC_CSR & RCC_CSR_LSIRDY;
 	}
 	return false;
 }

lib/stm32/f4/rcc.c

@@ -425,19 +425,19 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
 {
 	switch (osc) {
 	case RCC_PLL:
-		return (RCC_CR & RCC_CR_PLLRDY);
+		return RCC_CR & RCC_CR_PLLRDY;
 	case RCC_HSE:
-		return (RCC_CR & RCC_CR_HSERDY);
+		return RCC_CR & RCC_CR_HSERDY;
 	case RCC_HSI:
-		return (RCC_CR & RCC_CR_HSIRDY);
+		return RCC_CR & RCC_CR_HSIRDY;
 	case RCC_LSE:
-		return (RCC_BDCR & RCC_BDCR_LSERDY);
+		return RCC_BDCR & RCC_BDCR_LSERDY;
 	case RCC_LSI:
-		return (RCC_CSR & RCC_CSR_LSIRDY);
+		return RCC_CSR & RCC_CSR_LSIRDY;
 	case RCC_PLLSAI:
-		return (RCC_CR & RCC_CR_PLLSAIRDY);
+		return RCC_CR & RCC_CR_PLLSAIRDY;
 	case RCC_PLLI2S:
-		return (RCC_CR & RCC_CR_PLLI2SRDY);
+		return RCC_CR & RCC_CR_PLLI2SRDY;
 	}
 	return false;
 }

lib/stm32/l0/rcc.c

@@ -262,19 +262,19 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
 {
 	switch (osc) {
 	case RCC_PLL:
-		return (RCC_CR & RCC_CR_PLLRDY);
+		return RCC_CR & RCC_CR_PLLRDY;
 	case RCC_HSE:
-		return (RCC_CR & RCC_CR_HSERDY);
+		return RCC_CR & RCC_CR_HSERDY;
 	case RCC_HSI16:
-		return (RCC_CR & RCC_CR_HSI16RDY);
+		return RCC_CR & RCC_CR_HSI16RDY;
 	case RCC_HSI48:
-		return (RCC_CRRCR & RCC_CRRCR_HSI48RDY);
+		return RCC_CRRCR & RCC_CRRCR_HSI48RDY;
 	case RCC_MSI:
-		return (RCC_CR & RCC_CR_MSIRDY);
+		return RCC_CR & RCC_CR_MSIRDY;
 	case RCC_LSE:
-		return (RCC_CSR & RCC_CSR_LSERDY);
+		return RCC_CSR & RCC_CSR_LSERDY;
 	case RCC_LSI:
-		return (RCC_CSR & RCC_CSR_LSIRDY);
+		return RCC_CSR & RCC_CSR_LSIRDY;
 	}
 	return false;
 }

lib/stm32/l1/rcc.c

@@ -232,17 +232,17 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
 {
 	switch (osc) {
 	case RCC_PLL:
-		return (RCC_CR & RCC_CR_PLLRDY);
+		return RCC_CR & RCC_CR_PLLRDY;
 	case RCC_HSE:
-		return (RCC_CR & RCC_CR_HSERDY);
+		return RCC_CR & RCC_CR_HSERDY;
 	case RCC_HSI:
-		return (RCC_CR & RCC_CR_HSIRDY);
+		return RCC_CR & RCC_CR_HSIRDY;
 	case RCC_MSI:
-		return (RCC_CR & RCC_CR_MSIRDY);
+		return RCC_CR & RCC_CR_MSIRDY;
 	case RCC_LSE:
-		return (RCC_CSR & RCC_CSR_LSERDY);
+		return RCC_CSR & RCC_CSR_LSERDY;
 	case RCC_LSI:
-		return (RCC_CSR & RCC_CSR_LSIRDY);
+		return RCC_CSR & RCC_CSR_LSIRDY;
 	}
 	return false;
 }
@@ -534,8 +534,9 @@ void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock)
 	}
 
 	rcc_wait_for_osc_ready(RCC_HSI);
-	while (PWR_CSR & PWR_CSR_VOSF)
+	while (PWR_CSR & PWR_CSR_VOSF) {
 		;
+	}
 	rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
 
 	/* Set the peripheral clock frequencies used. */

lib/stm32/l4/adc.c

@@ -55,4 +55,5 @@ void adc_disable_regulator(uint32_t adc)
 	ADC_CR(adc) &= ~ADC_CR_ADVREGEN;
 }
 
-/**@}*/
+/**@}*/
+

lib/stm32/l4/flash.c

@@ -246,7 +246,7 @@ void flash_lock_option_bytes(void)
  * This performs all operations necessary to program a 32 bit word to FLASH
  * memory. The program error flag should be checked separately for the event
  * that memory was not properly erased.
- * 
+ *
  * @param[in] address Starting address in Flash.
  * @param[in] data word to write
  */
@@ -340,4 +340,5 @@ void flash_program_option_bytes(uint32_t data)
 	FLASH_OPTR |= FLASH_CR_OPTSTRT;
 	flash_wait_for_last_operation();
 }
-/**@}*/
+/**@}*/
+

lib/stm32/l4/rcc.c

@@ -155,17 +155,17 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
 {
 	switch (osc) {
 	case RCC_PLL:
-		return (RCC_CR & RCC_CR_PLLRDY);
+		return RCC_CR & RCC_CR_PLLRDY;
 	case RCC_HSE:
-		return (RCC_CR & RCC_CR_HSERDY);
+		return RCC_CR & RCC_CR_HSERDY;
 	case RCC_HSI16:
-		return (RCC_CR & RCC_CR_HSIRDY);
+		return RCC_CR & RCC_CR_HSIRDY;
 	case RCC_MSI:
-		return (RCC_CR & RCC_CR_MSIRDY);
+		return RCC_CR & RCC_CR_MSIRDY;
 	case RCC_LSE:
-		return (RCC_BDCR & RCC_BDCR_LSERDY);
+		return RCC_BDCR & RCC_BDCR_LSERDY;
 	case RCC_LSI:
-		return (RCC_CSR & RCC_CSR_LSIRDY);
+		return RCC_CSR & RCC_CSR_LSIRDY;
 	}
 	return false;
 }
@@ -353,7 +353,7 @@ void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pl
 uint32_t rcc_system_clock_source(void)
 {
 	/* Return the clock source which is used as system clock. */
-	return ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK);
+	return (RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK;
 }
 
 /**

lib/vf6xx/ccm.c

@@ -45,13 +45,13 @@ static const uint32_t pll2_main_clk = 528000000;
 static const uint32_t pll3_main_clk = 480000000;
 
 /* ARM Cortex-A5 clock, core clock */
-uint32_t ccm_core_clk = 0;
+uint32_t ccm_core_clk;
 
 /* Platform bus clock and Cortex-M4 core clock */
-uint32_t ccm_platform_bus_clk = 0;
+uint32_t ccm_platform_bus_clk;
 
 /* IPS bus clock */
-uint32_t ccm_ipg_bus_clk = 0;
+uint32_t ccm_ipg_bus_clk;
 
 
 uint32_t ccm_get_pll_pfd(uint32_t pfd_sel, uint32_t pll_pfd, uint32_t pll_clk);

tests/gadget-zero/main-stm32f072disco.c

@@ -28,10 +28,10 @@
 /* no trace on cm0 #define ER_DEBUG */
 #ifdef ER_DEBUG
 #define ER_DPRINTF(fmt, ...) \
-    do { printf(fmt, ## __VA_ARGS__); } while (0)
+	do { printf(fmt, ## __VA_ARGS__); } while (0)
 #else
 #define ER_DPRINTF(fmt, ...) \
-    do { } while (0)
+	do { } while (0)
 #endif
 
 #include "trace.h"

tests/gadget-zero/main-stm32f103-generic.c

@@ -27,10 +27,10 @@
 #define ER_DEBUG
 #ifdef ER_DEBUG
 #define ER_DPRINTF(fmt, ...) \
-    do { printf(fmt, ## __VA_ARGS__); } while (0)
+	do { printf(fmt, ## __VA_ARGS__); } while (0)
 #else
 #define ER_DPRINTF(fmt, ...) \
-    do { } while (0)
+	do { } while (0)
 #endif
 
 int main(void)

tests/gadget-zero/main-stm32f429i-disco.c

@@ -27,10 +27,10 @@
 #define ER_DEBUG
 #ifdef ER_DEBUG
 #define ER_DPRINTF(fmt, ...) \
-    do { printf(fmt, ## __VA_ARGS__); } while (0)
+	do { printf(fmt, ## __VA_ARGS__); } while (0)
 #else
 #define ER_DPRINTF(fmt, ...) \
-    do { } while (0)
+	do { } while (0)
 #endif
 
 int main(void)

tests/gadget-zero/main-stm32f4disco.c

@@ -27,10 +27,10 @@
 #define ER_DEBUG
 #ifdef ER_DEBUG
 #define ER_DPRINTF(fmt, ...) \
-    do { printf(fmt, ## __VA_ARGS__); } while (0)
+	do { printf(fmt, ## __VA_ARGS__); } while (0)
 #else
 #define ER_DPRINTF(fmt, ...) \
-    do { } while (0)
+	do { } while (0)
 #endif
 
 int main(void)

tests/gadget-zero/main-stm32l053disco.c

@@ -29,10 +29,10 @@
 /* no trace on cm0 #define ER_DEBUG */
 #ifdef ER_DEBUG
 #define ER_DPRINTF(fmt, ...) \
-    do { printf(fmt, ## __VA_ARGS__); } while (0)
+	do { printf(fmt, ## __VA_ARGS__); } while (0)
 #else
 #define ER_DPRINTF(fmt, ...) \
-    do { } while (0)
+	do { } while (0)
 #endif
 
 #include "trace.h"

tests/gadget-zero/main-stm32l1-generic.c

@@ -28,10 +28,10 @@
 #define ER_DEBUG
 #ifdef ER_DEBUG
 #define ER_DPRINTF(fmt, ...) \
-    do { printf(fmt, ## __VA_ARGS__); } while (0)
+	do { printf(fmt, ## __VA_ARGS__); } while (0)
 #else
 #define ER_DPRINTF(fmt, ...) \
-    do { } while (0)
+	do { } while (0)
 #endif
 
 const struct rcc_clock_scale this_clock_config = {