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style: fix some of the easier style bugs

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No real changes.
This commit is contained in:
Karl Palsson 2017-01-12 21:22:58 +00:00
parent 4af374f7c4
commit c9c5cb7c9c
30 changed files with 107 additions and 102 deletions
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4
include/libopencm3/sam/d/port.h
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@ -23,8 +23,8 @@
/* --- Convenience macros ------------------------------------------------ */
#define PORTA PORT_BASE + 0
#define PORTB PORT_BASE + 0x80
#define PORTA (PORT_BASE + 0)
#define PORTB (PORT_BASE + 0x80)
/* --- PORT registers ----------------------------------------------------- */

2
include/libopencm3/stm32/f0/adc.h
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@ -182,7 +182,7 @@ void adc_disable_vbat_sensor(void);
void adc_calibrate_start(uint32_t adc)
LIBOPENCM3_DEPRECATED("see adc_calibrate/_async");
void adc_calibrate_wait_finish(uint32_t adc)
LIBOPENCM3_DEPRECATED("see adc_is_calibrating"); ;
LIBOPENCM3_DEPRECATED("see adc_is_calibrating");
/* Analog Watchdog */
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);

2
include/libopencm3/stm32/f1/adc.h
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@ -413,7 +413,7 @@ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger);
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger);
void adc_reset_calibration(uint32_t adc);
void adc_calibration(uint32_t adc)
LIBOPENCM3_DEPRECATED("see adc_calibrate/_async");;
LIBOPENCM3_DEPRECATED("see adc_calibrate/_async");
void adc_calibrate_async(uint32_t adc);
bool adc_is_calibrating(uint32_t adc);
void adc_calibrate(uint32_t adc);

4
lib/lm3s/usart.c
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@ -38,12 +38,12 @@ void usart_send_blocking(uint32_t usart, uint16_t data)
bool usart_is_recv_ready(uint32_t usart)
{
return((USART_FR(usart) & USART_FR_RXFE) == 0);
return ((USART_FR(usart) & USART_FR_RXFE) == 0);
}
bool usart_is_send_ready(uint32_t usart)
{
return((USART_FR(usart) & USART_FR_BUSY) == 0);
return ((USART_FR(usart) & USART_FR_BUSY) == 0);
}
uint16_t usart_recv_blocking(uint32_t usart)

8
lib/stm32/common/adc_common_v2.c
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@ -82,7 +82,7 @@ void adc_power_on_async(uint32_t adc)
*/
bool adc_is_power_on(uint32_t adc)
{
return (ADC_ISR(adc) & ADC_ISR_ADRDY);
return ADC_ISR(adc) & ADC_ISR_ADRDY;
}
/**
@ -112,7 +112,7 @@ void adc_power_off_async(uint32_t adc)
uint32_t checks = ADC_CR_ADSTART;
uint32_t stops = ADC_CR_ADSTP;
#if defined (ADC_CR_JADSTART)
#if defined(ADC_CR_JADSTART)
checks |= ADC_CR_JADSTART;
stops |= ADC_CR_JADSTP;
#endif
@ -130,7 +130,7 @@ void adc_power_off_async(uint32_t adc)
*/
bool adc_is_power_off(uint32_t adc)
{
return (!(ADC_CR(adc) & ADC_CR_ADEN));
return !(ADC_CR(adc) & ADC_CR_ADEN);
}
/**
@ -164,7 +164,7 @@ void adc_calibrate_async(uint32_t adc)
*/
bool adc_is_calibrating(uint32_t adc)
{
return (ADC_CR(adc) & ADC_CR_ADCAL);
return ADC_CR(adc) & ADC_CR_ADCAL;
}
/**

1
lib/stm32/common/adc_common_v2_multi.c
View File

@ -129,3 +129,4 @@ void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
}
/**@}*/

1
lib/stm32/common/pwr_common_l01.c
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@ -45,3 +45,4 @@ void pwr_set_vos_scale(enum pwr_vos_scale scale)
}
/**@}*/

4
lib/stm32/common/usart_common_v2.c
View File

@ -30,8 +30,8 @@
/*---------------------------------------------------------------------------*/
/** @brief USART enable data inversion
Logical data from the data register are send/received in negative/inverse logic.
(1=L, 0=H). The parity bit is also inverted.
Logical data from the data register are send/received in negative/inverse
logic. (1=L, 0=H). The parity bit is also inverted.
@note This bit field can only be written when the USART is disabled.

2
lib/stm32/desig.c
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@ -36,7 +36,7 @@ void desig_get_unique_id_as_string(char *string,
{
int i, len;
uint32_t dev_id_buf[3];
uint8_t *device_id = (uint8_t*)dev_id_buf;
uint8_t *device_id = (uint8_t *)dev_id_buf;
const char chars[] = "0123456789ABCDEF";
desig_get_unique_id(dev_id_buf);

14
lib/stm32/f0/rcc.c
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@ -206,19 +206,19 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
return (RCC_CR2 & RCC_CR2_HSI48RDY);
return RCC_CR2 & RCC_CR2_HSI48RDY;
case RCC_HSI14:
return (RCC_CR2 & RCC_CR2_HSI14RDY);
return RCC_CR2 & RCC_CR2_HSI14RDY;
case RCC_HSI:
return (RCC_CR & RCC_CR_HSIRDY);
return RCC_CR & RCC_CR_HSIRDY;
case RCC_HSE:
return (RCC_CR & RCC_CR_HSERDY);
return RCC_CR & RCC_CR_HSERDY;
case RCC_PLL:
return (RCC_CR & RCC_CR_PLLRDY);
return RCC_CR & RCC_CR_PLLRDY;
case RCC_LSE:
return (RCC_BDCR & RCC_BDCR_LSERDY);
return RCC_BDCR & RCC_BDCR_LSERDY;
case RCC_LSI:
return (RCC_CSR & RCC_CSR_LSIRDY);
return RCC_CSR & RCC_CSR_LSIRDY;
}
return false;
}

14
lib/stm32/f1/rcc.c
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@ -221,19 +221,19 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return (RCC_CR & RCC_CR_PLLRDY);
return RCC_CR & RCC_CR_PLLRDY;
case RCC_PLL2:
return (RCC_CR & RCC_CR_PLL2RDY);
return RCC_CR & RCC_CR_PLL2RDY;
case RCC_PLL3:
return (RCC_CR & RCC_CR_PLL3RDY);
return RCC_CR & RCC_CR_PLL3RDY;
case RCC_HSE:
return (RCC_CR & RCC_CR_HSERDY);
return RCC_CR & RCC_CR_HSERDY;
case RCC_HSI:
return (RCC_CR & RCC_CR_HSIRDY);
return RCC_CR & RCC_CR_HSIRDY;
case RCC_LSE:
return (RCC_BDCR & RCC_BDCR_LSERDY);
return RCC_BDCR & RCC_BDCR_LSERDY;
case RCC_LSI:
return (RCC_CSR & RCC_CSR_LSIRDY);
return RCC_CSR & RCC_CSR_LSIRDY;
}
return false;
}

10
lib/stm32/f2/rcc.c
View File

@ -164,15 +164,15 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return (RCC_CR & RCC_CR_PLLRDY);
return RCC_CR & RCC_CR_PLLRDY;
case RCC_HSE:
return (RCC_CR & RCC_CR_HSERDY);
return RCC_CR & RCC_CR_HSERDY;
case RCC_HSI:
return (RCC_CR & RCC_CR_HSIRDY);
return RCC_CR & RCC_CR_HSIRDY;
case RCC_LSE:
return (RCC_BDCR & RCC_BDCR_LSERDY);
return RCC_BDCR & RCC_BDCR_LSERDY;
case RCC_LSI:
return (RCC_CSR & RCC_CSR_LSIRDY);
return RCC_CSR & RCC_CSR_LSIRDY;
}
return false;
}

10
lib/stm32/f3/rcc.c
View File

@ -180,15 +180,15 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return (RCC_CR & RCC_CR_PLLRDY);
return RCC_CR & RCC_CR_PLLRDY;
case RCC_HSE:
return (RCC_CR & RCC_CR_HSERDY);
return RCC_CR & RCC_CR_HSERDY;
case RCC_HSI:
return (RCC_CR & RCC_CR_HSIRDY);
return RCC_CR & RCC_CR_HSIRDY;
case RCC_LSE:
return (RCC_BDCR & RCC_BDCR_LSERDY);
return RCC_BDCR & RCC_BDCR_LSERDY;
case RCC_LSI:
return (RCC_CSR & RCC_CSR_LSIRDY);
return RCC_CSR & RCC_CSR_LSIRDY;
}
return false;
}

14
lib/stm32/f4/rcc.c
View File

@ -425,19 +425,19 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return (RCC_CR & RCC_CR_PLLRDY);
return RCC_CR & RCC_CR_PLLRDY;
case RCC_HSE:
return (RCC_CR & RCC_CR_HSERDY);
return RCC_CR & RCC_CR_HSERDY;
case RCC_HSI:
return (RCC_CR & RCC_CR_HSIRDY);
return RCC_CR & RCC_CR_HSIRDY;
case RCC_LSE:
return (RCC_BDCR & RCC_BDCR_LSERDY);
return RCC_BDCR & RCC_BDCR_LSERDY;
case RCC_LSI:
return (RCC_CSR & RCC_CSR_LSIRDY);
return RCC_CSR & RCC_CSR_LSIRDY;
case RCC_PLLSAI:
return (RCC_CR & RCC_CR_PLLSAIRDY);
return RCC_CR & RCC_CR_PLLSAIRDY;
case RCC_PLLI2S:
return (RCC_CR & RCC_CR_PLLI2SRDY);
return RCC_CR & RCC_CR_PLLI2SRDY;
}
return false;
}

14
lib/stm32/l0/rcc.c
View File

@ -262,19 +262,19 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return (RCC_CR & RCC_CR_PLLRDY);
return RCC_CR & RCC_CR_PLLRDY;
case RCC_HSE:
return (RCC_CR & RCC_CR_HSERDY);
return RCC_CR & RCC_CR_HSERDY;
case RCC_HSI16:
return (RCC_CR & RCC_CR_HSI16RDY);
return RCC_CR & RCC_CR_HSI16RDY;
case RCC_HSI48:
return (RCC_CRRCR & RCC_CRRCR_HSI48RDY);
return RCC_CRRCR & RCC_CRRCR_HSI48RDY;
case RCC_MSI:
return (RCC_CR & RCC_CR_MSIRDY);
return RCC_CR & RCC_CR_MSIRDY;
case RCC_LSE:
return (RCC_CSR & RCC_CSR_LSERDY);
return RCC_CSR & RCC_CSR_LSERDY;
case RCC_LSI:
return (RCC_CSR & RCC_CSR_LSIRDY);
return RCC_CSR & RCC_CSR_LSIRDY;
}
return false;
}

15
lib/stm32/l1/rcc.c
View File

@ -232,17 +232,17 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return (RCC_CR & RCC_CR_PLLRDY);
return RCC_CR & RCC_CR_PLLRDY;
case RCC_HSE:
return (RCC_CR & RCC_CR_HSERDY);
return RCC_CR & RCC_CR_HSERDY;
case RCC_HSI:
return (RCC_CR & RCC_CR_HSIRDY);
return RCC_CR & RCC_CR_HSIRDY;
case RCC_MSI:
return (RCC_CR & RCC_CR_MSIRDY);
return RCC_CR & RCC_CR_MSIRDY;
case RCC_LSE:
return (RCC_CSR & RCC_CSR_LSERDY);
return RCC_CSR & RCC_CSR_LSERDY;
case RCC_LSI:
return (RCC_CSR & RCC_CSR_LSIRDY);
return RCC_CSR & RCC_CSR_LSIRDY;
}
return false;
}
@ -534,8 +534,9 @@ void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock)
}
rcc_wait_for_osc_ready(RCC_HSI);
while (PWR_CSR & PWR_CSR_VOSF)
while (PWR_CSR & PWR_CSR_VOSF) {
;
}
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
/* Set the peripheral clock frequencies used. */

1
lib/stm32/l4/adc.c
View File

@ -56,3 +56,4 @@ void adc_disable_regulator(uint32_t adc)
}
/**@}*/

1
lib/stm32/l4/flash.c
View File

@ -341,3 +341,4 @@ void flash_program_option_bytes(uint32_t data)
flash_wait_for_last_operation();
}
/**@}*/

14
lib/stm32/l4/rcc.c
View File

@ -155,17 +155,17 @@ bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return (RCC_CR & RCC_CR_PLLRDY);
return RCC_CR & RCC_CR_PLLRDY;
case RCC_HSE:
return (RCC_CR & RCC_CR_HSERDY);
return RCC_CR & RCC_CR_HSERDY;
case RCC_HSI16:
return (RCC_CR & RCC_CR_HSIRDY);
return RCC_CR & RCC_CR_HSIRDY;
case RCC_MSI:
return (RCC_CR & RCC_CR_MSIRDY);
return RCC_CR & RCC_CR_MSIRDY;
case RCC_LSE:
return (RCC_BDCR & RCC_BDCR_LSERDY);
return RCC_BDCR & RCC_BDCR_LSERDY;
case RCC_LSI:
return (RCC_CSR & RCC_CSR_LSIRDY);
return RCC_CSR & RCC_CSR_LSIRDY;
}
return false;
}
@ -353,7 +353,7 @@ void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pl
uint32_t rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK);
return (RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK;
}
/**

6
lib/vf6xx/ccm.c
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@ -45,13 +45,13 @@ static const uint32_t pll2_main_clk = 528000000;
static const uint32_t pll3_main_clk = 480000000;
/* ARM Cortex-A5 clock, core clock */
uint32_t ccm_core_clk = 0;
uint32_t ccm_core_clk;
/* Platform bus clock and Cortex-M4 core clock */
uint32_t ccm_platform_bus_clk = 0;
uint32_t ccm_platform_bus_clk;
/* IPS bus clock */
uint32_t ccm_ipg_bus_clk = 0;
uint32_t ccm_ipg_bus_clk;
uint32_t ccm_get_pll_pfd(uint32_t pfd_sel, uint32_t pll_pfd, uint32_t pll_clk);