From ca43a73ea357fa505423ec229d4ff1091157718f Mon Sep 17 00:00:00 2001
From: Karl Palsson <karlp@tweak.net.au>
Date: Thu, 9 May 2019 11:49:25 +0000
Subject: [PATCH] stm32: dac: move DAC_SR to common.

It's available on f0, f2, f3, f4, f7, l0, l1 and l4.
Just note that it's not available on f1.
---
 .../libopencm3/stm32/common/dac_common_all.h    | 13 +++++++++++++
 include/libopencm3/stm32/f4/dac.h               | 17 -----------------
 include/libopencm3/stm32/f7/dac.h               | 14 --------------
 3 files changed, 13 insertions(+), 31 deletions(-)

diff --git a/include/libopencm3/stm32/common/dac_common_all.h b/include/libopencm3/stm32/common/dac_common_all.h
index 7a241ab8..258af88b 100644
--- a/include/libopencm3/stm32/common/dac_common_all.h
+++ b/include/libopencm3/stm32/common/dac_common_all.h
@@ -77,6 +77,10 @@ specific memorymap.h header before including this header file.*/
 /* DAC channel2 data output register (DAC_DOR2) */
 #define DAC_DOR2			MMIO32(DAC_BASE + 0x30)
 
+/** DAC status register.
+ * @note not available on F1
+ */
+#define DAC_SR				MMIO32(DAC_BASE + 0x34)
 
 /* --- DAC_CR values ------------------------------------------------------- */
 
@@ -377,6 +381,15 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
 #define DAC_DOR2_DACC2DOR_LSB		(1 << 0)
 #define DAC_DOR2_DACC2DOR_MSK		(0x0FFF << 0)
 
+/** @defgroup dac_sr_values DAC_SR Values
+@{*/
+/** DAC channel 1 DMA underrun flag */
+#define DAC_SR_DMAUDR1		(1 << 13)
+
+/** DAC channel 2 DMA underrun flag */
+#define DAC_SR_DMAUDR2		(1 << 29)
+/*@}*/
+
 /** DAC channel identifier */
 typedef enum {
 	CHANNEL_1, CHANNEL_2, CHANNEL_D
diff --git a/include/libopencm3/stm32/f4/dac.h b/include/libopencm3/stm32/f4/dac.h
index c13a6a32..3a384032 100644
--- a/include/libopencm3/stm32/f4/dac.h
+++ b/include/libopencm3/stm32/f4/dac.h
@@ -33,21 +33,4 @@ LGPL License Terms @ref lgpl_license
 
 #include <libopencm3/stm32/common/dac_common_all.h>
 
-
-/** DAC status register (DAC_SR).
- * not available on STM32F4x1/STM32F4x2 */
-#define DAC_SR				MMIO32(DAC_BASE + 0x34)
-
-/* --- DAC_SR values ------------------------------------------------------- */
-
-/** DMAUDR2: DAC channel 1 DMA underrun flag */
-#define DAC_SR_DMAUDR1		(1 << 13)
-
-
-/** DMAUDR2: DAC channel 2 DMA underrun flag.
- * not available on STM32F4x1/STM32F4x2 and STM32F410*/
-#define DAC_SR_DMAUDR2		(1 << 29)
-
-
 #endif
-
diff --git a/include/libopencm3/stm32/f7/dac.h b/include/libopencm3/stm32/f7/dac.h
index 5f6c34d2..1e5607e4 100644
--- a/include/libopencm3/stm32/f7/dac.h
+++ b/include/libopencm3/stm32/f7/dac.h
@@ -33,18 +33,4 @@ LGPL License Terms @ref lgpl_license
 
 #include <libopencm3/stm32/common/dac_common_all.h>
 
-/** DAC status register (DAC_SR) */
-#define DAC_SR				MMIO32(DAC_BASE + 0x34)
-
-/* --- DAC_SR values ------------------------------------------------------- */
-
-/** DMAUDR1: DAC channel 1 DMA underrun flag */
-#define DAC_SR_DMAUDR1		(1 << 13)
-
-
-/** DMAUDR2: DAC channel 2 DMA underrun flag */
-#define DAC_SR_DMAUDR2		(1 << 29)
-
-
 #endif
-