doc: cm3/scb+scs: turn on existing documentation
Lots of registers were already documented extensively. Turn it all in doxygen with groups and the right syntax.
This commit is contained in:
Karl Palsson
parent
1ad2cda496
commit
cae295ee2c
@ -29,168 +29,184 @@
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#include <libopencm3/cm3/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- SCB: Registers ------------------------------------------------------ */
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/** @defgroup cm_scb_registers SCB Registers
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* @ingroup cm_scb
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* @{
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*/
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/* CPUID: CPUID base register */
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/** CPUID: CPUID base register */
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#define SCB_CPUID MMIO32(SCB_BASE + 0x00)
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/* ICSR: Interrupt Control State Register */
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/** ICSR: Interrupt Control State Register */
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#define SCB_ICSR MMIO32(SCB_BASE + 0x04)
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/* VTOR: Vector Table Offset Register */
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/** VTOR: Vector Table Offset Register */
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#define SCB_VTOR MMIO32(SCB_BASE + 0x08)
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/* AIRCR: Application Interrupt and Reset Control Register */
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/** AIRCR: Application Interrupt and Reset Control Register */
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#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C)
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/* SCR: System Control Register */
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/** SCR: System Control Register */
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#define SCB_SCR MMIO32(SCB_BASE + 0x10)
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/* CCR: Configuration Control Register */
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/** CCR: Configuration Control Register */
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#define SCB_CCR MMIO32(SCB_BASE + 0x14)
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/* SHP: System Handler Priority Registers */
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/* Note: 12 8bit registers */
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/** SHP: System Handler Priority Registers.
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* Note: 12 8bit registers
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*/
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#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + (shpr_id))
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#define SCB_SHPR1 MMIO32(SCB_BASE + 0x18)
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#define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C)
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#define SCB_SHPR3 MMIO32(SCB_BASE + 0x20)
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/* SHCSR: System Handler Control and State Register */
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/** SHCSR: System Handler Control and State Register */
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#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
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/* DFSR: Debug Fault Status Register */
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/** DFSR: Debug Fault Status Register */
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#define SCB_DFSR MMIO32(SCB_BASE + 0x30)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* CFSR: Configurable Fault Status Registers */
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/** CFSR: Configurable Fault Status Registers */
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#define SCB_CFSR MMIO32(SCB_BASE + 0x28)
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/* HFSR: Hard Fault Status Register */
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/** HFSR: Hard Fault Status Register */
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#define SCB_HFSR MMIO32(SCB_BASE + 0x2C)
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/* MMFAR: Memory Manage Fault Address Register */
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/** MMFAR: Memory Manage Fault Address Register */
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#define SCB_MMFAR MMIO32(SCB_BASE + 0x34)
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/* BFAR: Bus Fault Address Register */
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/** BFAR: Bus Fault Address Register */
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#define SCB_BFAR MMIO32(SCB_BASE + 0x38)
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/* AFSR: Auxiliary Fault Status Register */
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/** AFSR: Auxiliary Fault Status Register */
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#define SCB_AFSR MMIO32(SCB_BASE + 0x3C)
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/* ID_PFR0: Processor Feature Register 0 */
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/** ID_PFR0: Processor Feature Register 0 */
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#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40)
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/* ID_PFR1: Processor Feature Register 1 */
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/** ID_PFR1: Processor Feature Register 1 */
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#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44)
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/* ID_DFR0: Debug Features Register 0 */
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/** ID_DFR0: Debug Features Register 0 */
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#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48)
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/* ID_AFR0: Auxiliary Features Register 0 */
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/** ID_AFR0: Auxiliary Features Register 0 */
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#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C)
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/* ID_MMFR0: Memory Model Feature Register 0 */
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/** ID_MMFR0: Memory Model Feature Register 0 */
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#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50)
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/* ID_MMFR1: Memory Model Feature Register 1 */
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/** ID_MMFR1: Memory Model Feature Register 1 */
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#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54)
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/* ID_MMFR2: Memory Model Feature Register 2 */
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/** ID_MMFR2: Memory Model Feature Register 2 */
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#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58)
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/* ID_MMFR3: Memory Model Feature Register 3 */
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/** ID_MMFR3: Memory Model Feature Register 3 */
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#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C)
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/* ID_ISAR0: Instruction Set Attributes Register 0 */
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/** ID_ISAR0: Instruction Set Attributes Register 0 */
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#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60)
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/* ID_ISAR1: Instruction Set Attributes Register 1 */
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/** ID_ISAR1: Instruction Set Attributes Register 1 */
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#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64)
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/* ID_ISAR2: Instruction Set Attributes Register 2 */
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/** ID_ISAR2: Instruction Set Attributes Register 2 */
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#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68)
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/* ID_ISAR3: Instruction Set Attributes Register 3 */
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/** ID_ISAR3: Instruction Set Attributes Register 3 */
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#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C)
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/* ID_ISAR4: Instruction Set Attributes Register 4 */
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/** ID_ISAR4: Instruction Set Attributes Register 4 */
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#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70)
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/* CPACR: Coprocessor Access Control Register */
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/** CPACR: Coprocessor Access Control Register */
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#define SCB_CPACR MMIO32(SCB_BASE + 0x88)
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/* FPCCR: Floating-Point Context Control Register */
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/** FPCCR: Floating-Point Context Control Register */
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#define SCB_FPCCR MMIO32(SCB_BASE + 0x234)
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/* FPCAR: Floating-Point Context Address Register */
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/** FPCAR: Floating-Point Context Address Register */
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#define SCB_FPCAR MMIO32(SCB_BASE + 0x238)
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/* FPDSCR: Floating-Point Default Status Control Register */
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/** FPDSCR: Floating-Point Default Status Control Register */
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#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C)
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/* MVFR0: Media and Floating-Point Feature Register 0 */
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/** MVFR0: Media and Floating-Point Feature Register 0 */
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#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240)
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/* MVFR1: Media and Floating-Point Feature Register 1 */
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/** MVFR1: Media and Floating-Point Feature Register 1 */
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#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
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#endif
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/**@}*/
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/* --- SCB values ---------------------------------------------------------- */
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/* --- SCB_CPUID values ---------------------------------------------------- */
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/* Implementer[31:24]: Implementer code */
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/**
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* @defgroup cm3_scb_cpuid_values SCB_CPUID Values
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* @{
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*/
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/** Implementer[31:24]: Implementer code */
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#define SCB_CPUID_IMPLEMENTER_LSB 24
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#define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)
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/* Variant[23:20]: Variant number */
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/** Variant[23:20]: Variant number */
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#define SCB_CPUID_VARIANT_LSB 20
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#define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)
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/* Constant[19:16]: Reads as 0xF (ARMv7-M) M3, M4 */
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/* Constant[19:16]: Reads as 0xC (ARMv6-M) M0, M0+ */
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/** Constant[19:16]
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* Reads as 0xF (ARMv7-M) M3, M4
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* Reads as 0xC (ARMv6-M) M0, M0+
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*/
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#define SCB_CPUID_CONSTANT_LSB 16
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#define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)
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#define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)
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#define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)
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/* PartNo[15:4]: Part number of the processor */
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/** PartNo[15:4]: Part number of the processor */
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#define SCB_CPUID_PARTNO_LSB 4
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#define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)
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/* Revision[3:0]: Revision number */
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/** Revision[3:0]: Revision number */
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#define SCB_CPUID_REVISION_LSB 0
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#define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)
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/**@}*/
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/* --- SCB_ICSR values ----------------------------------------------------- */
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/* NMIPENDSET: NMI set-pending bit */
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/**
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* @defgroup cm3_scb_icsr_values SCB_ICSR Values
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* @{
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*/
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/** NMIPENDSET: NMI set-pending bit */
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#define SCB_ICSR_NMIPENDSET (1 << 31)
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/* Bits [30:29]: reserved - must be kept cleared */
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/* PENDSVSET: PendSV set-pending bit */
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/** PENDSVSET: PendSV set-pending bit */
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#define SCB_ICSR_PENDSVSET (1 << 28)
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/* PENDSVCLR: PendSV clear-pending bit */
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/** PENDSVCLR: PendSV clear-pending bit */
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#define SCB_ICSR_PENDSVCLR (1 << 27)
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/* PENDSTSET: SysTick exception set-pending bit */
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/** PENDSTSET: SysTick exception set-pending bit */
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#define SCB_ICSR_PENDSTSET (1 << 26)
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/* PENDSTCLR: SysTick exception clear-pending bit */
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/** PENDSTCLR: SysTick exception clear-pending bit */
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#define SCB_ICSR_PENDSTCLR (1 << 25)
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/* Bit 24: reserved - must be kept cleared */
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/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
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/** Bit 23: reserved for debug - reads as 0 when not in debug mode */
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#define SCB_ICSR_ISRPREEMPT (1 << 23)
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/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
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/** ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
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#define SCB_ICSR_ISRPENDING (1 << 22)
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/* VECTPENDING[21:12] Pending vector */
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/** VECTPENDING[21:12] Pending vector */
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#define SCB_ICSR_VECTPENDING_LSB 12
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#define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)
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/* RETOBASE: Return to base level */
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/** RETOBASE: Return to base level */
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#define SCB_ICSR_RETOBASE (1 << 11)
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/* Bits [10:9]: reserved - must be kept cleared */
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/* VECTACTIVE[8:0] Active vector */
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/** VECTACTIVE[8:0] Active vector */
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#define SCB_ICSR_VECTACTIVE_LSB 0
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#define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)
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/**@}*/
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/* --- SCB_VTOR values ----------------------------------------------------- */
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/**
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* @defgroup cm3_scb_vtor_values SCB_VTOR Values
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* @{
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*/
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/* IMPLEMENTATION DEFINED */
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@ -212,21 +228,25 @@
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#define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB)
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#endif
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/**@}*/
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/* --- SCB_AIRCR values ---------------------------------------------------- */
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/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
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/**
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* @defgroup cm3_scb_aicr_values SCB_AICR Values
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* @{
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*/
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/** VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
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#define SCB_AIRCR_VECTKEYSTAT_LSB 16
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#define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)
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#define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)
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/* ENDIANNESS Data endianness bit */
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/** ENDIANNESS Data endianness bit */
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#define SCB_AIRCR_ENDIANESS (1 << 15)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* Bits [14:11]: reserved - must be kept cleared */
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/* PRIGROUP[10:8]: Interrupt priority grouping field */
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/** PRIGROUP[10:8]: Interrupt priority grouping field */
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#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
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#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8)
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#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8)
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@ -237,55 +257,62 @@
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/* Bits [7:3]: reserved - must be kept cleared */
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#endif
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/* SYSRESETREQ System reset request */
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/** SYSRESETREQ System reset request */
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#define SCB_AIRCR_SYSRESETREQ (1 << 2)
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/* VECTCLRACTIVE */
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/** VECTCLRACTIVE clears state information for exceptions */
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#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* VECTRESET */
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/** VECTRESET cause local system reset */
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#define SCB_AIRCR_VECTRESET (1 << 0)
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#endif
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/**@}*/
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/* --- SCB_SCR values ------------------------------------------------------ */
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/**
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* @defgroup cm3_scb_scr_values SCB_SCR Values
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* @{
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*/
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/* Bits [31:5]: reserved - must be kept cleared */
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/* SEVONPEND Send Event on Pending bit */
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/** SEVONPEND Send Event on Pending bit */
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#define SCB_SCR_SEVONPEND (1 << 4)
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/* Bit 3: reserved - must be kept cleared */
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/* SLEEPDEEP */
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/** SLEEPDEEP implementation defined */
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#define SCB_SCR_SLEEPDEEP (1 << 2)
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/* SLEEPONEXIT */
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/** SLEEPONEXIT sleep when exiting ISR */
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#define SCB_SCR_SLEEPONEXIT (1 << 1)
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/* Bit 0: reserved - must be kept cleared */
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/**@}*/
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/* --- SCB_CCR values ------------------------------------------------------ */
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/**
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* @defgroup cm3_scb_ccr_values SCB_CCR Values
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* @{
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*/
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/* Bits [31:10]: reserved - must be kept cleared */
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/* STKALIGN */
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/** STKALIGN set to zero to break things :) */
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#define SCB_CCR_STKALIGN (1 << 9)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* BFHFNMIGN */
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/** BFHFNMIGN set to attempt ignoring faults in handlers */
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#define SCB_CCR_BFHFNMIGN (1 << 8)
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/* Bits [7:5]: reserved - must be kept cleared */
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/* DIV_0_TRP */
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/** DIV_0_TRP set to trap on divide by zero*/
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#define SCB_CCR_DIV_0_TRP (1 << 4)
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#endif
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/* UNALIGN_TRP */
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/** UNALIGN_TRP set to trap on unaligned */
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#define SCB_CCR_UNALIGN_TRP (1 << 3)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* Bit 2: reserved - must be kept cleared */
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/* USERSETMPEND */
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/** USERSETMPEND set to allow unprivileged access to STIR */
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#define SCB_CCR_USERSETMPEND (1 << 1)
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/* NONBASETHRDENA */
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/** NONBASETHRDENA set to allow non base priority threads */
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#define SCB_CCR_NONBASETHRDENA (1 << 0)
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#endif
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/**@}*/
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/* These numbers are designed to be used with the SCB_SHPR() macro */
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/* SCB_SHPR1 */
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* - a Nested Vectored Interrupt Controller (NVIC)
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* - a Protected Memory System Architecture (PMSA)
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* - system debug.
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* @{
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*/
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/* System Handler Priority 8 bits Registers, SHPR1/2/3 */
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/* Note: 12 8bit Registers */
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/** @defgroup cm_scs_registers SCS Registers
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* @ingroup cm_scs
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* @{
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*/
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/** System Handler Priority 8 bits Registers, SHPR1/2/3.
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* Note: 12 8bit Registers
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*/
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#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))
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/*
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/**
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* Debug Halting Control and Status Register (DHCSR).
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*
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* Purpose Controls halting debug.
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* C1-824.
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* Configurations Always implemented.
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*/
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/* SCS_DHCSR register */
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#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)
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/*
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/**
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* Debug Core Register Selector Register (DCRSR).
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*
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* Purpose With the DCRDR, the DCRSR provides debug access to the ARM core
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@ -75,9 +81,8 @@
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* Configurations Always implemented.
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*
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*/
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/* SCS_DCRS register */
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#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)
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/*
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/**
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* Debug Core Register Data Register (DCRDR)
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*
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* Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR
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* Configurations Always implemented.
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*
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*/
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/* SCS_DCRDR register */
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#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)
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/*
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/**
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* Debug Exception and Monitor Control Register (DEMCR).
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*
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* Purpose Manages vector catch behavior and DebugMonitor handling when
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@ -107,9 +111,10 @@
|
||||
* Configurations Always implemented.
|
||||
*
|
||||
*/
|
||||
/* SCS_DEMCR register */
|
||||
#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)
|
||||
|
||||
/**@}*/
|
||||
|
||||
/* Debug Halting Control and Status Register (DHCSR) */
|
||||
#define SCS_DHCSR_DBGKEY 0xA05F0000
|
||||
#define SCS_DHCSR_C_DEBUGEN 0x00000001
|
||||
|
||||
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Reference in New Issue
Block a user