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As requested (6 Feb 2013) change DMA interrupt flag names

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in STM32/common, for dma_common_f24, to match those used in dma_common_f13.
Examples compile OK
This commit is contained in:
Ken Sarkies 2013-04-26 12:12:03 +09:30
parent 113e5c22e6
commit cbb4756440
2 changed files with 11 additions and 11 deletions
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12
include/libopencm3/stm32/common/dma_common_f24.h
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@ -250,20 +250,20 @@ being at the same relative location */
@{*/ @{*/
/** Transfer Complete Interrupt Flag */ /** Transfer Complete Interrupt Flag */
#define DMA_ISR_TCIF (1 << 5) #define DMA_TCIF (1 << 5)
/** Half Transfer Interrupt Flag */ /** Half Transfer Interrupt Flag */
#define DMA_ISR_HTIF (1 << 4) #define DMA_HTIF (1 << 4)
/** Transfer Error Interrupt Flag */ /** Transfer Error Interrupt Flag */
#define DMA_ISR_TEIF (1 << 3) #define DMA_TEIF (1 << 3)
/** Direct Mode Error Interrupt Flag */ /** Direct Mode Error Interrupt Flag */
#define DMA_ISR_DMEIF (1 << 2) #define DMA_DMEIF (1 << 2)
/** FIFO Error Interrupt Flag */ /** FIFO Error Interrupt Flag */
#define DMA_ISR_FEIF (1 << 0) #define DMA_FEIF (1 << 0)
/**@}*/ /**@}*/
/* Offset within interrupt status register to start of stream interrupt flag field */ /* Offset within interrupt status register to start of stream interrupt flag field */
#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1)) #define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1))
#define DMA_ISR_FLAGS (DMA_ISR_TCIF | DMA_ISR_HTIF | DMA_ISR_TEIF | DMA_ISR_DMEIF | DMA_ISR_FEIF) #define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | DMA_FEIF)
#define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream) #define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)
/* --- DMA_LISR values ----------------------------------------------------- */ /* --- DMA_LISR values ----------------------------------------------------- */

10
lib/stm32/common/dma_common_f24.c
View File

@ -490,7 +490,7 @@ void dma_set_dma_flow_control(u32 dma, u8 stream)
void dma_enable_transfer_error_interrupt(u32 dma, u8 stream) void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
{ {
dma_clear_interrupt_flags(dma, stream, DMA_ISR_TEIF); dma_clear_interrupt_flags(dma, stream, DMA_TEIF);
DMA_SCR(dma, stream) |= DMA_SxCR_TEIE; DMA_SCR(dma, stream) |= DMA_SxCR_TEIE;
} }
@ -515,7 +515,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
void dma_enable_half_transfer_interrupt(u32 dma, u8 stream) void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
{ {
dma_clear_interrupt_flags(dma, stream, DMA_ISR_HTIF); dma_clear_interrupt_flags(dma, stream, DMA_HTIF);
DMA_SCR(dma, stream) |= DMA_SxCR_HTIE; DMA_SCR(dma, stream) |= DMA_SxCR_HTIE;
} }
@ -540,7 +540,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream) void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
{ {
dma_clear_interrupt_flags(dma, stream, DMA_ISR_TCIF); dma_clear_interrupt_flags(dma, stream, DMA_TCIF);
DMA_SCR(dma, stream) |= DMA_SxCR_TCIE; DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
} }
@ -565,7 +565,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream) void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
{ {
dma_clear_interrupt_flags(dma, stream, DMA_ISR_DMEIF); dma_clear_interrupt_flags(dma, stream, DMA_DMEIF);
DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE; DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE;
} }
@ -590,7 +590,7 @@ void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
void dma_enable_fifo_error_interrupt(u32 dma, u8 stream) void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
{ {
dma_clear_interrupt_flags(dma, stream, DMA_ISR_FEIF); dma_clear_interrupt_flags(dma, stream, DMA_FEIF);
DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE; DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE;
} }