diff --git a/include/libopencm3/stm32/common/flash_common_l01.h b/include/libopencm3/stm32/common/flash_common_l01.h new file mode 100644 index 00000000..8827873e --- /dev/null +++ b/include/libopencm3/stm32/common/flash_common_l01.h @@ -0,0 +1,137 @@ +/** @addtogroup flash_defines + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @cond */ +#ifdef LIBOPENCM3_FLASH_H +/** @endcond */ +#ifndef LIBOPENCM3_FLASH_COMMON_L01_H +#define LIBOPENCM3_FLASH_COMMON_L01_H +/**@{*/ + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) +#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c) +#define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) +#define FLASH_WRPR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80) + +/* --- FLASH_ACR values ---------------------------------------------------- */ +#define FLASH_ACR_RUNPD (1 << 4) +#define FLASH_ACR_SLEEPPD (1 << 3) +#define FLASH_ACR_PRFTEN (1 << 1) +/** @defgroup flash_latency FLASH Wait States +@ingroup flash_defines +@{*/ +#define FLASH_ACR_LATENCY_0WS 0x00 +#define FLASH_ACR_LATENCY_1WS 0x01 +/**@}*/ + +/* --- FLASH_PECR values. Program/erase control register */ +#define FLASH_PECR_OBL_LAUNCH (1 << 18) +#define FLASH_PECR_ERRIE (1 << 17) +#define FLASH_PECR_EOPIE (1 << 16) +#define FLASH_PECR_PARALLBANK (1 << 15) +#define FLASH_PECR_FPRG (1 << 10) +#define FLASH_PECR_ERASE (1 << 9) +#define FLASH_PECR_FTDW (1 << 8) +#define FLASH_PECR_DATA (1 << 4) +#define FLASH_PECR_PROG (1 << 3) +#define FLASH_PECR_OPTLOCK (1 << 2) +#define FLASH_PECR_PRGLOCK (1 << 1) +#define FLASH_PECR_PELOCK (1 << 0) + +/* Power down key register (FLASH_PDKEYR) */ +#define FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637) +#define FLASH_PDKEYR_PDKEY2 ((uint32_t)0xFAFBFCFD) + +/* Program/erase key register (FLASH_PEKEYR) */ +#define FLASH_PEKEYR_PEKEY1 ((uint32_t)0x89ABCDEF) +#define FLASH_PEKEYR_PEKEY2 ((uint32_t)0x02030405) + +/* Program memory key register (FLASH_PRGKEYR) */ +#define FLASH_PRGKEYR_PRGKEY1 ((uint32_t)0x8C9DAEBF) +#define FLASH_PRGKEYR_PRGKEY2 ((uint32_t)0x13141516) + +/* Option byte key register (FLASH_OPTKEYR) */ +#define FLASH_OPTKEYR_OPTKEY1 ((uint32_t)0xFBEAD9C8) +#define FLASH_OPTKEYR_OPTKEY2 ((uint32_t)0x24252627) + +/* --- FLASH_SR values ----------------------------------------------------- */ +#define FLASH_SR_OPTVERR (1 << 11) +#define FLASH_SR_SIZEERR (1 << 10) +#define FLASH_SR_PGAERR (1 << 9) +#define FLASH_SR_WRPERR (1 << 8) +#define FLASH_SR_READY (1 << 3) +#define FLASH_SR_ENDHV (1 << 2) +#define FLASH_SR_EOP (1 << 1) +#define FLASH_SR_BSY (1 << 0) + +/* --- FLASH_OBR values ----------------------------------------------------- */ +#define FLASH_OBR_BFB2 (1 << 23) +#define FLASH_OBR_NRST_STDBY (1 << 22) +#define FLASH_OBR_NRST_STOP (1 << 21) +#define FLASH_OBR_IWDG_SW (1 << 20) +#define FLASH_OBR_BOR_OFF (0x0 << 16) +#define FLASH_OBR_BOR_LEVEL_1 (0x8 << 16) +#define FLASH_OBR_BOR_LEVEL_2 (0x9 << 16) +#define FLASH_OBR_BOR_LEVEL_3 (0xa << 16) +#define FLASH_OBR_BOR_LEVEL_4 (0xb << 16) +#define FLASH_OBR_BOR_LEVEL_5 (0xc << 16) +#define FLASH_OBR_RDPRT_LEVEL_0 (0xaa) +#define FLASH_OBR_RDPRT_LEVEL_1 (0x00) +#define FLASH_OBR_RDPRT_LEVEL_2 (0xcc) + +BEGIN_DECLS + +void flash_prefetch_enable(void); +void flash_prefetch_disable(void); +void flash_set_ws(uint32_t ws); +void flash_unlock_pecr(void); +void flash_lock_pecr(void); +void flash_unlock_progmem(void); +void flash_lock_progmem(void); +void flash_unlock_option_bytes(void); +void flash_lock_option_bytes(void); +void flash_unlock(void); +void flash_lock(void); + +void eeprom_program_word(uint32_t address, uint32_t data); +void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#error "flash_common_l01.h should not be included directly, only via flash.h" +#endif +/** @endcond */ + diff --git a/include/libopencm3/stm32/l1/flash.h b/include/libopencm3/stm32/l1/flash.h index 680de5cc..10afcd81 100644 --- a/include/libopencm3/stm32/l1/flash.h +++ b/include/libopencm3/stm32/l1/flash.h @@ -44,90 +44,16 @@ #define LIBOPENCM3_FLASH_H /**@{*/ -/* --- FLASH registers ----------------------------------------------------- */ +#include -#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) -#define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) -#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) -#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) -#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) -#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) -#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) -#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c) -#define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) -#define FLASH_WRPR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80) +/* --- FLASH registers ----------------------------------------------------- */ #define FLASH_WRPR3 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x84) /* --- FLASH_ACR values ---------------------------------------------------- */ - -#define FLASH_ACR_RUNPD (1 << 4) -#define FLASH_ACR_SLEEPPD (1 << 3) #define FLASH_ACR_ACC64 (1 << 2) -#define FLASH_ACR_PRFTEN (1 << 1) -/** @defgroup flash_latency FLASH Wait States -@ingroup flash_defines -@{*/ -#define FLASH_ACR_LATENCY_0WS 0x00 -#define FLASH_ACR_LATENCY_1WS 0x01 -/**@}*/ - -/* --- FLASH_PECR values. Program/erase control register */ -#define FLASH_PECR_OBL_LAUNCH (1 << 18) -#define FLASH_PECR_ERRIE (1 << 17) -#define FLASH_PECR_EOPIE (1 << 16) -#define FLASH_PECR_PARALLBANK (1 << 15) -#define FLASH_PECR_FPRG (1 << 10) -#define FLASH_PECR_ERASE (1 << 9) -#define FLASH_PECR_FTDW (1 << 8) -#define FLASH_PECR_FTDW (1 << 8) -#define FLASH_PECR_DATA (1 << 4) -#define FLASH_PECR_PROG (1 << 3) -#define FLASH_PECR_OPTLOCK (1 << 2) -#define FLASH_PECR_PRGLOCK (1 << 1) -#define FLASH_PECR_PELOCK (1 << 0) - -/* Power down key register (FLASH_PDKEYR) */ -#define FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637) -#define FLASH_PDKEYR_PDKEY2 ((uint32_t)0xFAFBFCFD) - -/* Program/erase key register (FLASH_PEKEYR) */ -#define FLASH_PEKEYR_PEKEY1 ((uint32_t)0x89ABCDEF) -#define FLASH_PEKEYR_PEKEY2 ((uint32_t)0x02030405) - -/* Program memory key register (FLASH_PRGKEYR) */ -#define FLASH_PRGKEYR_PRGKEY1 ((uint32_t)0x8C9DAEBF) -#define FLASH_PRGKEYR_PRGKEY2 ((uint32_t)0x13141516) - -/* Option byte key register (FLASH_OPTKEYR) */ -#define FLASH_OPTKEYR_OPTKEY1 ((uint32_t)0xFBEAD9C8) -#define FLASH_OPTKEYR_OPTKEY2 ((uint32_t)0x24252627) - /* --- FLASH_SR values ----------------------------------------------------- */ #define FLASH_SR_OPTVERRUSR (1 << 12) -#define FLASH_SR_OPTVERR (1 << 11) -#define FLASH_SR_SIZEERR (1 << 10) -#define FLASH_SR_PGAERR (1 << 9) -#define FLASH_SR_WRPERR (1 << 8) -#define FLASH_SR_READY (1 << 3) -#define FLASH_SR_ENDHV (1 << 2) -#define FLASH_SR_EOP (1 << 1) -#define FLASH_SR_BSY (1 << 0) - -/* --- FLASH_OBR values ----------------------------------------------------- */ -#define FLASH_OBR_BFB2 (1 << 23) -#define FLASH_OBR_NRST_STDBY (1 << 22) -#define FLASH_OBR_NRST_STOP (1 << 21) -#define FLASH_OBR_IWDG_SW (1 << 20) -#define FLASH_OBR_BOR_OFF (0x0 << 16) -#define FLASH_OBR_BOR_LEVEL_1 (0x8 << 16) -#define FLASH_OBR_BOR_LEVEL_2 (0x9 << 16) -#define FLASH_OBR_BOR_LEVEL_3 (0xa << 16) -#define FLASH_OBR_BOR_LEVEL_4 (0xb << 16) -#define FLASH_OBR_BOR_LEVEL_5 (0xc << 16) -#define FLASH_OBR_RDPRT_LEVEL_0 (0xaa) -#define FLASH_OBR_RDPRT_LEVEL_1 (0x00) -#define FLASH_OBR_RDPRT_LEVEL_2 (0xcc) /* --- Function prototypes ------------------------------------------------- */ @@ -135,20 +61,6 @@ BEGIN_DECLS void flash_64bit_enable(void); void flash_64bit_disable(void); -void flash_prefetch_enable(void); -void flash_prefetch_disable(void); -void flash_set_ws(uint32_t ws); -void flash_unlock_pecr(void); -void flash_lock_pecr(void); -void flash_unlock_progmem(void); -void flash_lock_progmem(void); -void flash_unlock_option_bytes(void); -void flash_lock_option_bytes(void); -void flash_unlock(void); -void flash_lock(void); - -void eeprom_program_word(uint32_t address, uint32_t data); -void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words); END_DECLS /**@}*/ diff --git a/lib/stm32/common/flash_common_l01.c b/lib/stm32/common/flash_common_l01.c new file mode 100644 index 00000000..48b99f14 --- /dev/null +++ b/lib/stm32/common/flash_common_l01.c @@ -0,0 +1,191 @@ +/** @addtogroup flash_file + * + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * Copyright (C) 2012-13 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Flash routines shared by L0/L1. L4 has a different flash controller */ + +/**@{*/ + +#include + +/*---------------------------------------------------------------------------*/ +/** @brief Enable the FLASH Prefetch Buffer + +This buffer is used for instruction fetches and is enabled by default after +reset. + +Note carefully the restrictions under which the prefetch buffer may be +enabled or disabled. Prefetch is only available when 64-bit +access is enabled. +*/ + +void flash_prefetch_enable(void) +{ + FLASH_ACR |= FLASH_ACR_PRFTEN; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Disable the FLASH Prefetch Buffer + +Note carefully the restrictions under which the prefetch buffer may be +set to disabled. See the reference and programming manuals for details. +*/ + +void flash_prefetch_disable(void) +{ + FLASH_ACR &= ~FLASH_ACR_PRFTEN; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the Number of Wait States + +Used to match the system clock to the FLASH memory access time. See the +programming manual for more information on clock speed and voltage ranges. The +latency must be changed to the appropriate value before any increase in +clock speed, or after any decrease in clock speed. A latency setting of +zero only applies if 64-bit mode is not used. + +@param[in] ws values from @ref flash_latency. +*/ + +void flash_set_ws(uint32_t ws) +{ + uint32_t reg32; + + reg32 = FLASH_ACR; + reg32 &= ~(1 << 0); + reg32 |= ws; + FLASH_ACR = reg32; +} + +/** + * Unlock primary access to the flash control/erase block + * You must call this before using any of the low level routines + * yourself. + * @sa flash_unlock + */ +void flash_unlock_pecr(void) +{ + FLASH_PEKEYR = FLASH_PEKEYR_PEKEY1; + FLASH_PEKEYR = FLASH_PEKEYR_PEKEY2; +} + +void flash_lock_pecr(void) +{ + FLASH_PECR |= FLASH_PECR_PELOCK; +} + +/** + * Unlock program memory itself. + * Writes the magic sequence to unlock the program memory + * you must have already unlocked access to this register! + * @sa flash_unlock_pecr + */ +void flash_unlock_progmem(void) +{ + FLASH_PRGKEYR = FLASH_PRGKEYR_PRGKEY1; + FLASH_PRGKEYR = FLASH_PRGKEYR_PRGKEY2; +} + +void flash_lock_progmem(void) +{ + FLASH_PECR |= FLASH_PECR_PRGLOCK; +} + +/** + * Unlock option bytes. + * Writes the magic sequence to unlock the option bytes, + * you must have already unlocked access to this register! + * @sa flash_unlock_pecr + */ +void flash_unlock_option_bytes(void) +{ + FLASH_OPTKEYR = FLASH_OPTKEYR_OPTKEY1; + FLASH_OPTKEYR = FLASH_OPTKEYR_OPTKEY2; +} + +void flash_lock_option_bytes(void) +{ + FLASH_PECR |= FLASH_PECR_OPTLOCK; +} + +/** @brief Unlock all segments of flash + * + */ +void flash_unlock(void) +{ + flash_unlock_pecr(); + flash_unlock_progmem(); + flash_unlock_option_bytes(); +} + +/** @brief Lock all segments of flash + * + */ +void flash_lock(void) +{ + flash_lock_option_bytes(); + flash_lock_progmem(); + flash_lock_pecr(); +} + +/** @brief Write a word to eeprom + * + * @param address assumed to be in the eeprom space, no checking + * @param data word to write + */ +void eeprom_program_word(uint32_t address, uint32_t data) +{ + flash_unlock_pecr(); + /* erase only if needed */ + FLASH_PECR &= ~FLASH_PECR_FTDW; + MMIO32(address) = data; + flash_lock_pecr(); +} + +/** @brief Write a block of words to eeprom + * + * Writes a block of words to EEPROM at the requested address, erasing if + * necessary, and locking afterwards. Only wordwise writing is safe for + * writing any value + * + * @param[in] address must point to EEPROM space, no checking! + * @param[in] data pointer to data to write + * @param[in] length_in_words size of of data in WORDS! + */ +void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words) +{ + int i; + flash_unlock_pecr(); + while (FLASH_SR & FLASH_SR_BSY); + /* erase only if needed */ + FLASH_PECR &= ~FLASH_PECR_FTDW; + for (i = 0; i < length_in_words; i++) { + MMIO32(address + (i * sizeof(uint32_t))) = *(data+i); + while (FLASH_SR & FLASH_SR_BSY); + } + flash_lock_pecr(); +} + +/**@}*/ diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index 630d216b..3ca80605 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -38,6 +38,7 @@ ARFLAGS = rcs OBJS = crc.o desig.o flash.o rcc.o usart.o dma.o lcd.o OBJS += crc_common_all.o dac_common_all.o OBJS += dma_common_l1f013.o +OBJS += flash_common_l01.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v1.o iwdg_common_all.o OBJS += pwr_common_v1.o pwr_common_v2.o rtc_common_l1f024.o diff --git a/lib/stm32/l1/flash.c b/lib/stm32/l1/flash.c index a6beba8a..5e176b05 100644 --- a/lib/stm32/l1/flash.c +++ b/lib/stm32/l1/flash.c @@ -71,164 +71,4 @@ void flash_64bit_disable(void) FLASH_ACR &= ~FLASH_ACR_ACC64; } -/*---------------------------------------------------------------------------*/ -/** @brief Enable the FLASH Prefetch Buffer - -This buffer is used for instruction fetches and is enabled by default after -reset. - -Note carefully the restrictions under which the prefetch buffer may be -enabled or disabled. Prefetch is only available when 64-bit -access is enabled. -*/ - -void flash_prefetch_enable(void) -{ - FLASH_ACR |= FLASH_ACR_PRFTEN; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Disable the FLASH Prefetch Buffer - -Note carefully the restrictions under which the prefetch buffer may be -set to disabled. See the reference and programming manuals for details. -*/ - -void flash_prefetch_disable(void) -{ - FLASH_ACR &= ~FLASH_ACR_PRFTEN; -} - -/*---------------------------------------------------------------------------*/ -/** @brief Set the Number of Wait States - -Used to match the system clock to the FLASH memory access time. See the -programming manual for more information on clock speed and voltage ranges. The -latency must be changed to the appropriate value before any increase in -clock speed, or after any decrease in clock speed. A latency setting of -zero only applies if 64-bit mode is not used. - -@param[in] ws values from @ref flash_latency. -*/ - -void flash_set_ws(uint32_t ws) -{ - uint32_t reg32; - - reg32 = FLASH_ACR; - reg32 &= ~(1 << 0); - reg32 |= ws; - FLASH_ACR = reg32; -} - -/** - * Unlock primary access to the flash control/erase block - * You must call this before using any of the low level routines - * yourself. - * @sa flash_unlock - */ -void flash_unlock_pecr(void) -{ - FLASH_PEKEYR = FLASH_PEKEYR_PEKEY1; - FLASH_PEKEYR = FLASH_PEKEYR_PEKEY2; -} - -void flash_lock_pecr(void) -{ - FLASH_PECR |= FLASH_PECR_PELOCK; -} - -/** - * Unlock program memory itself. - * Writes the magic sequence to unlock the program memory - * you must have already unlocked access to this register! - * @sa flash_unlock_pecr - */ -void flash_unlock_progmem(void) -{ - FLASH_PRGKEYR = FLASH_PRGKEYR_PRGKEY1; - FLASH_PRGKEYR = FLASH_PRGKEYR_PRGKEY2; -} - -void flash_lock_progmem(void) -{ - FLASH_PECR |= FLASH_PECR_PRGLOCK; -} - -/** - * Unlock option bytes. - * Writes the magic sequence to unlock the option bytes, - * you must have already unlocked access to this register! - * @sa flash_unlock_pecr - */ -void flash_unlock_option_bytes(void) -{ - FLASH_OPTKEYR = FLASH_OPTKEYR_OPTKEY1; - FLASH_OPTKEYR = FLASH_OPTKEYR_OPTKEY2; -} - -void flash_lock_option_bytes(void) -{ - FLASH_PECR |= FLASH_PECR_OPTLOCK; -} - -/** @brief Unlock all segments of flash - * - */ -void flash_unlock(void) -{ - flash_unlock_pecr(); - flash_unlock_progmem(); - flash_unlock_option_bytes(); -} - -/** @brief Lock all segments of flash - * - */ -void flash_lock(void) -{ - flash_lock_option_bytes(); - flash_lock_progmem(); - flash_lock_pecr(); -} - -/** @brief Write a word to eeprom - * - * @param address assumed to be in the eeprom space, no checking - * @param data word to write - */ -void eeprom_program_word(uint32_t address, uint32_t data) -{ - flash_unlock_pecr(); - /* erase only if needed */ - FLASH_PECR &= ~FLASH_PECR_FTDW; - MMIO32(address) = data; - flash_lock_pecr(); -} - -/** @brief Write a block of words to eeprom - * - * Writes a block of words to EEPROM at the requested address, erasing if - * necessary, and locking afterwards. Only wordwise writing is safe for - * writing any value - * - * @param[in] address must point to EEPROM space, no checking! - * @param[in] data pointer to data to write - * @param[in] length_in_words size of of data in WORDS! - */ -void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words) -{ - int i; - flash_unlock_pecr(); - while (FLASH_SR & FLASH_SR_BSY); - /* erase only if needed */ - FLASH_PECR &= ~FLASH_PECR_FTDW; - for (i = 0; i < length_in_words; i++) { - MMIO32(address + (i * sizeof(uint32_t))) = *(data+i); - while (FLASH_SR & FLASH_SR_BSY); - } - flash_lock_pecr(); -} - - /**@}*/