diff --git a/include/libopencm3/stm32/l0/rcc.h b/include/libopencm3/stm32/l0/rcc.h
index 0ca3a617..2ffbadf9 100644
--- a/include/libopencm3/stm32/l0/rcc.h
+++ b/include/libopencm3/stm32/l0/rcc.h
@@ -168,41 +168,51 @@
 #define RCC_CFGR_STOPWUCK_HSI16		(1<<15)
 
 /* PPRE2: APB high-speed prescaler (APB2) */
-#define RCC_CFGR_PPRE2_HCLK_NODIV		0x0
-#define RCC_CFGR_PPRE2_HCLK_DIV2		0x4
-#define RCC_CFGR_PPRE2_HCLK_DIV4		0x5
-#define RCC_CFGR_PPRE2_HCLK_DIV8		0x6
-#define RCC_CFGR_PPRE2_HCLK_DIV16		0x7
+#define RCC_CFGR_PPRE2_NODIV		0x0
+#define RCC_CFGR_PPRE2_DIV2		0x4
+#define RCC_CFGR_PPRE2_DIV4		0x5
+#define RCC_CFGR_PPRE2_DIV8		0x6
+#define RCC_CFGR_PPRE2_DIV16		0x7
+#define RCC_CFGR_PPRE2_MASK		0x7
+#define RCC_CFGR_PPRE2_SHIFT		11
 
 /* PPRE1: APB low-speed prescaler (APB1) */
-#define RCC_CFGR_PPRE1_HCLK_NODIV		0x0
-#define RCC_CFGR_PPRE1_HCLK_DIV2		0x4
-#define RCC_CFGR_PPRE1_HCLK_DIV4		0x5
-#define RCC_CFGR_PPRE1_HCLK_DIV8		0x6
-#define RCC_CFGR_PPRE1_HCLK_DIV16		0x7
+#define RCC_CFGR_PPRE1_NODIV		0x0
+#define RCC_CFGR_PPRE1_DIV2		0x4
+#define RCC_CFGR_PPRE1_DIV4		0x5
+#define RCC_CFGR_PPRE1_DIV8		0x6
+#define RCC_CFGR_PPRE1_DIV16		0x7
+#define RCC_CFGR_PPRE1_MASK		0x7
+#define RCC_CFGR_PPRE1_SHIFT		8
 
 /* HPRE: AHB prescaler */
-#define RCC_CFGR_HPRE_SYSCLK_NODIV		0x0
-#define RCC_CFGR_HPRE_SYSCLK_DIV2		0x8
-#define RCC_CFGR_HPRE_SYSCLK_DIV4		0x9
-#define RCC_CFGR_HPRE_SYSCLK_DIV8		0xa
-#define RCC_CFGR_HPRE_SYSCLK_DIV16		0xb
-#define RCC_CFGR_HPRE_SYSCLK_DIV64		0xc
-#define RCC_CFGR_HPRE_SYSCLK_DIV128		0xd
-#define RCC_CFGR_HPRE_SYSCLK_DIV256		0xe
-#define RCC_CFGR_HPRE_SYSCLK_DIV512		0xf
+#define RCC_CFGR_HPRE_NODIV		0x0
+#define RCC_CFGR_HPRE_DIV2		0x8
+#define RCC_CFGR_HPRE_DIV4		0x9
+#define RCC_CFGR_HPRE_DIV8		0xa
+#define RCC_CFGR_HPRE_DIV16		0xb
+#define RCC_CFGR_HPRE_DIV64		0xc
+#define RCC_CFGR_HPRE_DIV128		0xd
+#define RCC_CFGR_HPRE_DIV256		0xe
+#define RCC_CFGR_HPRE_DIV512		0xf
+#define RCC_CFGR_HPRE_MASK		0xf
+#define RCC_CFGR_HPRE_SHIFT		4
 
 /* SWS: System clock switch status */
-#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK		0x0
-#define RCC_CFGR_SWS_SYSCLKSEL_HSI16CLK		0x1
-#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK		0x2
-#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK		0x3
+#define RCC_CFGR_SWS_MSI			0x0
+#define RCC_CFGR_SWS_HSI16			0x1
+#define RCC_CFGR_SWS_HSE			0x2
+#define RCC_CFGR_SWS_PLL			0x3
+#define RCC_CFGR_SWS_MASK			0x3
+#define RCC_CFGR_SWS_SHIFT			2
 
 /* SW: System clock switch */
-#define RCC_CFGR_SW_SYSCLKSEL_MSICLK		0x0
-#define RCC_CFGR_SW_SYSCLKSEL_HSI16CLK		0x1
-#define RCC_CFGR_SW_SYSCLKSEL_HSECLK		0x2
-#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK		0x3
+#define RCC_CFGR_SW_MSI				0x0
+#define RCC_CFGR_SW_HSI16			0x1
+#define RCC_CFGR_SW_HSE				0x2
+#define RCC_CFGR_SW_PLL				0x3
+#define RCC_CFGR_SW_MASK			0x3
+#define RCC_CFGR_SW_SHIFT			0
 
 /* --- RCC_CIER - Clock interrupt enable register */