diff --git a/include/libopencm3/stm32/common/spi_common_f03.h b/include/libopencm3/stm32/common/spi_common_f03.h index 6e1984c2..69813d87 100644 --- a/include/libopencm3/stm32/common/spi_common_f03.h +++ b/include/libopencm3/stm32/common/spi_common_f03.h @@ -37,6 +37,11 @@ * applicable to the STM32F0/F3 series of devices */ +#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) +#define SPI1_DR8 SPI_DR8(SPI1_BASE) +#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE) +#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE) + /* DFF: Data frame format */ /****************************************************************************/ /** @defgroup spi_dff SPI data frame format @@ -98,6 +103,8 @@ BEGIN_DECLS +void spi_set_crcl_8bit(uint32_t spi); +void spi_set_crcl_16bit(uint32_t spi); void spi_set_data_size(uint32_t spi, uint16_t data_s); void spi_fifo_reception_threshold_8bit(uint32_t spi); void spi_fifo_reception_threshold_16bit(uint32_t spi); diff --git a/include/libopencm3/stm32/f3/spi.h b/include/libopencm3/stm32/f3/spi.h index dd8668e2..5abbb970 100644 --- a/include/libopencm3/stm32/f3/spi.h +++ b/include/libopencm3/stm32/f3/spi.h @@ -34,9 +34,4 @@ #include #include -#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) -#define SPI1_DR8 SPI_DR8(SPI1_BASE) -#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE) -#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE) - #endif diff --git a/lib/stm32/common/spi_common_f03.c b/lib/stm32/common/spi_common_f03.c new file mode 100644 index 00000000..5713653a --- /dev/null +++ b/lib/stm32/common/spi_common_f03.c @@ -0,0 +1,177 @@ +/** @addtogroup spi_file + +@author @htmlonly © @endhtmlonly 2009 +Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies + +Devices can have up to three SPI peripherals. The common 4-wire full-duplex +mode of operation is supported, along with 3-wire variants using unidirectional +communication modes or half-duplex bidirectional communication. A variety of +options allows many of the SPI variants to be supported. Multimaster operation +is also supported. A CRC can be generated and checked in hardware. + +@note Some JTAG pins need to be remapped if SPI is to be used. + +@note The I2S protocol shares the SPI hardware so the two protocols cannot be +used at the same time on the same peripheral. + +Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words, +LSB first. +@code + spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_CRCL_8BIT, + SPI_CR1_LSBFIRST); + spi_write(SPI1, 0x55); // 8-bit write + spi_write(SPI1, 0xaa88); // 16-bit write + reg8 = spi_read(SPI1); // 8-bit read + reg16 = spi_read(SPI1); // 16-bit read +@endcode + +@todo need additional functions to aid ISRs in retrieving status + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +/* + * SPI and I2S code. + * + * Examples: + * spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, + * SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_CRCL_8BIT, + * SPI_CR1_LSBFIRST); + * spi_write(SPI1, 0x55); // 8-bit write + * spi_write(SPI1, 0xaa88); // 16-bit write + * reg8 = spi_read(SPI1); // 8-bit read + * reg16 = spi_read(SPI1); // 16-bit read + */ + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief Configure the SPI as Master. + +The SPI peripheral is configured as a master with communication parameters +baudrate, crc length 8/16 bits, frame format lsb/msb first, clock polarity +and phase. The SPI enable, CRC enable and CRC next controls are not affected. +These must be controlled separately. + +@todo NSS pin handling. + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] br Unsigned int32. Baudrate @ref spi_baudrate. +@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol. +@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha. +@param[in] crcl Unsigned int32. CRC length 8/16 bits @ref spi_crcl. +@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref +spi_lsbfirst. +@returns int. Error code. +*/ + +int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, + uint32_t crcl, uint32_t lsbfirst) +{ + uint32_t reg32 = SPI_CR1(spi); + + /* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */ + reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT; + + reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */ + + reg32 |= br; /* Set baud rate bits. */ + reg32 |= cpol; /* Set CPOL value. */ + reg32 |= cpha; /* Set CPHA value. */ + reg32 |= crcl; /* Set crc length (8 or 16 bits). */ + reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */ + + /* TODO: NSS pin handling. */ + + SPI_CR1(spi) = reg32; + + return 0; /* TODO */ +} + +void spi_send8(uint32_t spi, uint8_t data) +{ + /* Wait for transfer finished. */ + while (!(SPI_SR(spi) & SPI_SR_TXE)); + + /* Write data (8 or 16 bits, depending on DFF) into DR. */ + SPI_DR8(spi) = data; +} + +uint8_t spi_read8(uint32_t spi) +{ + /* Wait for transfer finished. */ + while (!(SPI_SR(spi) & SPI_SR_RXNE)); + + /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ + return SPI_DR8(spi); +} + +/*---------------------------------------------------------------------------*/ +/** @brief SPI Set CRC length to 8 bits + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_crcl_8bit(uint32_t spi) +{ + SPI_CR1(spi) &= ~SPI_CR1_CRCL; +} + +/*---------------------------------------------------------------------------*/ +/** @brief SPI Set CRC length to 16 bits + +@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +*/ + +void spi_set_crcl_16bit(uint32_t spi) +{ + SPI_CR1(spi) |= SPI_CR1_CRCL; +} + +void spi_set_data_size(uint32_t spi, uint16_t data_s) +{ + SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) | + (data_s & SPI_CR2_DS_MASK); +} + +void spi_fifo_reception_threshold_8bit(uint32_t spi) +{ + SPI_CR2(spi) |= SPI_CR2_FRXTH; +} + +void spi_fifo_reception_threshold_16bit(uint32_t spi) +{ + SPI_CR2(spi) &= ~SPI_CR2_FRXTH; +} + +void spi_i2s_mode_spi_mode(uint32_t spi) +{ + SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD; +} + + +/**@}*/ diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index 84d36ea3..62f4a31e 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -33,12 +33,13 @@ CFLAGS = -Os -g \ ARFLAGS = rcs -OBJS = flash.o rcc.o usart.o dma.o rtc.o comparator.o spi.o crc.o \ +OBJS = flash.o rcc.o usart.o dma.o rtc.o comparator.o crc.o \ dac.o i2c.o iwdg.o pwr.o gpio.o timer.o adc.o OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o \ pwr_common_all.o iwdg_common_all.o rtc_common_l1f024.o \ - dma_common_l1f013.o exti_common_all.o spi_common_all.o + dma_common_l1f013.o exti_common_all.o spi_common_all.o \ + spi_common_f03.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f0/spi.c b/lib/stm32/f0/spi.c deleted file mode 100644 index 3546769d..00000000 --- a/lib/stm32/f0/spi.c +++ /dev/null @@ -1,54 +0,0 @@ -/** @defgroup spi_file SPI - * - * @ingroup STM32F0xx - * - * @brief libopencm3 STM32F0xx Serial Peripheral Interface - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -void spi_set_data_size(uint32_t spi, uint16_t data_s) -{ - SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) | - (data_s & SPI_CR2_DS_MASK); -} - -void spi_fifo_reception_threshold_8bit(uint32_t spi) -{ - SPI_CR2(spi) |= SPI_CR2_FRXTH; -} - -void spi_fifo_reception_threshold_16bit(uint32_t spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_FRXTH; -} - -void spi_i2s_mode_spi_mode(uint32_t spi) -{ - SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD; -} diff --git a/lib/stm32/f3/Makefile b/lib/stm32/f3/Makefile index adf8623d..3ec6ab61 100644 --- a/lib/stm32/f3/Makefile +++ b/lib/stm32/f3/Makefile @@ -34,13 +34,13 @@ CFLAGS = -Os -g \ ARFLAGS = rcs -OBJS = rcc.o gpio.o adc.o i2c.o spi.o usart.o dma.o flash.o +OBJS = rcc.o gpio.o adc.o i2c.o usart.o dma.o flash.o OBJS += gpio_common_all.o gpio_common_f0234.o \ dac_common_all.o usart_common_all.o crc_common_all.o\ iwdg_common_all.o spi_common_all.o dma_common_l1f013.o\ timer_common_all.o timer_common_f234.o flash_common_f234.o \ - flash.o exti_common_all.o rcc_common_all.o + flash.o exti_common_all.o rcc_common_all.o spi_common_f03.o OBJS += usb.o usb_control.o usb_standard.o usb_f103.o diff --git a/lib/stm32/f3/spi.c b/lib/stm32/f3/spi.c deleted file mode 100644 index b33411db..00000000 --- a/lib/stm32/f3/spi.c +++ /dev/null @@ -1,72 +0,0 @@ -/** @defgroup spi_file SPI - * - * @ingroup STM32F3xx - * - * @brief libopencm3 STM32F3xx Serial Peripheral Interface - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2009 Uwe Hermann - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see . - */ - -#include -#include - -void spi_send8(uint32_t spi, uint8_t data) -{ - /* Wait for transfer finished. */ - while (!(SPI_SR(spi) & SPI_SR_TXE)); - - /* Write data (8 or 16 bits, depending on DFF) into DR. */ - SPI_DR8(spi) = data; -} - -uint8_t spi_read8(uint32_t spi) -{ - /* Wait for transfer finished. */ - while (!(SPI_SR(spi) & SPI_SR_RXNE)); - - /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ - return SPI_DR8(spi); -} - -void spi_set_data_size(uint32_t spi, uint16_t data_s) -{ - SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) | - (data_s & SPI_CR2_DS_MASK); -} - -void spi_fifo_reception_threshold_8bit(uint32_t spi) -{ - SPI_CR2(spi) |= SPI_CR2_FRXTH; -} - -void spi_fifo_reception_threshold_16bit(uint32_t spi) -{ - SPI_CR2(spi) &= ~SPI_CR2_FRXTH; -} - -void spi_i2s_mode_spi_mode(uint32_t spi) -{ - SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD; -}