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stm32: rcc_wait_for_sysclk_status should actually wait

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Original implementation only checked whether the user had _selected_ the
clock, not whether it had actually switched to the clock or not.  For
almost all cases, this made this function either a no-op, if you _had_
selected the clock, or a blocking loop if you hadn't selected it ahead
of time.

Fixes github issue #687
This commit is contained in:
Karl Palsson 2016-08-15 16:09:58 +00:00
parent 781e4d94ba
commit cf7d0a08ca
8 changed files with 31 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
include/libopencm3/stm32/f2/rcc.h
View File

@ -165,6 +165,7 @@
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SHIFT 2
#define RCC_CFGR_SWS_MASK 0x3
#define RCC_CFGR_SWS_HSI 0x0
#define RCC_CFGR_SWS_HSE 0x1
#define RCC_CFGR_SWS_PLL 0x2

1
include/libopencm3/stm32/f3/rcc.h
View File

@ -159,6 +159,7 @@
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SHIFT 2
#define RCC_CFGR_SWS_MASK 0x3
#define RCC_CFGR_SWS_HSI 0x0
#define RCC_CFGR_SWS_HSE 0x1
#define RCC_CFGR_SWS_PLL 0x2

1
include/libopencm3/stm32/f4/rcc.h
View File

@ -174,6 +174,7 @@
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SHIFT 2
#define RCC_CFGR_SWS_MASK 0x3
#define RCC_CFGR_SWS_HSI 0x0
#define RCC_CFGR_SWS_HSE 0x1
#define RCC_CFGR_SWS_PLL 0x2

2
include/libopencm3/stm32/l1/rcc.h
View File

@ -188,6 +188,8 @@
#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1
#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2
#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3
#define RCC_CFGR_SWS_MASK 0x3
#define RCC_CFGR_SWS_SHIFT 2
/* SW: System clock switch */
#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0

9
lib/stm32/f2/rcc.c
View File

@ -185,13 +185,16 @@ void rcc_wait_for_sysclk_status(osc_t osc)
{
switch (osc) {
case RCC_PLL:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL);
break;
case RCC_HSE:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_HSE);
break;
case RCC_HSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_HSI);
break;
default:
/* Shouldn't be reached. */

9
lib/stm32/f3/rcc.c
View File

@ -223,13 +223,16 @@ void rcc_wait_for_sysclk_status(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL);
break;
case RCC_HSE:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_HSE);
break;
case RCC_HSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_HSI);
break;
default:
/* Shouldn't be reached. */

9
lib/stm32/f4/rcc.c
View File

@ -414,13 +414,16 @@ void rcc_wait_for_sysclk_status(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL);
break;
case RCC_HSE:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_HSE);
break;
case RCC_HSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_HSI);
break;
default:
/* Shouldn't be reached. */

16
lib/stm32/l1/rcc.c
View File

@ -256,20 +256,20 @@ void rcc_wait_for_sysclk_status(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
RCC_CFGR_SWS_SYSCLKSEL_PLLCLK);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_SYSCLKSEL_PLLCLK);
break;
case RCC_HSE:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
RCC_CFGR_SWS_SYSCLKSEL_HSECLK);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_SYSCLKSEL_HSECLK);
break;
case RCC_HSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
RCC_CFGR_SWS_SYSCLKSEL_HSICLK);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_SYSCLKSEL_HSICLK);
break;
case RCC_MSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) !=
RCC_CFGR_SWS_SYSCLKSEL_MSICLK);
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_SYSCLKSEL_MSICLK);
break;
default:
/* Shouldn't be reached. */