From d144f9d54b66d07c56873d6f3507250a08a79184 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 9 Oct 2021 13:12:10 +0200 Subject: [PATCH] adiv5: CMSIS DAP transactions are slow but work in principle Slowness results in strange STM32F767 DHCSR implementation to nearly never halt in the given 2 second period when F767 is sleeping most of the time. --- src/target/adiv5.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/target/adiv5.c b/src/target/adiv5.c index 429d6125..a257175a 100644 --- a/src/target/adiv5.c +++ b/src/target/adiv5.c @@ -323,12 +323,7 @@ static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap) CORTEXM_DHCSR_C_HALT; uint32_t dhcsr_valid = CORTEXM_DHCSR_S_HALT | CORTEXM_DHCSR_C_DEBUGEN; bool reset_seen = false; - bool is_mindp = (ap->dp->idcode & ADIV5_MINDP); -#if PC_HOSTED == 1 - bool use_low_access = (!(ap->dp->ap_setup) && !is_mindp); -#else - bool use_low_access = (!is_mindp); -#endif + bool use_low_access = (!(ap->dp->idcode & ADIV5_MINDP)); if (use_low_access) { /* ap_mem_access_setup() sets ADIV5_AP_CSW_ADDRINC_SINGLE -> unusable!*/ adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD);