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stm32:f1:RTC: Replace direct register access with API calls

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Some additional functions added to rcc to support the rtc.
This commit is contained in:
Ken Sarkies 2014-02-19 14:35:59 +10:30 committed by Karl Palsson
parent 957c5233f4
commit d316bbca39
3 changed files with 92 additions and 52 deletions
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3
include/libopencm3/stm32/f1/rcc.h
View File

@ -697,6 +697,9 @@ void rcc_set_pll2_multiplication_factor(uint32_t mul);
void rcc_set_pll3_multiplication_factor(uint32_t mul);
void rcc_set_pll_source(uint32_t pllsrc);
void rcc_set_pllxtpre(uint32_t pllxtpre);
uint32_t rcc_rtc_clock_enabled_flag(void);
void rcc_enable_rtc_clock(void);
void rcc_set_rtc_clock_source(enum rcc_osc clock_source);
void rcc_set_adcpre(uint32_t adcpre);
void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1);

75
lib/stm32/f1/rcc.c
View File

@ -501,6 +501,76 @@ void rcc_set_pllxtpre(uint32_t pllxtpre)
(pllxtpre << 17);
}
/*---------------------------------------------------------------------------*/
/** @brief RCC RTC Clock Enabled Flag
@returns uint32_t. Nonzero if the RTC Clock is enabled.
*/
uint32_t rcc_rtc_clock_enabled_flag(void)
{
return RCC_BDCR & RCC_BDCR_RTCEN;
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Enable the RTC clock
*/
void rcc_enable_rtc_clock(void)
{
RCC_BDCR |= RCC_BDCR_RTCEN;
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the Source for the RTC clock
@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/128, LSE and LSI.
*/
void rcc_set_rtc_clock_source(enum rcc_osc clock_source)
{
uint32_t reg32;
switch (clock_source) {
case LSE:
/* Turn the LSE on and wait while it stabilises. */
RCC_BDCR |= RCC_BDCR_LSEON;
while ((reg32 = (RCC_BDCR & RCC_BDCR_LSERDY)) == 0);
/* Choose LSE as the RTC clock source. */
RCC_BDCR &= ~((1 << 8) | (1 << 9));
RCC_BDCR |= (1 << 8);
break;
case LSI:
/* Turn the LSI on and wait while it stabilises. */
RCC_CSR |= RCC_CSR_LSION;
while ((reg32 = (RCC_CSR & RCC_CSR_LSIRDY)) == 0);
/* Choose LSI as the RTC clock source. */
RCC_BDCR &= ~((1 << 8) | (1 << 9));
RCC_BDCR |= (1 << 9);
break;
case HSE:
/* Turn the HSE on and wait while it stabilises. */
RCC_CR |= RCC_CR_HSEON;
while ((reg32 = (RCC_CR & RCC_CR_HSERDY)) == 0);
/* Choose HSE as the RTC clock source. */
RCC_BDCR &= ~((1 << 8) | (1 << 9));
RCC_BDCR |= (1 << 9) | (1 << 8);
break;
case PLL:
case PLL2:
case PLL3:
case HSI:
/* Unusable clock source, here to prevent warnings. */
/* Turn off clock sources to RTC. */
RCC_BDCR &= ~((1 << 8) | (1 << 9));
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Setup the A/D Clock
@ -1089,9 +1159,10 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Reset the backup domain
/** @brief RCC Reset the Backup Domain
The backup domain register is reset to disable all controls.
The backup domain registers are reset to disable RTC controls and clear user
data.
*/
void rcc_backupdomain_reset(void)

66
lib/stm32/f1/rtc.c
View File

@ -84,7 +84,8 @@ established.
@note The Backup Domain is reset by this function and will therefore result in
the loss of any unrelated user data stored there.
@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/128, LSE and LSI.
@param[in] clock_source ::rcc_osc. RTC clock source. Only the values HSE, LSE
and LSI are permitted.
*/
void rtc_awake_from_off(enum rcc_osc clock_source)
@ -92,10 +93,11 @@ void rtc_awake_from_off(enum rcc_osc clock_source)
uint32_t reg32;
/* Enable power and backup interface clocks. */
RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN);
rcc_periph_clock_enable(RCC_PWR);
rcc_periph_clock_enable(RCC_BKP);
/* Enable access to the backup registers and the RTC. */
PWR_CR |= PWR_CR_DBP;
pwr_disable_backup_domain_write_protect();
/*
* Reset the backup domain, clears everything RTC related.
@ -103,46 +105,11 @@ void rtc_awake_from_off(enum rcc_osc clock_source)
*/
rcc_backupdomain_reset();
switch (clock_source) {
case LSE:
/* Turn the LSE on and wait while it stabilises. */
RCC_BDCR |= RCC_BDCR_LSEON;
while ((reg32 = (RCC_BDCR & RCC_BDCR_LSERDY)) == 0);
/* Choose LSE as the RTC clock source. */
RCC_BDCR &= ~((1 << 8) | (1 << 9));
RCC_BDCR |= (1 << 8);
break;
case LSI:
/* Turn the LSI on and wait while it stabilises. */
RCC_CSR |= RCC_CSR_LSION;
while ((reg32 = (RCC_CSR & RCC_CSR_LSIRDY)) == 0);
/* Choose LSI as the RTC clock source. */
RCC_BDCR &= ~((1 << 8) | (1 << 9));
RCC_BDCR |= (1 << 9);
break;
case HSE:
/* Turn the HSE on and wait while it stabilises. */
RCC_CR |= RCC_CR_HSEON;
while ((reg32 = (RCC_CR & RCC_CR_HSERDY)) == 0);
/* Choose HSE as the RTC clock source. */
RCC_BDCR &= ~((1 << 8) | (1 << 9));
RCC_BDCR |= (1 << 9) | (1 << 8);
break;
case PLL:
case PLL2:
case PLL3:
case HSI:
/* Unusable clock source, here to prevent warnings. */
/* Turn off clock sources to RTC. */
RCC_BDCR &= ~((1 << 8) | (1 << 9));
break;
}
/* Set the clock source */
rcc_set_rtc_clock_source(clock_source);
/* Enable the RTC. */
RCC_BDCR |= RCC_BDCR_RTCEN;
rcc_enable_rtc_clock();
/* Wait for the RSF bit in RTC_CRL to be set by hardware. */
RTC_CRL &= ~RTC_CRL_RSF;
@ -405,10 +372,11 @@ void rtc_awake_from_standby(void)
uint32_t reg32;
/* Enable power and backup interface clocks. */
RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN);
rcc_periph_clock_enable(RCC_PWR);
rcc_periph_clock_enable(RCC_BKP);
/* Enable access to the backup registers and the RTC. */
PWR_CR |= PWR_CR_DBP;
pwr_disable_backup_domain_write_protect();
/* Wait for the RSF bit in RTC_CRL to be set by hardware. */
RTC_CRL &= ~RTC_CRL_RSF;
@ -426,7 +394,8 @@ Enable the backup domain clocks and write access to the backup domain.
If the RTC has not been enabled, set the clock source and prescaler value.
The parameters are not used if the RTC has already been enabled.
@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/128, LSE and LSI.
@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE, LSE
and LSI are permitted.
@param[in] prescale_val uint32_t. 20 bit prescale divider.
*/
@ -435,13 +404,10 @@ void rtc_auto_awake(enum rcc_osc clock_source, uint32_t prescale_val)
uint32_t reg32;
/* Enable power and backup interface clocks. */
RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN);
rcc_periph_clock_enable(RCC_PWR);
rcc_periph_clock_enable(RCC_BKP);
/* Enable access to the backup registers and the RTC. */
/* TODO: Not sure if this is necessary to just read the flag. */
PWR_CR |= PWR_CR_DBP;
reg32 = RCC_BDCR & RCC_BDCR_RTCEN;
reg32 = rcc_rtc_clock_enabled_flag();
if (reg32 != 0) {
rtc_awake_from_standby();