From d3a073d9b57ae7a5c7916d2a75ba2b35e5374178 Mon Sep 17 00:00:00 2001 From: BuFran Date: Mon, 8 Jul 2013 17:51:21 +0200 Subject: [PATCH] [Style] Corrected many style errors (mainly line too long) --- include/libopencm3/lpc43xx/cgu.h | 650 +++++++++++++++------------- include/libopencm3/lpc43xx/creg.h | 12 +- include/libopencm3/lpc43xx/gpdma.h | 409 ++++++++++++------ include/libopencm3/lpc43xx/gpio.h | 102 +++-- include/libopencm3/lpc43xx/rgu.h | 195 ++++++--- include/libopencm3/lpc43xx/sgpio.h | 652 ++++++++++++++++++----------- include/libopencm3/lpc43xx/timer.h | 12 +- include/libopencm3/lpc43xx/uart.h | 348 +++++++++------ include/libopencm3/lpc43xx/usb.h | 90 ++-- 9 files changed, 1528 insertions(+), 942 deletions(-) diff --git a/include/libopencm3/lpc43xx/cgu.h b/include/libopencm3/lpc43xx/cgu.h index 597f3f38..0a169fd6 100644 --- a/include/libopencm3/lpc43xx/cgu.h +++ b/include/libopencm3/lpc43xx/cgu.h @@ -1,16 +1,18 @@ /** @defgroup cgu_defines Clock Generation Unit Defines - -@brief Defined Constants and Types for the LPC43xx Clock Generation Unit - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license + * + * @brief Defined Constants and Types for the LPC43xx Clock Generation + * Unit + * + * @ingroup LPC43xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann + * + * + * @date 10 March 2013 + * + * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. @@ -182,707 +184,763 @@ LGPL License Terms @ref lgpl_license /* --- CGU_FREQ_MON values -------------------------------------- */ /* RCNT: 9-bit reference clock-counter value */ -#define CGU_FREQ_MON_RCNT_SHIFT (0) -#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT) -#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT) +#define CGU_FREQ_MON_RCNT_SHIFT (0) +#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT) +#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT) /* FCNT: 14-bit selected clock-counter value */ -#define CGU_FREQ_MON_FCNT_SHIFT (9) -#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT) -#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT) +#define CGU_FREQ_MON_FCNT_SHIFT (9) +#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT) +#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT) /* MEAS: Measure frequency */ -#define CGU_FREQ_MON_MEAS_SHIFT (23) -#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT) +#define CGU_FREQ_MON_MEAS_SHIFT (23) +#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT) /* CLK_SEL: Clock-source selection for the clock to be measured */ -#define CGU_FREQ_MON_CLK_SEL_SHIFT (24) -#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT) -#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT) +#define CGU_FREQ_MON_CLK_SEL_SHIFT (24) +#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT) +#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT) /* --- CGU_XTAL_OSC_CTRL values --------------------------------- */ /* ENABLE: Oscillator-pad enable */ -#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0) -#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT) +#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0) +#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT) /* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */ -#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1) -#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT) +#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1) +#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT) /* HF: Select frequency range */ -#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2) -#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT) +#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2) +#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT) /* --- CGU_PLL0USB_STAT values ---------------------------------- */ /* LOCK: PLL0 lock indicator */ -#define CGU_PLL0USB_STAT_LOCK_SHIFT (0) -#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT) +#define CGU_PLL0USB_STAT_LOCK_SHIFT (0) +#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT) /* FR: PLL0 free running indicator */ -#define CGU_PLL0USB_STAT_FR_SHIFT (1) -#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT) +#define CGU_PLL0USB_STAT_FR_SHIFT (1) +#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT) /* --- CGU_PLL0USB_CTRL values ---------------------------------- */ /* PD: PLL0 power down */ -#define CGU_PLL0USB_CTRL_PD_SHIFT (0) -#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT) +#define CGU_PLL0USB_CTRL_PD_SHIFT (0) +#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT) /* BYPASS: Input clock bypass control */ -#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1) -#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT) +#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT) /* DIRECTI: PLL0 direct input */ -#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2) -#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT) +#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2) +#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT) /* DIRECTO: PLL0 direct output */ -#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3) -#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT) +#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3) +#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT) /* CLKEN: PLL0 clock enable */ -#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4) -#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT) +#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4) +#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT) /* FRM: Free running mode */ -#define CGU_PLL0USB_CTRL_FRM_SHIFT (6) -#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT) +#define CGU_PLL0USB_CTRL_FRM_SHIFT (6) +#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT) +#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ -#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24) -#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) -#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) /* --- CGU_PLL0USB_MDIV values ---------------------------------- */ /* MDEC: Decoded M-divider coefficient value */ -#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0) -#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT) -#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT) +#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0) +#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT) +#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT) /* SELP: Bandwidth select P value */ -#define CGU_PLL0USB_MDIV_SELP_SHIFT (17) -#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT) -#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT) +#define CGU_PLL0USB_MDIV_SELP_SHIFT (17) +#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT) +#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT) /* SELI: Bandwidth select I value */ -#define CGU_PLL0USB_MDIV_SELI_SHIFT (22) -#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT) -#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT) +#define CGU_PLL0USB_MDIV_SELI_SHIFT (22) +#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT) +#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT) /* SELR: Bandwidth select R value */ -#define CGU_PLL0USB_MDIV_SELR_SHIFT (28) -#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT) -#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT) +#define CGU_PLL0USB_MDIV_SELR_SHIFT (28) +#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT) +#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT) /* --- CGU_PLL0USB_NP_DIV values -------------------------------- */ /* PDEC: Decoded P-divider coefficient value */ -#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0) -#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) -#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) +#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0) +#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) +#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) /* NDEC: Decoded N-divider coefficient value */ -#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12) -#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) -#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) +#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12) +#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) +#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) /* --- CGU_PLL0AUDIO_STAT values -------------------------------- */ /* LOCK: PLL0 lock indicator */ -#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0) -#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT) +#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0) +#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT) /* FR: PLL0 free running indicator */ -#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1) -#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT) +#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1) +#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT) /* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */ /* PD: PLL0 power down */ -#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0) -#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT) +#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0) +#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT) /* BYPASS: Input clock bypass control */ -#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1) -#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT) +#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT) /* DIRECTI: PLL0 direct input */ #define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2) -#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT) +#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT) /* DIRECTO: PLL0 direct output */ #define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3) -#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT) +#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT) /* CLKEN: PLL0 clock enable */ -#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4) -#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT) +#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4) +#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT) /* FRM: Free running mode */ -#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6) -#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT) +#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6) +#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT) +#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK \ + (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT) /* PLLFRACT_REQ: Fractional PLL word write request */ #define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12) -#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT) +#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ \ + (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT) /* SEL_EXT: Select fractional divider */ #define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13) -#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT) +#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT) /* MOD_PD: Sigma-Delta modulator power-down */ #define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14) -#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT) +#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24) -#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) -#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK \ + (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) \ + ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) /* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */ /* MDEC: Decoded M-divider coefficient value */ -#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0) -#define CGU_PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) -#define CGU_PLL0AUDIO_MDIV_MDEC(x) ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) +#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0) +#define CGU_PLL0AUDIO_MDIV_MDEC_MASK \ + (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) +#define CGU_PLL0AUDIO_MDIV_MDEC(x) \ + ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) /* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */ /* PDEC: Decoded P-divider coefficient value */ -#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) -#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) -#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) +#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) +#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK \ + (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) +#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) \ + ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) /* NDEC: Decoded N-divider coefficient value */ -#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) -#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) -#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) +#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) +#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK \ + (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) +#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) \ + ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) /* --- CGU_PLLAUDIO_FRAC values --------------------------------- */ /* PLLFRACT_CTRL: PLL fractional divider control word */ -#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0) -#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) -#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0) +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK \ + (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) \ + ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) /* --- CGU_PLL1_STAT values ------------------------------------- */ /* LOCK: PLL1 lock indicator */ -#define CGU_PLL1_STAT_LOCK_SHIFT (0) -#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT) +#define CGU_PLL1_STAT_LOCK_SHIFT (0) +#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT) /* --- CGU_PLL1_CTRL values ------------------------------------- */ /* PD: PLL1 power down */ -#define CGU_PLL1_CTRL_PD_SHIFT (0) -#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT) +#define CGU_PLL1_CTRL_PD_SHIFT (0) +#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT) /* BYPASS: Input clock bypass control */ -#define CGU_PLL1_CTRL_BYPASS_SHIFT (1) -#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT) +#define CGU_PLL1_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT) /* FBSEL: PLL feedback select */ -#define CGU_PLL1_CTRL_FBSEL_SHIFT (6) -#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT) +#define CGU_PLL1_CTRL_FBSEL_SHIFT (6) +#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT) /* DIRECT: PLL direct CCO output */ -#define CGU_PLL1_CTRL_DIRECT_SHIFT (7) -#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT) +#define CGU_PLL1_CTRL_DIRECT_SHIFT (7) +#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT) /* PSEL: Post-divider division ratio P */ -#define CGU_PLL1_CTRL_PSEL_SHIFT (8) -#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT) -#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT) +#define CGU_PLL1_CTRL_PSEL_SHIFT (8) +#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT) +#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT) +#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT) /* NSEL: Pre-divider division ratio N */ -#define CGU_PLL1_CTRL_NSEL_SHIFT (12) -#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT) -#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT) +#define CGU_PLL1_CTRL_NSEL_SHIFT (12) +#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT) +#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT) /* MSEL: Feedback-divider division ratio (M) */ -#define CGU_PLL1_CTRL_MSEL_SHIFT (16) -#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT) -#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT) +#define CGU_PLL1_CTRL_MSEL_SHIFT (16) +#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT) +#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT) /* CLK_SEL: Clock-source selection */ -#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24) -#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT) -#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT) /* --- CGU_IDIVA_CTRL values ------------------------------------ */ /* PD: Integer divider power down */ -#define CGU_IDIVA_CTRL_PD_SHIFT (0) -#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT) +#define CGU_IDIVA_CTRL_PD_SHIFT (0) +#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT) /* IDIV: Integer divider A divider value (1/(IDIV + 1)) */ -#define CGU_IDIVA_CTRL_IDIV_SHIFT (2) -#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT) -#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT) +#define CGU_IDIVA_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT) +#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT) +#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ -#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24) -#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) -#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) /* --- CGU_IDIVB_CTRL values ------------------------------------ */ /* PD: Integer divider power down */ -#define CGU_IDIVB_CTRL_PD_SHIFT (0) -#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT) +#define CGU_IDIVB_CTRL_PD_SHIFT (0) +#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT) /* IDIV: Integer divider B divider value (1/(IDIV + 1)) */ -#define CGU_IDIVB_CTRL_IDIV_SHIFT (2) -#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT) -#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT) +#define CGU_IDIVB_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT) +#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT) +#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ -#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24) -#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) -#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) /* --- CGU_IDIVC_CTRL values ------------------------------------ */ /* PD: Integer divider power down */ -#define CGU_IDIVC_CTRL_PD_SHIFT (0) -#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT) +#define CGU_IDIVC_CTRL_PD_SHIFT (0) +#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT) /* IDIV: Integer divider C divider value (1/(IDIV + 1)) */ -#define CGU_IDIVC_CTRL_IDIV_SHIFT (2) -#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT) -#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT) +#define CGU_IDIVC_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT) +#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT) +#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ -#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24) -#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) -#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) /* --- CGU_IDIVD_CTRL values ------------------------------------ */ /* PD: Integer divider power down */ -#define CGU_IDIVD_CTRL_PD_SHIFT (0) -#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT) +#define CGU_IDIVD_CTRL_PD_SHIFT (0) +#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT) /* IDIV: Integer divider D divider value (1/(IDIV + 1)) */ -#define CGU_IDIVD_CTRL_IDIV_SHIFT (2) -#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT) -#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT) +#define CGU_IDIVD_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT) +#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT) +#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ -#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24) -#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) -#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) /* --- CGU_IDIVE_CTRL values ------------------------------------ */ /* PD: Integer divider power down */ -#define CGU_IDIVE_CTRL_PD_SHIFT (0) -#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT) +#define CGU_IDIVE_CTRL_PD_SHIFT (0) +#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT) /* IDIV: Integer divider E divider value (1/(IDIV + 1)) */ -#define CGU_IDIVE_CTRL_IDIV_SHIFT (2) -#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT) -#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT) +#define CGU_IDIVE_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT) +#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ -#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11) -#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT) +#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ -#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24) -#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) -#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) /* --- CGU_BASE_SAFE_CLK values --------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_SAFE_CLK_PD_SHIFT (0) -#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT) +#define CGU_BASE_SAFE_CLK_PD_SHIFT (0) +#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SAFE_CLK_CLK_SEL(x) ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SAFE_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_USB0_CLK values --------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_USB0_CLK_PD_SHIFT (0) -#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT) +#define CGU_BASE_USB0_CLK_PD_SHIFT (0) +#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_USB0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_USB0_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_USB0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_USB0_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_PERIPH_CLK values ------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0) -#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT) +#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0) +#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_PERIPH_CLK_AUTOBLOCK (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_PERIPH_CLK_AUTOBLOCK \ + (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_USB1_CLK values --------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_USB1_CLK_PD_SHIFT (0) -#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT) +#define CGU_BASE_USB1_CLK_PD_SHIFT (0) +#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_USB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_USB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_USB1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_USB1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_M4_CLK values ----------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_M4_CLK_PD_SHIFT (0) -#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT) +#define CGU_BASE_M4_CLK_PD_SHIFT (0) +#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_SPIFI_CLK values -------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0) -#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT) +#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0) +#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SPIFI_CLK_AUTOBLOCK (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_SPIFI_CLK_AUTOBLOCK \ + (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_SPI_CLK values ---------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_SPI_CLK_PD_SHIFT (0) -#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT) +#define CGU_BASE_SPI_CLK_PD_SHIFT (0) +#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ -#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0) -#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT) +#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0) +#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK \ + (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0) -#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT) +#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0) +#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK \ + (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_APB1_CLK values --------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_APB1_CLK_PD_SHIFT (0) -#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT) +#define CGU_BASE_APB1_CLK_PD_SHIFT (0) +#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_APB1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APB1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_APB3_CLK values --------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_APB3_CLK_PD_SHIFT (0) -#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT) +#define CGU_BASE_APB3_CLK_PD_SHIFT (0) +#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_APB3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APB3_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_LCD_CLK values ---------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_LCD_CLK_PD_SHIFT (0) -#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT) +#define CGU_BASE_LCD_CLK_PD_SHIFT (0) +#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ -#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_VADC_CLK values --------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_VADC_CLK_PD_SHIFT (0) -#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT) +#define CGU_BASE_VADC_CLK_PD_SHIFT (0) +#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_VADC_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_VADC_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_SDIO_CLK values --------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_SDIO_CLK_PD_SHIFT (0) -#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT) +#define CGU_BASE_SDIO_CLK_PD_SHIFT (0) +#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_SSP0_CLK values --------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_SSP0_CLK_PD_SHIFT (0) -#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT) +#define CGU_BASE_SSP0_CLK_PD_SHIFT (0) +#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_SSP1_CLK values --------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_SSP1_CLK_PD_SHIFT (0) -#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT) +#define CGU_BASE_SSP1_CLK_PD_SHIFT (0) +#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_SSP1_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SSP1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_UART0_CLK values -------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_UART0_CLK_PD_SHIFT (0) -#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT) +#define CGU_BASE_UART0_CLK_PD_SHIFT (0) +#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_UART0_CLK_AUTOBLOCK (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_UART0_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_UART0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_UART0_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART0_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_UART1_CLK values -------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_UART1_CLK_PD_SHIFT (0) -#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT) +#define CGU_BASE_UART1_CLK_PD_SHIFT (0) +#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_UART1_CLK_AUTOBLOCK (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_UART1_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_UART1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_UART1_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_UART2_CLK values -------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_UART2_CLK_PD_SHIFT (0) -#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT) +#define CGU_BASE_UART2_CLK_PD_SHIFT (0) +#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_UART2_CLK_AUTOBLOCK (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_UART2_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_UART2_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_UART2_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART2_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART2_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_UART3_CLK values -------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_UART3_CLK_PD_SHIFT (0) -#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT) +#define CGU_BASE_UART3_CLK_PD_SHIFT (0) +#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_UART3_CLK_AUTOBLOCK (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_UART3_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_UART3_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_UART3_CLK_CLK_SEL(x) ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART3_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART3_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_OUT_CLK values ---------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_OUT_CLK_PD_SHIFT (0) -#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT) +#define CGU_BASE_OUT_CLK_PD_SHIFT (0) +#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ -#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_APLL_CLK values --------------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_APLL_CLK_PD_SHIFT (0) -#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT) +#define CGU_BASE_APLL_CLK_PD_SHIFT (0) +#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_APLL_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APLL_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0) -#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT) +#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0) +#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK \ + (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */ /* PD: Output stage power down */ -#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0) -#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT) +#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0) +#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT) /* AUTOBLOCK: Block clock automatically during frequency change */ #define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11) -#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT) +#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK \ + (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT) /* CLK_SEL: Clock source selection */ #define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24) -#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) -#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) /* --- CGU_BASE_x_CLK clock sources --------------------------------------- */ diff --git a/include/libopencm3/lpc43xx/creg.h b/include/libopencm3/lpc43xx/creg.h index 7b5cac1b..2c695510 100644 --- a/include/libopencm3/lpc43xx/creg.h +++ b/include/libopencm3/lpc43xx/creg.h @@ -255,7 +255,8 @@ LGPL License Terms @ref lgpl_license /* --- CREG_FLASHCFGA values ------------------------------------ */ -/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access */ +/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number + * of BASE_M4_CLK clocks used for a flash access */ #define CREG_FLASHCFGA_FLASHTIM_SHIFT (12) #define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT) #define CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT) @@ -266,7 +267,8 @@ LGPL License Terms @ref lgpl_license /* --- CREG_FLASHCFGB values ------------------------------------ */ -/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number of BASE_M4_CLK clocks used for a flash access */ +/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number + * of BASE_M4_CLK clocks used for a flash access */ #define CREG_FLASHCFGB_FLASHTIM_SHIFT (12) #define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT) #define CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT) @@ -283,7 +285,8 @@ LGPL License Terms @ref lgpl_license /* --- CREG_CREG6 values ---------------------------------------- */ -/* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the PHY interface */ +/* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the + * PHY interface */ #define CREG_CREG6_ETHMODE_SHIFT (0) #define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT) #define CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT) @@ -328,7 +331,8 @@ LGPL License Terms @ref lgpl_license /* M0APPMAP: Shadow address when accessing memory at address 0x00000000 */ #define CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12) -#define CREG_M0APPMEMMAP_M0APPMAP_MASK (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) +#define CREG_M0APPMEMMAP_M0APPMAP_MASK \ + (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) #define CREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) /* --- CREG_USB0FLADJ values ------------------------------------ */ diff --git a/include/libopencm3/lpc43xx/gpdma.h b/include/libopencm3/lpc43xx/gpdma.h index eed791dd..32d42947 100644 --- a/include/libopencm3/lpc43xx/gpdma.h +++ b/include/libopencm3/lpc43xx/gpdma.h @@ -1,16 +1,16 @@ /** @defgroup gpdma_defines General Purpose DMA Defines - -@brief Defined Constants and Types for the LPC43xx General Purpose DMA - -@ingroup LPC43xx_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2012 Michael Ossmann - -@date 10 March 2013 - -LGPL License Terms @ref lgpl_license + * + * @brief Defined Constants and Types for the LPC43xx General Purpose DMA + * + * @ingroup LPC43xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann + * + * @date 10 March 2013 + * + * LGPL License Terms @ref lgpl_license */ /* * This file is part of the libopencm3 project. @@ -89,7 +89,8 @@ LGPL License Terms @ref lgpl_license /* Channel registers */ /* Source Address Register */ -#define GPDMA_CSRCADDR(channel) MMIO32(GPDMA_BASE + (channel * 0x20) + 0x100) +#define GPDMA_CSRCADDR(channel) MMIO32(GPDMA_BASE + 0x100 + \ + (channel * 0x20)) #define GPDMA_C0SRCADDR GPDMA_CSRCADDR(0) #define GPDMA_C1SRCADDR GPDMA_CSRCADDR(1) #define GPDMA_C2SRCADDR GPDMA_CSRCADDR(2) @@ -100,7 +101,8 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C7SRCADDR GPDMA_CSRCADDR(7) /* Destination Address Register */ -#define GPDMA_CDESTADDR(channel) MMIO32(GPDMA_BASE + (channel * 0x20) + 0x104) +#define GPDMA_CDESTADDR(channel) MMIO32(GPDMA_BASE + 0x104 + \ + (channel * 0x20)) #define GPDMA_C0DESTADDR GPDMA_CDESTADDR(0) #define GPDMA_C1DESTADDR GPDMA_CDESTADDR(1) #define GPDMA_C2DESTADDR GPDMA_CDESTADDR(2) @@ -111,7 +113,8 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C7DESTADDR GPDMA_CDESTADDR(7) /* Linked List Item Register */ -#define GPDMA_CLLI(channel) MMIO32(GPDMA_BASE + (channel * 0x20) + 0x108) +#define GPDMA_CLLI(channel) MMIO32(GPDMA_BASE + 0x108 + \ + (channel * 0x20)) #define GPDMA_C0LLI GPDMA_CLLI(0) #define GPDMA_C1LLI GPDMA_CLLI(1) #define GPDMA_C2LLI GPDMA_CLLI(2) @@ -122,7 +125,8 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C7LLI GPDMA_CLLI(7) /* Control Register */ -#define GPDMA_CCONTROL(channel) MMIO32(GPDMA_BASE + (channel * 0x20) + 0x10C) +#define GPDMA_CCONTROL(channel) MMIO32(GPDMA_BASE + 0x10C + \ + (channel * 0x20)) #define GPDMA_C0CONTROL GPDMA_CCONTROL(0) #define GPDMA_C1CONTROL GPDMA_CCONTROL(1) #define GPDMA_C2CONTROL GPDMA_CCONTROL(2) @@ -133,7 +137,8 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C7CONTROL GPDMA_CCONTROL(7) /* Configuration Register */ -#define GPDMA_CCONFIG(channel) MMIO32(GPDMA_BASE + (channel * 0x20) + 0x110) +#define GPDMA_CCONFIG(channel) MMIO32(GPDMA_BASE + 0x110 + \ + (channel * 0x20)) #define GPDMA_C0CONFIG GPDMA_CCONFIG(0) #define GPDMA_C1CONFIG GPDMA_CCONFIG(1) #define GPDMA_C2CONFIG GPDMA_CCONFIG(2) @@ -150,7 +155,8 @@ LGPL License Terms @ref lgpl_license #define GPDMA_CSRCADDR_SRCADDR(x) ((x) << GPDMA_CSRCADDR_SRCADDR_SHIFT) #define GPDMA_CDESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_CDESTADDR_DESTADDR_MASK (0xffffffff << GPDMA_CDESTADDR_DESTADDR_SHIFT) +#define GPDMA_CDESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_CDESTADDR_DESTADDR_SHIFT) #define GPDMA_CDESTADDR_DESTADDR(x) ((x) << GPDMA_CDESTADDR_DESTADDR_SHIFT) #define GPDMA_CLLI_LM_SHIFT (0) @@ -162,8 +168,10 @@ LGPL License Terms @ref lgpl_license #define GPDMA_CLLI_LLI(x) ((x) << GPDMA_CLLI_LLI_SHIFT) #define GPDMA_CCONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_CCONTROL_TRANSFERSIZE_MASK (0xfff << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_CCONTROL_TRANSFERSIZE(x) ((x) << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_CCONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_CCONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) #define GPDMA_CCONTROL_SBSIZE_SHIFT (12) #define GPDMA_CCONTROL_SBSIZE_MASK (0x7 << GPDMA_CCONTROL_SBSIZE_SHIFT) @@ -218,12 +226,16 @@ LGPL License Terms @ref lgpl_license #define GPDMA_CCONFIG_E(x) ((x) << GPDMA_CCONFIG_E_SHIFT) #define GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_CCONFIG_SRCPERIPHERAL_MASK (0x1f << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_CCONFIG_SRCPERIPHERAL(x) ((x) << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_CCONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_CCONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) #define GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_CCONFIG_DESTPERIPHERAL_MASK (0x1f << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_CCONFIG_DESTPERIPHERAL(x) ((x) << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_CCONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_CCONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) #define GPDMA_CCONFIG_FLOWCNTRL_SHIFT (11) #define GPDMA_CCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CCONFIG_FLOWCNTRL_SHIFT) @@ -267,45 +279,61 @@ LGPL License Terms @ref lgpl_license /* --- GPDMA_INTTCCLEAR values ---------------------------------- */ -/* INTTCCLEAR: Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels */ +/* INTTCCLEAR: Allows clearing the Terminal count interrupt request (IntTCStat) + for DMA channels */ #define GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT (0) -#define GPDMA_INTTCCLEAR_INTTCCLEAR_MASK (0xff << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) -#define GPDMA_INTTCCLEAR_INTTCCLEAR(x) ((x) << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) +#define GPDMA_INTTCCLEAR_INTTCCLEAR_MASK \ + (0xff << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) +#define GPDMA_INTTCCLEAR_INTTCCLEAR(x) \ + ((x) << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) /* --- GPDMA_INTERRSTAT values ---------------------------------- */ /* INTERRSTAT: Interrupt error status for DMA channels */ #define GPDMA_INTERRSTAT_INTERRSTAT_SHIFT (0) -#define GPDMA_INTERRSTAT_INTERRSTAT_MASK (0xff << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) -#define GPDMA_INTERRSTAT_INTERRSTAT(x) ((x) << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) +#define GPDMA_INTERRSTAT_INTERRSTAT_MASK \ + (0xff << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) +#define GPDMA_INTERRSTAT_INTERRSTAT(x) \ + ((x) << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) /* --- GPDMA_INTERRCLR values ----------------------------------- */ -/* INTERRCLR: Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels */ +/* INTERRCLR: Writing a 1 clears the error interrupt request (IntErrStat) + for DMA channels */ #define GPDMA_INTERRCLR_INTERRCLR_SHIFT (0) -#define GPDMA_INTERRCLR_INTERRCLR_MASK (0xff << GPDMA_INTERRCLR_INTERRCLR_SHIFT) -#define GPDMA_INTERRCLR_INTERRCLR(x) ((x) << GPDMA_INTERRCLR_INTERRCLR_SHIFT) +#define GPDMA_INTERRCLR_INTERRCLR_MASK \ + (0xff << GPDMA_INTERRCLR_INTERRCLR_SHIFT) +#define GPDMA_INTERRCLR_INTERRCLR(x) \ + ((x) << GPDMA_INTERRCLR_INTERRCLR_SHIFT) /* --- GPDMA_RAWINTTCSTAT values -------------------------------- */ -/* RAWINTTCSTAT: Status of the terminal count interrupt for DMA channels prior to masking */ +/* RAWINTTCSTAT: Status of the terminal count interrupt for DMA channels + prior to masking */ #define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT (0) -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_MASK (0xff << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) -#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT(x) ((x) << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_MASK \ + (0xff << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT(x) \ + ((x) << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) /* --- GPDMA_RAWINTERRSTAT values ------------------------------- */ -/* RAWINTERRSTAT: Status of the error interrupt for DMA channels prior to masking */ +/* RAWINTERRSTAT: Status of the error interrupt for DMA channels prior to + masking */ #define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT (0) -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_MASK (0xff << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) -#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT(x) ((x) << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_MASK \ + (0xff << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT(x) \ + ((x) << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) /* --- GPDMA_ENBLDCHNS values ----------------------------------- */ /* ENABLEDCHANNELS: Enable status for DMA channels */ #define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT (0) -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_MASK (0xff << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) -#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS(x) ((x) << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_MASK \ + (0xff << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS(x) \ + ((x) << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) /* --- GPDMA_SOFTBREQ values ------------------------------------ */ @@ -316,24 +344,31 @@ LGPL License Terms @ref lgpl_license /* --- GPDMA_SOFTSREQ values ------------------------------------ */ -/* SOFTSREQ: Software single transfer request flags for each of 16 possible sources */ +/* SOFTSREQ: Software single transfer request flags for each of 16 possible + sources */ #define GPDMA_SOFTSREQ_SOFTSREQ_SHIFT (0) #define GPDMA_SOFTSREQ_SOFTSREQ_MASK (0xffff << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT) #define GPDMA_SOFTSREQ_SOFTSREQ(x) ((x) << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT) /* --- GPDMA_SOFTLBREQ values ----------------------------------- */ -/* SOFTLBREQ: Software last burst request flags for each of 16 possible sources */ +/* SOFTLBREQ: Software last burst request flags for each of 16 possible + sources */ #define GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT (0) -#define GPDMA_SOFTLBREQ_SOFTLBREQ_MASK (0xffff << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) -#define GPDMA_SOFTLBREQ_SOFTLBREQ(x) ((x) << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) +#define GPDMA_SOFTLBREQ_SOFTLBREQ_MASK \ + (0xffff << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) +#define GPDMA_SOFTLBREQ_SOFTLBREQ(x) \ + ((x) << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) /* --- GPDMA_SOFTLSREQ values ----------------------------------- */ -/* SOFTLSREQ: Software last single transfer request flags for each of 16 possible sources */ +/* SOFTLSREQ: Software last single transfer request flags for each of 16 + possible sources */ #define GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT (0) -#define GPDMA_SOFTLSREQ_SOFTLSREQ_MASK (0xffff << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) -#define GPDMA_SOFTLSREQ_SOFTLSREQ(x) ((x) << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) +#define GPDMA_SOFTLSREQ_SOFTLSREQ_MASK \ + (0xffff << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) +#define GPDMA_SOFTLSREQ_SOFTLSREQ(x) \ + ((x) << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) /* --- GPDMA_CONFIG values -------------------------------------- */ @@ -363,112 +398,128 @@ LGPL License Terms @ref lgpl_license /* SRCADDR: DMA source address */ #define GPDMA_C0SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C0SRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_C0SRCADDR_SRCADDR_SHIFT) +#define GPDMA_C0SRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_C0SRCADDR_SRCADDR_SHIFT) #define GPDMA_C0SRCADDR_SRCADDR(x) ((x) << GPDMA_C0SRCADDR_SRCADDR_SHIFT) /* --- GPDMA_C1SRCADDR values ----------------------------------- */ /* SRCADDR: DMA source address */ #define GPDMA_C1SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C1SRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_C1SRCADDR_SRCADDR_SHIFT) +#define GPDMA_C1SRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_C1SRCADDR_SRCADDR_SHIFT) #define GPDMA_C1SRCADDR_SRCADDR(x) ((x) << GPDMA_C1SRCADDR_SRCADDR_SHIFT) /* --- GPDMA_C2SRCADDR values ----------------------------------- */ /* SRCADDR: DMA source address */ #define GPDMA_C2SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C2SRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_C2SRCADDR_SRCADDR_SHIFT) +#define GPDMA_C2SRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_C2SRCADDR_SRCADDR_SHIFT) #define GPDMA_C2SRCADDR_SRCADDR(x) ((x) << GPDMA_C2SRCADDR_SRCADDR_SHIFT) /* --- GPDMA_C3SRCADDR values ----------------------------------- */ /* SRCADDR: DMA source address */ #define GPDMA_C3SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C3SRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_C3SRCADDR_SRCADDR_SHIFT) +#define GPDMA_C3SRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_C3SRCADDR_SRCADDR_SHIFT) #define GPDMA_C3SRCADDR_SRCADDR(x) ((x) << GPDMA_C3SRCADDR_SRCADDR_SHIFT) /* --- GPDMA_C4SRCADDR values ----------------------------------- */ /* SRCADDR: DMA source address */ #define GPDMA_C4SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C4SRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_C4SRCADDR_SRCADDR_SHIFT) +#define GPDMA_C4SRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_C4SRCADDR_SRCADDR_SHIFT) #define GPDMA_C4SRCADDR_SRCADDR(x) ((x) << GPDMA_C4SRCADDR_SRCADDR_SHIFT) /* --- GPDMA_C5SRCADDR values ----------------------------------- */ /* SRCADDR: DMA source address */ #define GPDMA_C5SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C5SRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_C5SRCADDR_SRCADDR_SHIFT) +#define GPDMA_C5SRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_C5SRCADDR_SRCADDR_SHIFT) #define GPDMA_C5SRCADDR_SRCADDR(x) ((x) << GPDMA_C5SRCADDR_SRCADDR_SHIFT) /* --- GPDMA_C6SRCADDR values ----------------------------------- */ /* SRCADDR: DMA source address */ #define GPDMA_C6SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C6SRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_C6SRCADDR_SRCADDR_SHIFT) +#define GPDMA_C6SRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_C6SRCADDR_SRCADDR_SHIFT) #define GPDMA_C6SRCADDR_SRCADDR(x) ((x) << GPDMA_C6SRCADDR_SRCADDR_SHIFT) /* --- GPDMA_C7SRCADDR values ----------------------------------- */ /* SRCADDR: DMA source address */ #define GPDMA_C7SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C7SRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_C7SRCADDR_SRCADDR_SHIFT) +#define GPDMA_C7SRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_C7SRCADDR_SRCADDR_SHIFT) #define GPDMA_C7SRCADDR_SRCADDR(x) ((x) << GPDMA_C7SRCADDR_SRCADDR_SHIFT) /* --- GPDMA_C0DESTADDR values ---------------------------------- */ /* DESTADDR: DMA source address */ #define GPDMA_C0DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C0DESTADDR_DESTADDR_MASK (0xffffffff << GPDMA_C0DESTADDR_DESTADDR_SHIFT) +#define GPDMA_C0DESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_C0DESTADDR_DESTADDR_SHIFT) #define GPDMA_C0DESTADDR_DESTADDR(x) ((x) << GPDMA_C0DESTADDR_DESTADDR_SHIFT) /* --- GPDMA_C1DESTADDR values ---------------------------------- */ /* DESTADDR: DMA source address */ #define GPDMA_C1DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C1DESTADDR_DESTADDR_MASK (0xffffffff << GPDMA_C1DESTADDR_DESTADDR_SHIFT) +#define GPDMA_C1DESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_C1DESTADDR_DESTADDR_SHIFT) #define GPDMA_C1DESTADDR_DESTADDR(x) ((x) << GPDMA_C1DESTADDR_DESTADDR_SHIFT) /* --- GPDMA_C2DESTADDR values ---------------------------------- */ /* DESTADDR: DMA source address */ #define GPDMA_C2DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C2DESTADDR_DESTADDR_MASK (0xffffffff << GPDMA_C2DESTADDR_DESTADDR_SHIFT) +#define GPDMA_C2DESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_C2DESTADDR_DESTADDR_SHIFT) #define GPDMA_C2DESTADDR_DESTADDR(x) ((x) << GPDMA_C2DESTADDR_DESTADDR_SHIFT) /* --- GPDMA_C3DESTADDR values ---------------------------------- */ /* DESTADDR: DMA source address */ #define GPDMA_C3DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C3DESTADDR_DESTADDR_MASK (0xffffffff << GPDMA_C3DESTADDR_DESTADDR_SHIFT) +#define GPDMA_C3DESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_C3DESTADDR_DESTADDR_SHIFT) #define GPDMA_C3DESTADDR_DESTADDR(x) ((x) << GPDMA_C3DESTADDR_DESTADDR_SHIFT) /* --- GPDMA_C4DESTADDR values ---------------------------------- */ /* DESTADDR: DMA source address */ #define GPDMA_C4DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C4DESTADDR_DESTADDR_MASK (0xffffffff << GPDMA_C4DESTADDR_DESTADDR_SHIFT) +#define GPDMA_C4DESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_C4DESTADDR_DESTADDR_SHIFT) #define GPDMA_C4DESTADDR_DESTADDR(x) ((x) << GPDMA_C4DESTADDR_DESTADDR_SHIFT) /* --- GPDMA_C5DESTADDR values ---------------------------------- */ /* DESTADDR: DMA source address */ #define GPDMA_C5DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C5DESTADDR_DESTADDR_MASK (0xffffffff << GPDMA_C5DESTADDR_DESTADDR_SHIFT) +#define GPDMA_C5DESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_C5DESTADDR_DESTADDR_SHIFT) #define GPDMA_C5DESTADDR_DESTADDR(x) ((x) << GPDMA_C5DESTADDR_DESTADDR_SHIFT) /* --- GPDMA_C6DESTADDR values ---------------------------------- */ /* DESTADDR: DMA source address */ #define GPDMA_C6DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C6DESTADDR_DESTADDR_MASK (0xffffffff << GPDMA_C6DESTADDR_DESTADDR_SHIFT) +#define GPDMA_C6DESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_C6DESTADDR_DESTADDR_SHIFT) #define GPDMA_C6DESTADDR_DESTADDR(x) ((x) << GPDMA_C6DESTADDR_DESTADDR_SHIFT) /* --- GPDMA_C7DESTADDR values ---------------------------------- */ /* DESTADDR: DMA source address */ #define GPDMA_C7DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C7DESTADDR_DESTADDR_MASK (0xffffffff << GPDMA_C7DESTADDR_DESTADDR_SHIFT) +#define GPDMA_C7DESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_C7DESTADDR_DESTADDR_SHIFT) #define GPDMA_C7DESTADDR_DESTADDR(x) ((x) << GPDMA_C7DESTADDR_DESTADDR_SHIFT) /* --- GPDMA_C0LLI values --------------------------------------- */ @@ -571,8 +622,10 @@ LGPL License Terms @ref lgpl_license /* TRANSFERSIZE: Transfer size in number of transfers */ #define GPDMA_C0CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C0CONTROL_TRANSFERSIZE_MASK (0xfff << GPDMA_C0CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C0CONTROL_TRANSFERSIZE(x) ((x) << GPDMA_C0CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C0CONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_C0CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C0CONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_C0CONTROL_TRANSFERSIZE_SHIFT) /* SBSIZE: Source burst size */ #define GPDMA_C0CONTROL_SBSIZE_SHIFT (12) @@ -614,17 +667,22 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C0CONTROL_DI_MASK (0x1 << GPDMA_C0CONTROL_DI_SHIFT) #define GPDMA_C0CONTROL_DI(x) ((x) << GPDMA_C0CONTROL_DI_SHIFT) -/* PROT1: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode */ +/* PROT1: This information is provided to the peripheral during a DMA bus + access and indicates that the access is in user mode or privileged mode */ #define GPDMA_C0CONTROL_PROT1_SHIFT (28) #define GPDMA_C0CONTROL_PROT1_MASK (0x1 << GPDMA_C0CONTROL_PROT1_SHIFT) #define GPDMA_C0CONTROL_PROT1(x) ((x) << GPDMA_C0CONTROL_PROT1_SHIFT) -/* PROT2: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable */ +/* PROT2: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is bufferable or not + bufferable */ #define GPDMA_C0CONTROL_PROT2_SHIFT (29) #define GPDMA_C0CONTROL_PROT2_MASK (0x1 << GPDMA_C0CONTROL_PROT2_SHIFT) #define GPDMA_C0CONTROL_PROT2(x) ((x) << GPDMA_C0CONTROL_PROT2_SHIFT) -/* PROT3: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable */ +/* PROT3: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is cacheable or not + cacheable */ #define GPDMA_C0CONTROL_PROT3_SHIFT (30) #define GPDMA_C0CONTROL_PROT3_MASK (0x1 << GPDMA_C0CONTROL_PROT3_SHIFT) #define GPDMA_C0CONTROL_PROT3(x) ((x) << GPDMA_C0CONTROL_PROT3_SHIFT) @@ -638,8 +696,10 @@ LGPL License Terms @ref lgpl_license /* TRANSFERSIZE: Transfer size in number of transfers */ #define GPDMA_C1CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C1CONTROL_TRANSFERSIZE_MASK (0xfff << GPDMA_C1CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C1CONTROL_TRANSFERSIZE(x) ((x) << GPDMA_C1CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C1CONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_C1CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C1CONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_C1CONTROL_TRANSFERSIZE_SHIFT) /* SBSIZE: Source burst size */ #define GPDMA_C1CONTROL_SBSIZE_SHIFT (12) @@ -681,17 +741,22 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C1CONTROL_DI_MASK (0x1 << GPDMA_C1CONTROL_DI_SHIFT) #define GPDMA_C1CONTROL_DI(x) ((x) << GPDMA_C1CONTROL_DI_SHIFT) -/* PROT1: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode */ +/* PROT1: This information is provided to the peripheral during a DMA bus + access and indicates that the access is in user mode or privileged mode */ #define GPDMA_C1CONTROL_PROT1_SHIFT (28) #define GPDMA_C1CONTROL_PROT1_MASK (0x1 << GPDMA_C1CONTROL_PROT1_SHIFT) #define GPDMA_C1CONTROL_PROT1(x) ((x) << GPDMA_C1CONTROL_PROT1_SHIFT) -/* PROT2: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable */ +/* PROT2: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is bufferable or not + bufferable */ #define GPDMA_C1CONTROL_PROT2_SHIFT (29) #define GPDMA_C1CONTROL_PROT2_MASK (0x1 << GPDMA_C1CONTROL_PROT2_SHIFT) #define GPDMA_C1CONTROL_PROT2(x) ((x) << GPDMA_C1CONTROL_PROT2_SHIFT) -/* PROT3: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable */ +/* PROT3: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is cacheable or not + cacheable */ #define GPDMA_C1CONTROL_PROT3_SHIFT (30) #define GPDMA_C1CONTROL_PROT3_MASK (0x1 << GPDMA_C1CONTROL_PROT3_SHIFT) #define GPDMA_C1CONTROL_PROT3(x) ((x) << GPDMA_C1CONTROL_PROT3_SHIFT) @@ -705,8 +770,10 @@ LGPL License Terms @ref lgpl_license /* TRANSFERSIZE: Transfer size in number of transfers */ #define GPDMA_C2CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C2CONTROL_TRANSFERSIZE_MASK (0xfff << GPDMA_C2CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C2CONTROL_TRANSFERSIZE(x) ((x) << GPDMA_C2CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C2CONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_C2CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C2CONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_C2CONTROL_TRANSFERSIZE_SHIFT) /* SBSIZE: Source burst size */ #define GPDMA_C2CONTROL_SBSIZE_SHIFT (12) @@ -748,17 +815,22 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C2CONTROL_DI_MASK (0x1 << GPDMA_C2CONTROL_DI_SHIFT) #define GPDMA_C2CONTROL_DI(x) ((x) << GPDMA_C2CONTROL_DI_SHIFT) -/* PROT1: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode */ +/* PROT1: This information is provided to the peripheral during a DMA bus + access and indicates that the access is in user mode or privileged mode */ #define GPDMA_C2CONTROL_PROT1_SHIFT (28) #define GPDMA_C2CONTROL_PROT1_MASK (0x1 << GPDMA_C2CONTROL_PROT1_SHIFT) #define GPDMA_C2CONTROL_PROT1(x) ((x) << GPDMA_C2CONTROL_PROT1_SHIFT) -/* PROT2: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable */ +/* PROT2: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is bufferable or not + bufferable */ #define GPDMA_C2CONTROL_PROT2_SHIFT (29) #define GPDMA_C2CONTROL_PROT2_MASK (0x1 << GPDMA_C2CONTROL_PROT2_SHIFT) #define GPDMA_C2CONTROL_PROT2(x) ((x) << GPDMA_C2CONTROL_PROT2_SHIFT) -/* PROT3: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable */ +/* PROT3: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is cacheable or not + cacheable */ #define GPDMA_C2CONTROL_PROT3_SHIFT (30) #define GPDMA_C2CONTROL_PROT3_MASK (0x1 << GPDMA_C2CONTROL_PROT3_SHIFT) #define GPDMA_C2CONTROL_PROT3(x) ((x) << GPDMA_C2CONTROL_PROT3_SHIFT) @@ -772,8 +844,10 @@ LGPL License Terms @ref lgpl_license /* TRANSFERSIZE: Transfer size in number of transfers */ #define GPDMA_C3CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C3CONTROL_TRANSFERSIZE_MASK (0xfff << GPDMA_C3CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C3CONTROL_TRANSFERSIZE(x) ((x) << GPDMA_C3CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C3CONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_C3CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C3CONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_C3CONTROL_TRANSFERSIZE_SHIFT) /* SBSIZE: Source burst size */ #define GPDMA_C3CONTROL_SBSIZE_SHIFT (12) @@ -815,17 +889,22 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C3CONTROL_DI_MASK (0x1 << GPDMA_C3CONTROL_DI_SHIFT) #define GPDMA_C3CONTROL_DI(x) ((x) << GPDMA_C3CONTROL_DI_SHIFT) -/* PROT1: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode */ +/* PROT1: This information is provided to the peripheral during a DMA bus + access and indicates that the access is in user mode or privileged mode */ #define GPDMA_C3CONTROL_PROT1_SHIFT (28) #define GPDMA_C3CONTROL_PROT1_MASK (0x1 << GPDMA_C3CONTROL_PROT1_SHIFT) #define GPDMA_C3CONTROL_PROT1(x) ((x) << GPDMA_C3CONTROL_PROT1_SHIFT) -/* PROT2: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable */ +/* PROT2: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is bufferable or + not bufferable */ #define GPDMA_C3CONTROL_PROT2_SHIFT (29) #define GPDMA_C3CONTROL_PROT2_MASK (0x1 << GPDMA_C3CONTROL_PROT2_SHIFT) #define GPDMA_C3CONTROL_PROT2(x) ((x) << GPDMA_C3CONTROL_PROT2_SHIFT) -/* PROT3: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable */ +/* PROT3: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is cacheable or not + cacheable */ #define GPDMA_C3CONTROL_PROT3_SHIFT (30) #define GPDMA_C3CONTROL_PROT3_MASK (0x1 << GPDMA_C3CONTROL_PROT3_SHIFT) #define GPDMA_C3CONTROL_PROT3(x) ((x) << GPDMA_C3CONTROL_PROT3_SHIFT) @@ -839,8 +918,10 @@ LGPL License Terms @ref lgpl_license /* TRANSFERSIZE: Transfer size in number of transfers */ #define GPDMA_C4CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C4CONTROL_TRANSFERSIZE_MASK (0xfff << GPDMA_C4CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C4CONTROL_TRANSFERSIZE(x) ((x) << GPDMA_C4CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C4CONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_C4CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C4CONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_C4CONTROL_TRANSFERSIZE_SHIFT) /* SBSIZE: Source burst size */ #define GPDMA_C4CONTROL_SBSIZE_SHIFT (12) @@ -882,17 +963,22 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C4CONTROL_DI_MASK (0x1 << GPDMA_C4CONTROL_DI_SHIFT) #define GPDMA_C4CONTROL_DI(x) ((x) << GPDMA_C4CONTROL_DI_SHIFT) -/* PROT1: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode */ +/* PROT1: This information is provided to the peripheral during a DMA bus + access and indicates that the access is in user mode or privileged mode */ #define GPDMA_C4CONTROL_PROT1_SHIFT (28) #define GPDMA_C4CONTROL_PROT1_MASK (0x1 << GPDMA_C4CONTROL_PROT1_SHIFT) #define GPDMA_C4CONTROL_PROT1(x) ((x) << GPDMA_C4CONTROL_PROT1_SHIFT) -/* PROT2: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable */ +/* PROT2: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is bufferable or + not bufferable */ #define GPDMA_C4CONTROL_PROT2_SHIFT (29) #define GPDMA_C4CONTROL_PROT2_MASK (0x1 << GPDMA_C4CONTROL_PROT2_SHIFT) #define GPDMA_C4CONTROL_PROT2(x) ((x) << GPDMA_C4CONTROL_PROT2_SHIFT) -/* PROT3: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable */ +/* PROT3: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is cacheable or not + cacheable */ #define GPDMA_C4CONTROL_PROT3_SHIFT (30) #define GPDMA_C4CONTROL_PROT3_MASK (0x1 << GPDMA_C4CONTROL_PROT3_SHIFT) #define GPDMA_C4CONTROL_PROT3(x) ((x) << GPDMA_C4CONTROL_PROT3_SHIFT) @@ -906,8 +992,10 @@ LGPL License Terms @ref lgpl_license /* TRANSFERSIZE: Transfer size in number of transfers */ #define GPDMA_C5CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C5CONTROL_TRANSFERSIZE_MASK (0xfff << GPDMA_C5CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C5CONTROL_TRANSFERSIZE(x) ((x) << GPDMA_C5CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C5CONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_C5CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C5CONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_C5CONTROL_TRANSFERSIZE_SHIFT) /* SBSIZE: Source burst size */ #define GPDMA_C5CONTROL_SBSIZE_SHIFT (12) @@ -949,17 +1037,22 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C5CONTROL_DI_MASK (0x1 << GPDMA_C5CONTROL_DI_SHIFT) #define GPDMA_C5CONTROL_DI(x) ((x) << GPDMA_C5CONTROL_DI_SHIFT) -/* PROT1: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode */ +/* PROT1: This information is provided to the peripheral during a DMA bus + access and indicates that the access is in user mode or privileged mode */ #define GPDMA_C5CONTROL_PROT1_SHIFT (28) #define GPDMA_C5CONTROL_PROT1_MASK (0x1 << GPDMA_C5CONTROL_PROT1_SHIFT) #define GPDMA_C5CONTROL_PROT1(x) ((x) << GPDMA_C5CONTROL_PROT1_SHIFT) -/* PROT2: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable */ +/* PROT2: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is bufferable or + not bufferable */ #define GPDMA_C5CONTROL_PROT2_SHIFT (29) #define GPDMA_C5CONTROL_PROT2_MASK (0x1 << GPDMA_C5CONTROL_PROT2_SHIFT) #define GPDMA_C5CONTROL_PROT2(x) ((x) << GPDMA_C5CONTROL_PROT2_SHIFT) -/* PROT3: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable */ +/* PROT3: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is cacheable or not + cacheable */ #define GPDMA_C5CONTROL_PROT3_SHIFT (30) #define GPDMA_C5CONTROL_PROT3_MASK (0x1 << GPDMA_C5CONTROL_PROT3_SHIFT) #define GPDMA_C5CONTROL_PROT3(x) ((x) << GPDMA_C5CONTROL_PROT3_SHIFT) @@ -973,8 +1066,10 @@ LGPL License Terms @ref lgpl_license /* TRANSFERSIZE: Transfer size in number of transfers */ #define GPDMA_C6CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C6CONTROL_TRANSFERSIZE_MASK (0xfff << GPDMA_C6CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C6CONTROL_TRANSFERSIZE(x) ((x) << GPDMA_C6CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C6CONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_C6CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C6CONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_C6CONTROL_TRANSFERSIZE_SHIFT) /* SBSIZE: Source burst size */ #define GPDMA_C6CONTROL_SBSIZE_SHIFT (12) @@ -1016,17 +1111,22 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C6CONTROL_DI_MASK (0x1 << GPDMA_C6CONTROL_DI_SHIFT) #define GPDMA_C6CONTROL_DI(x) ((x) << GPDMA_C6CONTROL_DI_SHIFT) -/* PROT1: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode */ +/* PROT1: This information is provided to the peripheral during a DMA bus + access and indicates that the access is in user mode or privileged mode */ #define GPDMA_C6CONTROL_PROT1_SHIFT (28) #define GPDMA_C6CONTROL_PROT1_MASK (0x1 << GPDMA_C6CONTROL_PROT1_SHIFT) #define GPDMA_C6CONTROL_PROT1(x) ((x) << GPDMA_C6CONTROL_PROT1_SHIFT) -/* PROT2: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable */ +/* PROT2: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is bufferable or not + bufferable */ #define GPDMA_C6CONTROL_PROT2_SHIFT (29) #define GPDMA_C6CONTROL_PROT2_MASK (0x1 << GPDMA_C6CONTROL_PROT2_SHIFT) #define GPDMA_C6CONTROL_PROT2(x) ((x) << GPDMA_C6CONTROL_PROT2_SHIFT) -/* PROT3: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable */ +/* PROT3: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is cacheable or + not cacheable */ #define GPDMA_C6CONTROL_PROT3_SHIFT (30) #define GPDMA_C6CONTROL_PROT3_MASK (0x1 << GPDMA_C6CONTROL_PROT3_SHIFT) #define GPDMA_C6CONTROL_PROT3(x) ((x) << GPDMA_C6CONTROL_PROT3_SHIFT) @@ -1040,8 +1140,10 @@ LGPL License Terms @ref lgpl_license /* TRANSFERSIZE: Transfer size in number of transfers */ #define GPDMA_C7CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C7CONTROL_TRANSFERSIZE_MASK (0xfff << GPDMA_C7CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C7CONTROL_TRANSFERSIZE(x) ((x) << GPDMA_C7CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C7CONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_C7CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_C7CONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_C7CONTROL_TRANSFERSIZE_SHIFT) /* SBSIZE: Source burst size */ #define GPDMA_C7CONTROL_SBSIZE_SHIFT (12) @@ -1083,17 +1185,22 @@ LGPL License Terms @ref lgpl_license #define GPDMA_C7CONTROL_DI_MASK (0x1 << GPDMA_C7CONTROL_DI_SHIFT) #define GPDMA_C7CONTROL_DI(x) ((x) << GPDMA_C7CONTROL_DI_SHIFT) -/* PROT1: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode */ +/* PROT1: This information is provided to the peripheral during a DMA bus + access and indicates that the access is in user mode or privileged mode */ #define GPDMA_C7CONTROL_PROT1_SHIFT (28) #define GPDMA_C7CONTROL_PROT1_MASK (0x1 << GPDMA_C7CONTROL_PROT1_SHIFT) #define GPDMA_C7CONTROL_PROT1(x) ((x) << GPDMA_C7CONTROL_PROT1_SHIFT) -/* PROT2: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable */ +/* PROT2: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is bufferable or + not bufferable */ #define GPDMA_C7CONTROL_PROT2_SHIFT (29) #define GPDMA_C7CONTROL_PROT2_MASK (0x1 << GPDMA_C7CONTROL_PROT2_SHIFT) #define GPDMA_C7CONTROL_PROT2(x) ((x) << GPDMA_C7CONTROL_PROT2_SHIFT) -/* PROT3: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable */ +/* PROT3: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is cacheable or not + cacheable */ #define GPDMA_C7CONTROL_PROT3_SHIFT (30) #define GPDMA_C7CONTROL_PROT3_MASK (0x1 << GPDMA_C7CONTROL_PROT3_SHIFT) #define GPDMA_C7CONTROL_PROT3(x) ((x) << GPDMA_C7CONTROL_PROT3_SHIFT) @@ -1112,13 +1219,17 @@ LGPL License Terms @ref lgpl_license /* SRCPERIPHERAL: Source peripheral */ #define GPDMA_C0CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C0CONFIG_SRCPERIPHERAL_MASK (0x1f << GPDMA_C0CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C0CONFIG_SRCPERIPHERAL(x) ((x) << GPDMA_C0CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C0CONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_C0CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C0CONFIG_SRCPERIPHERAL(x) + ((x) << GPDMA_C0CONFIG_SRCPERIPHERAL_SHIFT) /* DESTPERIPHERAL: Destination peripheral */ #define GPDMA_C0CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C0CONFIG_DESTPERIPHERAL_MASK (0x1f << GPDMA_C0CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C0CONFIG_DESTPERIPHERAL(x) ((x) << GPDMA_C0CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C0CONFIG_DESTPERIPHERAL_MASK + (0x1f << GPDMA_C0CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C0CONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_C0CONFIG_DESTPERIPHERAL_SHIFT) /* FLOWCNTRL: Flow control and transfer type */ #define GPDMA_C0CONFIG_FLOWCNTRL_SHIFT (11) @@ -1159,13 +1270,17 @@ LGPL License Terms @ref lgpl_license /* SRCPERIPHERAL: Source peripheral */ #define GPDMA_C1CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C1CONFIG_SRCPERIPHERAL_MASK (0x1f << GPDMA_C1CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C1CONFIG_SRCPERIPHERAL(x) ((x) << GPDMA_C1CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C1CONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_C1CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C1CONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_C1CONFIG_SRCPERIPHERAL_SHIFT) /* DESTPERIPHERAL: Destination peripheral */ #define GPDMA_C1CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C1CONFIG_DESTPERIPHERAL_MASK (0x1f << GPDMA_C1CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C1CONFIG_DESTPERIPHERAL(x) ((x) << GPDMA_C1CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C1CONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_C1CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C1CONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_C1CONFIG_DESTPERIPHERAL_SHIFT) /* FLOWCNTRL: Flow control and transfer type */ #define GPDMA_C1CONFIG_FLOWCNTRL_SHIFT (11) @@ -1206,13 +1321,17 @@ LGPL License Terms @ref lgpl_license /* SRCPERIPHERAL: Source peripheral */ #define GPDMA_C2CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C2CONFIG_SRCPERIPHERAL_MASK (0x1f << GPDMA_C2CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C2CONFIG_SRCPERIPHERAL(x) ((x) << GPDMA_C2CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C2CONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_C2CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C2CONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_C2CONFIG_SRCPERIPHERAL_SHIFT) /* DESTPERIPHERAL: Destination peripheral */ #define GPDMA_C2CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C2CONFIG_DESTPERIPHERAL_MASK (0x1f << GPDMA_C2CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C2CONFIG_DESTPERIPHERAL(x) ((x) << GPDMA_C2CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C2CONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_C2CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C2CONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_C2CONFIG_DESTPERIPHERAL_SHIFT) /* FLOWCNTRL: Flow control and transfer type */ #define GPDMA_C2CONFIG_FLOWCNTRL_SHIFT (11) @@ -1253,13 +1372,17 @@ LGPL License Terms @ref lgpl_license /* SRCPERIPHERAL: Source peripheral */ #define GPDMA_C3CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C3CONFIG_SRCPERIPHERAL_MASK (0x1f << GPDMA_C3CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C3CONFIG_SRCPERIPHERAL(x) ((x) << GPDMA_C3CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C3CONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_C3CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C3CONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_C3CONFIG_SRCPERIPHERAL_SHIFT) /* DESTPERIPHERAL: Destination peripheral */ #define GPDMA_C3CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C3CONFIG_DESTPERIPHERAL_MASK (0x1f << GPDMA_C3CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C3CONFIG_DESTPERIPHERAL(x) ((x) << GPDMA_C3CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C3CONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_C3CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C3CONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_C3CONFIG_DESTPERIPHERAL_SHIFT) /* FLOWCNTRL: Flow control and transfer type */ #define GPDMA_C3CONFIG_FLOWCNTRL_SHIFT (11) @@ -1300,13 +1423,17 @@ LGPL License Terms @ref lgpl_license /* SRCPERIPHERAL: Source peripheral */ #define GPDMA_C4CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C4CONFIG_SRCPERIPHERAL_MASK (0x1f << GPDMA_C4CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C4CONFIG_SRCPERIPHERAL(x) ((x) << GPDMA_C4CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C4CONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_C4CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C4CONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_C4CONFIG_SRCPERIPHERAL_SHIFT) /* DESTPERIPHERAL: Destination peripheral */ #define GPDMA_C4CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C4CONFIG_DESTPERIPHERAL_MASK (0x1f << GPDMA_C4CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C4CONFIG_DESTPERIPHERAL(x) ((x) << GPDMA_C4CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C4CONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_C4CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C4CONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_C4CONFIG_DESTPERIPHERAL_SHIFT) /* FLOWCNTRL: Flow control and transfer type */ #define GPDMA_C4CONFIG_FLOWCNTRL_SHIFT (11) @@ -1347,13 +1474,17 @@ LGPL License Terms @ref lgpl_license /* SRCPERIPHERAL: Source peripheral */ #define GPDMA_C5CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C5CONFIG_SRCPERIPHERAL_MASK (0x1f << GPDMA_C5CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C5CONFIG_SRCPERIPHERAL(x) ((x) << GPDMA_C5CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C5CONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_C5CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C5CONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_C5CONFIG_SRCPERIPHERAL_SHIFT) /* DESTPERIPHERAL: Destination peripheral */ #define GPDMA_C5CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C5CONFIG_DESTPERIPHERAL_MASK (0x1f << GPDMA_C5CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C5CONFIG_DESTPERIPHERAL(x) ((x) << GPDMA_C5CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C5CONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_C5CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C5CONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_C5CONFIG_DESTPERIPHERAL_SHIFT) /* FLOWCNTRL: Flow control and transfer type */ #define GPDMA_C5CONFIG_FLOWCNTRL_SHIFT (11) @@ -1394,13 +1525,17 @@ LGPL License Terms @ref lgpl_license /* SRCPERIPHERAL: Source peripheral */ #define GPDMA_C6CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C6CONFIG_SRCPERIPHERAL_MASK (0x1f << GPDMA_C6CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C6CONFIG_SRCPERIPHERAL(x) ((x) << GPDMA_C6CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C6CONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_C6CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C6CONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_C6CONFIG_SRCPERIPHERAL_SHIFT) /* DESTPERIPHERAL: Destination peripheral */ #define GPDMA_C6CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C6CONFIG_DESTPERIPHERAL_MASK (0x1f << GPDMA_C6CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C6CONFIG_DESTPERIPHERAL(x) ((x) << GPDMA_C6CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C6CONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_C6CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C6CONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_C6CONFIG_DESTPERIPHERAL_SHIFT) /* FLOWCNTRL: Flow control and transfer type */ #define GPDMA_C6CONFIG_FLOWCNTRL_SHIFT (11) @@ -1441,13 +1576,17 @@ LGPL License Terms @ref lgpl_license /* SRCPERIPHERAL: Source peripheral */ #define GPDMA_C7CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C7CONFIG_SRCPERIPHERAL_MASK (0x1f << GPDMA_C7CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C7CONFIG_SRCPERIPHERAL(x) ((x) << GPDMA_C7CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C7CONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_C7CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_C7CONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_C7CONFIG_SRCPERIPHERAL_SHIFT) /* DESTPERIPHERAL: Destination peripheral */ #define GPDMA_C7CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C7CONFIG_DESTPERIPHERAL_MASK (0x1f << GPDMA_C7CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C7CONFIG_DESTPERIPHERAL(x) ((x) << GPDMA_C7CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C7CONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_C7CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_C7CONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_C7CONFIG_DESTPERIPHERAL_SHIFT) /* FLOWCNTRL: Flow control and transfer type */ #define GPDMA_C7CONFIG_FLOWCNTRL_SHIFT (11) diff --git a/include/libopencm3/lpc43xx/gpio.h b/include/libopencm3/lpc43xx/gpio.h index 17214570..78e94bdb 100644 --- a/include/libopencm3/lpc43xx/gpio.h +++ b/include/libopencm3/lpc43xx/gpio.h @@ -123,108 +123,142 @@ LGPL License Terms @ref lgpl_license /* GPIO GROUP0 interrupt */ /* GPIO grouped interrupt control register */ -#define GPIO_GROUP0_INTERRUPT_CTRL MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x000) +#define GPIO_GROUP0_INTERRUPT_CTRL \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x000) /* GPIO grouped interrupt port 0 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL0 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020) +#define GPIO_GROUP0_INTERRUPT_PORT_POL0 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020) /* GPIO grouped interrupt port 1 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL1 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x024) +#define GPIO_GROUP0_INTERRUPT_PORT_POL1 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x024) /* GPIO grouped interrupt port 2 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL2 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x028) +#define GPIO_GROUP0_INTERRUPT_PORT_POL2 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x028) /* GPIO grouped interrupt port 3 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL3 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x02C) +#define GPIO_GROUP0_INTERRUPT_PORT_POL3 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x02C) /* GPIO grouped interrupt port 4 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL4 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x030) +#define GPIO_GROUP0_INTERRUPT_PORT_POL4 + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x030) /* GPIO grouped interrupt port 5 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL5 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x034) +#define GPIO_GROUP0_INTERRUPT_PORT_POL5 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x034) /* GPIO grouped interrupt port 6 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL6 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x038) +#define GPIO_GROUP0_INTERRUPT_PORT_POL6 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x038) /* GPIO grouped interrupt port 7 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL7 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x03C) +#define GPIO_GROUP0_INTERRUPT_PORT_POL7 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x03C) /* GPIO grouped interrupt port 0 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA0 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040) +#define GPIO_GROUP0_INTERRUPT_PORT_ENA0 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040) /* GPIO grouped interrupt port 1 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA1 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x044) +#define GPIO_GROUP0_INTERRUPT_PORT_ENA1 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x044) /* GPIO grouped interrupt port 2 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA2 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x048) +#define GPIO_GROUP0_INTERRUPT_PORT_ENA2 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x048) /* GPIO grouped interrupt port 3 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA3 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x04C) +#define GPIO_GROUP0_INTERRUPT_PORT_ENA3 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x04C) /* GPIO grouped interrupt port 4 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA4 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x050) +#define GPIO_GROUP0_INTERRUPT_PORT_ENA4 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x050) /* GPIO grouped interrupt port 5 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA5 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x054) +#define GPIO_GROUP0_INTERRUPT_PORT_ENA5 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x054) /* GPIO grouped interrupt port 6 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA6 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x058) +#define GPIO_GROUP0_INTERRUPT_PORT_ENA6 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x058) /* GPIO grouped interrupt port 7 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA7 MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x05C) +#define GPIO_GROUP0_INTERRUPT_PORT_ENA7 \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x05C) /* GPIO GROUP1 interrupt */ /* GPIO grouped interrupt control register */ -#define GPIO_GROUP1_INTERRUPT_CTRL MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x000) +#define GPIO_GROUP1_INTERRUPT_CTRL \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x000) /* GPIO grouped interrupt port 0 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL0 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020) +#define GPIO_GROUP1_INTERRUPT_PORT_POL0 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020) /* GPIO grouped interrupt port 1 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL1 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x024) +#define GPIO_GROUP1_INTERRUPT_PORT_POL1 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x024) /* GPIO grouped interrupt port 2 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL2 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x028) +#define GPIO_GROUP1_INTERRUPT_PORT_POL2 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x028) /* GPIO grouped interrupt port 3 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL3 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x02C) +#define GPIO_GROUP1_INTERRUPT_PORT_POL3 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x02C) /* GPIO grouped interrupt port 4 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL4 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x030) +#define GPIO_GROUP1_INTERRUPT_PORT_POL4 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x030) /* GPIO grouped interrupt port 5 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL5 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x034) +#define GPIO_GROUP1_INTERRUPT_PORT_POL5 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x034) /* GPIO grouped interrupt port 6 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL6 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x038) +#define GPIO_GROUP1_INTERRUPT_PORT_POL6 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x038) /* GPIO grouped interrupt port 7 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL7 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x03C) +#define GPIO_GROUP1_INTERRUPT_PORT_POL7 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x03C) /* GPIO grouped interrupt port 0 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA0 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040) +#define GPIO_GROUP1_INTERRUPT_PORT_ENA0 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040) /* GPIO grouped interrupt port 1 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA1 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x044) +#define GPIO_GROUP1_INTERRUPT_PORT_ENA1 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x044) /* GPIO grouped interrupt port 2 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA2 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x048) +#define GPIO_GROUP1_INTERRUPT_PORT_ENA2 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x048) /* GPIO grouped interrupt port 3 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA3 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x04C) +#define GPIO_GROUP1_INTERRUPT_PORT_ENA3 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x04C) /* GPIO grouped interrupt port 4 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA4 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x050) +#define GPIO_GROUP1_INTERRUPT_PORT_ENA4 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x050) /* GPIO grouped interrupt port 5 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA5 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x054) +#define GPIO_GROUP1_INTERRUPT_PORT_ENA5 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x054) /* GPIO grouped interrupt port 6 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA6 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x058) +#define GPIO_GROUP1_INTERRUPT_PORT_ENA6 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x058) /* GPIO grouped interrupt port 7 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA7 MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x05C) +#define GPIO_GROUP1_INTERRUPT_PORT_ENA7 \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x05C) /* Byte pin registers port 0; pins PIO0_0 to PIO0_31 (R/W) */ #define GPIO_B0 (GPIO_PORT_BASE + 0x0000) diff --git a/include/libopencm3/lpc43xx/rgu.h b/include/libopencm3/lpc43xx/rgu.h index 09338c8c..0ec01466 100644 --- a/include/libopencm3/lpc43xx/rgu.h +++ b/include/libopencm3/lpc43xx/rgu.h @@ -517,7 +517,8 @@ LGPL License Terms @ref lgpl_license /* ETHERNET_RST: Status of the ETHERNET_RST reset generator output */ #define RESET_STATUS1_ETHERNET_RST_SHIFT (12) -#define RESET_STATUS1_ETHERNET_RST_MASK (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT) +#define RESET_STATUS1_ETHERNET_RST_MASK \ + (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT) #define RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT) /* FLASHA_RST: Status of the FLASHA_RST reset generator output */ @@ -574,8 +575,10 @@ LGPL License Terms @ref lgpl_license /* MOTOCONPWM_RST: Status of the MOTOCONPWM_RST reset generator output */ #define RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12) -#define RESET_STATUS2_MOTOCONPWM_RST_MASK (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) -#define RESET_STATUS2_MOTOCONPWM_RST(x) ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) +#define RESET_STATUS2_MOTOCONPWM_RST_MASK \ + (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) +#define RESET_STATUS2_MOTOCONPWM_RST(x) \ + ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) /* QEI_RST: Status of the QEI_RST reset generator output */ #define RESET_STATUS2_QEI_RST_SHIFT (14) @@ -682,11 +685,13 @@ LGPL License Terms @ref lgpl_license /* PERIPH_RST: Current status of the PERIPH_RST */ #define RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1) -#define RESET_ACTIVE_STATUS0_PERIPH_RST (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT) +#define RESET_ACTIVE_STATUS0_PERIPH_RST \ + (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT) /* MASTER_RST: Current status of the MASTER_RST */ #define RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2) -#define RESET_ACTIVE_STATUS0_MASTER_RST (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT) +#define RESET_ACTIVE_STATUS0_MASTER_RST \ + (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT) /* WWDT_RST: Current status of the WWDT_RST */ #define RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4) @@ -734,15 +739,18 @@ LGPL License Terms @ref lgpl_license /* ETHERNET_RST: Current status of the ETHERNET_RST */ #define RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22) -#define RESET_ACTIVE_STATUS0_ETHERNET_RST (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT) +#define RESET_ACTIVE_STATUS0_ETHERNET_RST \ + (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT) /* FLASHA_RST: Current status of the FLASHA_RST */ #define RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25) -#define RESET_ACTIVE_STATUS0_FLASHA_RST (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT) +#define RESET_ACTIVE_STATUS0_FLASHA_RST \ + (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT) /* EEPROM_RST: Current status of the EEPROM_RST */ #define RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27) -#define RESET_ACTIVE_STATUS0_EEPROM_RST (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT) +#define RESET_ACTIVE_STATUS0_EEPROM_RST \ + (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT) /* GPIO_RST: Current status of the GPIO_RST */ #define RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28) @@ -750,49 +758,60 @@ LGPL License Terms @ref lgpl_license /* FLASHB_RST: Current status of the FLASHB_RST */ #define RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29) -#define RESET_ACTIVE_STATUS0_FLASHB_RST (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT) +#define RESET_ACTIVE_STATUS0_FLASHB_RST \ + (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT) /* --- RESET_ACTIVE_STATUS1 values ------------------------------ */ /* TIMER0_RST: Current status of the TIMER0_RST */ #define RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0) -#define RESET_ACTIVE_STATUS1_TIMER0_RST (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_TIMER0_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT) /* TIMER1_RST: Current status of the TIMER1_RST */ #define RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1) -#define RESET_ACTIVE_STATUS1_TIMER1_RST (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_TIMER1_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT) /* TIMER2_RST: Current status of the TIMER2_RST */ #define RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2) -#define RESET_ACTIVE_STATUS1_TIMER2_RST (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_TIMER2_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT) /* TIMER3_RST: Current status of the TIMER3_RST */ #define RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3) -#define RESET_ACTIVE_STATUS1_TIMER3_RST (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_TIMER3_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT) /* RITIMER_RST: Current status of the RITIMER_RST */ #define RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4) -#define RESET_ACTIVE_STATUS1_RITIMER_RST (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_RITIMER_RST \ + (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT) /* SCT_RST: Current status of the SCT_RST */ #define RESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5) -#define RESET_ACTIVE_STATUS1_SCT_RST (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_SCT_RST \ + (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT) /* MOTOCONPWM_RST: Current status of the MOTOCONPWM_RST */ #define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6) -#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST \ + (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT) /* QEI_RST: Current status of the QEI_RST */ #define RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7) -#define RESET_ACTIVE_STATUS1_QEI_RST (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_QEI_RST \ + (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT) /* ADC0_RST: Current status of the ADC0_RST */ #define RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8) -#define RESET_ACTIVE_STATUS1_ADC0_RST (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_ADC0_RST \ + (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT) /* ADC1_RST: Current status of the ADC1_RST */ #define RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9) -#define RESET_ACTIVE_STATUS1_ADC1_RST (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_ADC1_RST \ + (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT) /* DAC_RST: Current status of the DAC_RST */ #define RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10) @@ -800,35 +819,43 @@ LGPL License Terms @ref lgpl_license /* UART0_RST: Current status of the UART0_RST */ #define RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12) -#define RESET_ACTIVE_STATUS1_UART0_RST (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_UART0_RST \ + (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT) /* UART1_RST: Current status of the UART1_RST */ #define RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13) -#define RESET_ACTIVE_STATUS1_UART1_RST (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_UART1_RST \ + (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT) /* UART2_RST: Current status of the UART2_RST */ #define RESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14) -#define RESET_ACTIVE_STATUS1_UART2_RST (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_UART2_RST \ + (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT) /* UART3_RST: Current status of the UART3_RST */ #define RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15) -#define RESET_ACTIVE_STATUS1_UART3_RST (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_UART3_RST \ + (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT) /* I2C0_RST: Current status of the I2C0_RST */ #define RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16) -#define RESET_ACTIVE_STATUS1_I2C0_RST (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_I2C0_RST \ + (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT) /* I2C1_RST: Current status of the I2C1_RST */ #define RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17) -#define RESET_ACTIVE_STATUS1_I2C1_RST (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_I2C1_RST \ + (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT) /* SSP0_RST: Current status of the SSP0_RST */ #define RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18) -#define RESET_ACTIVE_STATUS1_SSP0_RST (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_SSP0_RST \ + (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT) /* SSP1_RST: Current status of the SSP1_RST */ #define RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19) -#define RESET_ACTIVE_STATUS1_SSP1_RST (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_SSP1_RST \ + (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT) /* I2S_RST: Current status of the I2S_RST */ #define RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20) @@ -836,23 +863,28 @@ LGPL License Terms @ref lgpl_license /* SPIFI_RST: Current status of the SPIFI_RST */ #define RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21) -#define RESET_ACTIVE_STATUS1_SPIFI_RST (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_SPIFI_RST \ + (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT) /* CAN1_RST: Current status of the CAN1_RST */ #define RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22) -#define RESET_ACTIVE_STATUS1_CAN1_RST (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_CAN1_RST \ + (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT) /* CAN0_RST: Current status of the CAN0_RST */ #define RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23) -#define RESET_ACTIVE_STATUS1_CAN0_RST (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_CAN0_RST \ + (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT) /* M0APP_RST: Current status of the M0APP_RST */ #define RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24) -#define RESET_ACTIVE_STATUS1_M0APP_RST (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_M0APP_RST \ + (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT) /* SGPIO_RST: Current status of the SGPIO_RST */ #define RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25) -#define RESET_ACTIVE_STATUS1_SGPIO_RST (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT) +#define RESET_ACTIVE_STATUS1_SGPIO_RST \ + (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT) /* SPI_RST: Current status of the SPI_RST */ #define RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26) @@ -882,7 +914,8 @@ LGPL License Terms @ref lgpl_license /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT2_PERIPHERAL_RESET (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT2_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT4 values ----------------------------------- */ @@ -900,13 +933,15 @@ LGPL License Terms @ref lgpl_license /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT8_PERIPHERAL_RESET (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT8_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT9 values ----------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT9_PERIPHERAL_RESET (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT9_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT13 values ---------------------------------- */ @@ -960,181 +995,211 @@ LGPL License Terms @ref lgpl_license /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT25_PERIPHERAL_RESET (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT25_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT27 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT27_PERIPHERAL_RESET (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT27_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT28 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT28_PERIPHERAL_RESET (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT28_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT29 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT29_PERIPHERAL_RESET (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT29_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT32 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT32_PERIPHERAL_RESET (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT32_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT33 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT33_PERIPHERAL_RESET (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT33_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT34 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT34_PERIPHERAL_RESET (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT34_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT35 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT35_PERIPHERAL_RESET (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT35_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT36 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT36_PERIPHERAL_RESET (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT36_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT37 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT37_PERIPHERAL_RESET (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT37_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT38 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT38_PERIPHERAL_RESET (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT38_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT39 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT39_PERIPHERAL_RESET (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT39_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT40 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT40_PERIPHERAL_RESET (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT40_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT41 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT41_PERIPHERAL_RESET (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT41_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT42 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT42_PERIPHERAL_RESET (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT42_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT44 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT44_PERIPHERAL_RESET (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT44_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT45 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT45_PERIPHERAL_RESET (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT45_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT46 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT46_PERIPHERAL_RESET (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT46_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT47 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT47_PERIPHERAL_RESET (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT47_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT48 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT48_PERIPHERAL_RESET (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT48_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT49 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT49_PERIPHERAL_RESET (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT49_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT50 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT50_PERIPHERAL_RESET (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT50_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT51 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT51_PERIPHERAL_RESET (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT51_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT52 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT52_PERIPHERAL_RESET (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT52_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT53 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT53_PERIPHERAL_RESET (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT53_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT54 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT54_PERIPHERAL_RESET (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT54_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT55 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT55_PERIPHERAL_RESET (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT55_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT56 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT56_PERIPHERAL_RESET (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT56_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT57 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT57_PERIPHERAL_RESET (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT57_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT) /* --- RESET_EXT_STAT58 values ---------------------------------- */ /* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ #define RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2) -#define RESET_EXT_STAT58_PERIPHERAL_RESET (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT) +#define RESET_EXT_STAT58_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT) /**@}*/ diff --git a/include/libopencm3/lpc43xx/sgpio.h b/include/libopencm3/lpc43xx/sgpio.h index 0a4108b7..82dbcee6 100644 --- a/include/libopencm3/lpc43xx/sgpio.h +++ b/include/libopencm3/lpc43xx/sgpio.h @@ -337,451 +337,609 @@ LGPL License Terms @ref lgpl_license /* --- Common register fields ----------------------------------- */ /* TODO: Generate this stuff with the gen.py script as well! */ -#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) -#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_MASK (1 << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) -#define SGPIO_MUX_CFG_EXT_CLK_ENABLE(x) ((x) << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_MASK \ + (1 << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE(x) \ + ((x) << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) -#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG_QUALIFIER_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_MODE(x) \ + ((x) << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG_CONCAT_ENABLE_MASK (1 << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) -#define SGPIO_MUX_CFG_CONCAT_ENABLE(x) ((x) << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) +#define SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG_CONCAT_ENABLE_MASK \ + (1 << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) +#define SGPIO_MUX_CFG_CONCAT_ENABLE(x) \ + ((x) << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) -#define SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG_CONCAT_ORDER_MASK \ + (0x3 << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG_CONCAT_ORDER(x) \ + ((x) << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) -#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_MASK (1 << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_MATCH_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_MASK (1 << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_MASK (1 << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_MASK (1 << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) -#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(x) ((x) << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) -#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_MASK (1 << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) -#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(x) ((x) << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) -#define SGPIO_POS_POS_SHIFT (0) -#define SGPIO_POS_POS_MASK (0xff << SGPIO_POS_POS_SHIFT) -#define SGPIO_POS_POS(x) ((x) << SGPIO_POS_POS_SHIFT) +#define SGPIO_POS_POS_SHIFT (0) +#define SGPIO_POS_POS_MASK (0xff << SGPIO_POS_POS_SHIFT) +#define SGPIO_POS_POS(x) ((x) << SGPIO_POS_POS_SHIFT) -#define SGPIO_POS_POS_RESET_SHIFT (8) -#define SGPIO_POS_POS_RESET_MASK (0xff << SGPIO_POS_POS_RESET_SHIFT) -#define SGPIO_POS_POS_RESET(x) ((x) << SGPIO_POS_POS_RESET_SHIFT) +#define SGPIO_POS_POS_RESET_SHIFT (8) +#define SGPIO_POS_POS_RESET_MASK (0xff << SGPIO_POS_POS_RESET_SHIFT) +#define SGPIO_POS_POS_RESET(x) ((x) << SGPIO_POS_POS_RESET_SHIFT) /* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ /* --- SGPIO_OUT_MUX_CFG0 values -------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG0_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG0_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG1 values -------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG1_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG1_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG2 values -------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG2_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG2_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG3 values -------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG3_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG3_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG4 values -------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG4_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG4_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG5 values -------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG5_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG5_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG6 values -------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG6_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG6_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG7 values -------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG7_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG7_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG8 values -------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG8_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG8_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG9 values -------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG9_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG9_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG10 values ------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG10_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG10_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG11 values ------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG11_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG11_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG12 values ------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG12_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG12_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG13 values ------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG13_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG13_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG14 values ------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG14_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG14_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT) /* --- SGPIO_OUT_MUX_CFG15 values ------------------------------- */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_MASK (0xf << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG(x) ((x) << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_MASK (0x7 << SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG15_P_OE_CFG(x) ((x) << SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG15_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT) /* --- SGPIO_MUX_CFG0 values ------------------------------------ */ /* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG0_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG0_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG0_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFG0_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG0_EXT_CLK_ENABLE \ + (1 << SGPIO_MUX_CFG0_EXT_CLK_ENABLE_SHIFT) /* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT) /* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE(x) + ((x) << SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT) /* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG0_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG0_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG0_QUALIFIER_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG0_QUALIFIER_MODE(x) \ + ((x) << SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT) /* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT) /* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) /* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG0_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG0_CONCAT_ENABLE_SHIFT (11) #define SGPIO_MUX_CFG0_CONCAT_ENABLE (1 << SGPIO_MUX_CFG0_CONCAT_ENABLE_SHIFT) /* CONCAT_ORDER: Select concatenation order */ #define SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG0_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG0_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG0_CONCAT_ORDER_MASK \ + (0x3 << SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG0_CONCAT_ORDER(x) \ + ((x) << SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT) /* --- SGPIO_MUX_CFG1 values ------------------------------------ */ /* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG1_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG1_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG1_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFG1_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG1_EXT_CLK_ENABLE \ + (1 << SGPIO_MUX_CFG1_EXT_CLK_ENABLE_SHIFT) /* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT) /* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT) /* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG1_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG1_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG1_QUALIFIER_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG1_QUALIFIER_MODE(x) \ + ((x) << SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT) /* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT) /* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT) /* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG1_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG1_CONCAT_ENABLE (1 << SGPIO_MUX_CFG1_CONCAT_ENABLE_SHIFT) +#define SGPIO_MUX_CFG1_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG1_CONCAT_ENABLE \ + (1 << SGPIO_MUX_CFG1_CONCAT_ENABLE_SHIFT) /* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG1_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG1_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG1_CONCAT_ORDER_MASK \ + (0x3 << SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG1_CONCAT_ORDER(x) \ + ((x) << SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT) /* --- SGPIO_MUX_CFG2 values ------------------------------------ */ /* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG2_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG2_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG2_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFG2_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG2_EXT_CLK_ENABLE \ + (1 << SGPIO_MUX_CFG2_EXT_CLK_ENABLE_SHIFT) /* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT) /* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT) /* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG2_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG2_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG2_QUALIFIER_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG2_QUALIFIER_MODE(x) \ + ((x) << SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT) /* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT) /* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT) /* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG2_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG2_CONCAT_ENABLE (1 << SGPIO_MUX_CFG2_CONCAT_ENABLE_SHIFT) +#define SGPIO_MUX_CFG2_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG2_CONCAT_ENABLE + (1 << SGPIO_MUX_CFG2_CONCAT_ENABLE_SHIFT) /* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG2_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG2_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG2_CONCAT_ORDER_MASK \ + (0x3 << SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG2_CONCAT_ORDER(x) \ + ((x) << SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT) /* --- SGPIO_MUX_CFG3 values ------------------------------------ */ /* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG3_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG3_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG3_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFG3_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG3_EXT_CLK_ENABLE \ + (1 << SGPIO_MUX_CFG3_EXT_CLK_ENABLE_SHIFT) /* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT) /* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT) /* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG3_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG3_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG3_QUALIFIER_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG3_QUALIFIER_MODE(x) \ + ((x) << SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT) /* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT) /* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT) /* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG3_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG3_CONCAT_ENABLE (1 << SGPIO_MUX_CFG3_CONCAT_ENABLE_SHIFT) +#define SGPIO_MUX_CFG3_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG3_CONCAT_ENABLE \ + (1 << SGPIO_MUX_CFG3_CONCAT_ENABLE_SHIFT) /* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG3_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG3_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG3_CONCAT_ORDER_MASK \ + (0x3 << SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG3_CONCAT_ORDER(x) \ + ((x) << SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT) /* --- SGPIO_MUX_CFG4 values ------------------------------------ */ /* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG4_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG4_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG4_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFG4_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG4_EXT_CLK_ENABLE \ + (1 << SGPIO_MUX_CFG4_EXT_CLK_ENABLE_SHIFT) /* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT) /* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT) /* QUALIFIER_MODE: Select qualifier mode */ #define SGPIO_MUX_CFG4_QUALIFIER_MODE_SHIFT (5) diff --git a/include/libopencm3/lpc43xx/timer.h b/include/libopencm3/lpc43xx/timer.h index 5a649ccc..2c691e7b 100644 --- a/include/libopencm3/lpc43xx/timer.h +++ b/include/libopencm3/lpc43xx/timer.h @@ -180,12 +180,12 @@ LGPL License Terms @ref lgpl_license #define TIMER_IR_CR2INT (1 << 6) #define TIMER_IR_CR3INT (1 << 7) -/* --- TIMERx_TCR values ----------------------------------------------------- */ +/* --- TIMERx_TCR values --------------------------------------------------- */ #define TIMER_TCR_CEN (1 << 0) #define TIMER_TCR_CRST (1 << 1) -/* --- TIMERx_MCR values ----------------------------------------------------- */ +/* --- TIMERx_MCR values --------------------------------------------------- */ #define TIMER_MCR_MR0I (1 << 0) #define TIMER_MCR_MR0R (1 << 1) @@ -200,7 +200,7 @@ LGPL License Terms @ref lgpl_license #define TIMER_MCR_MR3R (1 << 10) #define TIMER_MCR_MR3S (1 << 11) -/* --- TIMERx_MCR values ----------------------------------------------------- */ +/* --- TIMERx_MCR values --------------------------------------------------- */ #define TIMER_CCR_CAP0RE (1 << 0) #define TIMER_CCR_CAP0FE (1 << 1) @@ -215,7 +215,7 @@ LGPL License Terms @ref lgpl_license #define TIMER_CCR_CAP3FE (1 << 10) #define TIMER_CCR_CAP3I (1 << 11) -/* --- TIMERx_EMR values ----------------------------------------------------- */ +/* --- TIMERx_EMR values --------------------------------------------------- */ #define TIMER_EMR_EM0 (1 << 0) #define TIMER_EMR_EM1 (1 << 1) @@ -235,7 +235,7 @@ LGPL License Terms @ref lgpl_license #define TIMER_EMR_EMC_SET 0x2 #define TIMER_EMR_EMC_TOGGLE 0x3 -/* --- TIMERx_CTCR values ---------------------------------------------------- */ +/* --- TIMERx_CTCR values -------------------------------------------------- */ #define TIMER_CTCR_MODE_TIMER (0x0 << 0) #define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) @@ -249,7 +249,7 @@ LGPL License Terms @ref lgpl_license #define TIMER_CTCR_CINSEL_CAPN_3 (0x3 << 2) #define TIMER_CTCR_CINSEL_MASK (0x3 << 2) -/* --- TIMER function prototypes --------------------------------------------- */ +/* --- TIMER function prototypes ------------------------------------------- */ BEGIN_DECLS diff --git a/include/libopencm3/lpc43xx/uart.h b/include/libopencm3/lpc43xx/uart.h index 2fc5fff6..d90b501d 100644 --- a/include/libopencm3/lpc43xx/uart.h +++ b/include/libopencm3/lpc43xx/uart.h @@ -95,171 +95,270 @@ /* Transmit Enable Register */ #define UART_TER(port) MMIO32(port + 0x05C) -/* --------------------- BIT DEFINITIONS -------------------------------------- */ +/* --------------------- BIT DEFINITIONS ----------------------------------- */ /*********************************************************************** * Macro defines for Macro defines for UARTn Receiver Buffer Register **********************************************************************/ -#define UART_RBR_MASKBIT ((uint8_t)0xFF) /* UART Received Buffer mask bit (8 bits) */ +/* UART Received Buffer mask bit (8 bits) */ +#define UART_RBR_MASKBIT ((uint8_t)0xFF) /*********************************************************************** * Macro defines for Macro defines for UARTn Transmit Holding Register **********************************************************************/ -#define UART_THR_MASKBIT ((uint8_t)0xFF) /* UART Transmit Holding mask bit (8 bits) */ +/* UART Transmit Holding mask bit (8 bits) */ +#define UART_THR_MASKBIT ((uint8_t)0xFF) /*********************************************************************** * Macro defines for Macro defines for UARTn Divisor Latch LSB register **********************************************************************/ -#define UART_LOAD_DLL(div) ((div) & 0xFF) /* Macro for loading least significant halfs of divisors */ -#define UART_DLL_MASKBIT ((uint8_t)0xFF) /* Divisor latch LSB bit mask */ +/* Macro for loading least significant halfs of divisors */ +#define UART_LOAD_DLL(div) ((div) & 0xFF) + +/* Divisor latch LSB bit mask */ +#define UART_DLL_MASKBIT ((uint8_t)0xFF) /*********************************************************************** * Macro defines for Macro defines for UARTn Divisor Latch MSB register **********************************************************************/ -#define UART_DLM_MASKBIT ((uint8_t)0xFF) /* Divisor latch MSB bit mask */ -#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /* Macro for loading most significant halfs of divisors */ +/* Divisor latch MSB bit mask */ +#define UART_DLM_MASKBIT ((uint8_t)0xFF) + +/* Macro for loading most significant halfs of divisors */ +#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*********************************************************************** * Macro defines for Macro defines for UART interrupt enable register **********************************************************************/ -#define UART_IER_RBRINT_EN ((uint32_t)(BIT0)) /* RBR Interrupt enable*/ -#define UART_IER_THREINT_EN ((uint32_t)(BIT1)) /* THR Interrupt enable*/ -#define UART_IER_RLSINT_EN ((uint32_t)(BIT2)) /* RX line status interrupt enable*/ -#define UART1_IER_MSINT_EN ((uint32_t)(BIT3)) /* Modem status interrupt enable */ -#define UART1_IER_CTSINT_EN ((uint32_t)(BIT7)) /* CTS1 signal transition interrupt enable */ -#define UART_IER_ABEOINT_EN ((uint32_t)(BIT8)) /* Enables the end of auto-baud interrupt */ -#define UART_IER_ABTOINT_EN ((uint32_t)(BIT9)) /* Enables the auto-baud time-out interrupt */ -#define UART_IER_BITMASK ((uint32_t)(0x307)) /* UART interrupt enable register bit mask */ -#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /* UART1 interrupt enable register bit mask */ +/* RBR Interrupt enable*/ +#define UART_IER_RBRINT_EN (1 << 0) +/* THR Interrupt enable*/ +#define UART_IER_THREINT_EN (1 << 1) +/* RX line status interrupt enable*/ +#define UART_IER_RLSINT_EN (1 << 2) +/* Modem status interrupt enable */ +#define UART1_IER_MSINT_EN (1 << 3) +/* CTS1 signal transition interrupt enable */ +#define UART1_IER_CTSINT_EN (1 << 7) +/* Enables the end of auto-baud interrupt */ +#define UART_IER_ABEOINT_EN (1 << 8) +/* Enables the auto-baud time-out interrupt */ +#define UART_IER_ABTOINT_EN (1 << 9) +/* UART interrupt enable register bit mask */ +#define UART_IER_BITMASK ((uint32_t)(0x307)) +/* UART1 interrupt enable register bit mask */ +#define UART1_IER_BITMASK ((uint32_t)(0x38F)) /********************************************************************** * Macro defines for Macro defines for UART interrupt identification register **********************************************************************/ -#define UART_IIR_INTSTAT_PEND ((uint32_t)(BIT0)) /* Interrupt Status - Active low */ -#define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /* Interrupt identification: Receive data available*/ -#define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /* Interrupt identification: Receive line status*/ -#define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /* Interrupt identification: Character time-out indicator*/ -#define UART_IIR_INTID_THRE ((uint32_t)(BIT1)) /* Interrupt identification: THRE interrupt*/ -#define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /* Interrupt identification: Modem interrupt*/ -#define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /* Interrupt identification: Interrupt ID mask */ -#define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /* These bits are equivalent to UnFCR[0] */ -#define UART_IIR_ABEO_INT ((uint32_t)(BIT8)) /* End of auto-baud interrupt */ -#define UART_IIR_ABTO_INT ((uint32_t)(BIT9)) /* Auto-baud time-out interrupt */ -#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /* UART interrupt identification register bit mask */ + +/* Interrupt Status - Active low */ +#define UART_IIR_INTSTAT_PEND (1 << 0) +/* Interrupt identification: Modem interrupt*/ +#define UART1_IIR_INTID_MODEM (0 << 1) +/* Interrupt identification: THRE interrupt*/ +#define UART_IIR_INTID_THRE (1 << 1) +/* Interrupt identification: Receive data available*/ +#define UART_IIR_INTID_RDA (2 << 1) +/* Interrupt identification: Receive line status*/ +#define UART_IIR_INTID_RLS (3 << 1) +/* Interrupt identification: Character time-out indicator*/ +#define UART_IIR_INTID_CTI (6 << 1) +/* Interrupt identification: Interrupt ID mask */ +#define UART_IIR_INTID_MASK (7 << 1) +/* These bits are equivalent to UnFCR[0] */ +#define UART_IIR_FIFO_EN (3 << 6) +/* End of auto-baud interrupt */ +#define UART_IIR_ABEO_INT (1 << 8) +/* Auto-baud time-out interrupt */ +#define UART_IIR_ABTO_INT (1 << 9) +/* UART interrupt identification register bit mask */ +#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /********************************************************************** * Macro defines for Macro defines for UART FIFO control register **********************************************************************/ -#define UART_FCR_FIFO_EN ((uint8_t)(BIT0)) /* UART FIFO enable */ -#define UART_FCR_RX_RS ((uint8_t)(BIT1)) /* UART FIFO RX reset */ -#define UART_FCR_TX_RS ((uint8_t)(BIT2)) /* UART FIFO TX reset */ -#define UART_FCR_DMAMODE_SEL ((uint8_t)(BIT3)) /* UART DMA mode selection */ -#define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /* UART FIFO trigger level 0: 1 character */ -#define UART_FCR_TRG_LEV1 ((uint8_t)(BIT6)) /* UART FIFO trigger level 1: 4 character */ -#define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /* UART FIFO trigger level 2: 8 character */ -#define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /* UART FIFO trigger level 3: 14 character */ -#define UART_FCR_BITMASK ((uint8_t)(0xCF)) /* UART FIFO control bit mask */ +/* UART FIFO enable */ +#define UART_FCR_FIFO_EN (1 << 0) +/* UART FIFO RX reset */ +#define UART_FCR_RX_RS (1 << 1) +/* UART FIFO TX reset */ +#define UART_FCR_TX_RS (1 << 2) +/* UART DMA mode selection */ +#define UART_FCR_DMAMODE_SEL (1 << 3) +/* UART FIFO trigger level 0: 1 character */ +#define UART_FCR_TRG_LEV0 (0 << 6) +/* UART FIFO trigger level 1: 4 character */ +#define UART_FCR_TRG_LEV1 (1 << 6) +/* UART FIFO trigger level 2: 8 character */ +#define UART_FCR_TRG_LEV2 (2 << 6) +/* UART FIFO trigger level 3: 14 character */ +#define UART_FCR_TRG_LEV3 (3 << 6) +/* UART FIFO control bit mask */ +#define UART_FCR_BITMASK ((uint8_t)(0xCF)) #define UART_TX_FIFO_SIZE (16) /********************************************************************** * Macro defines for Macro defines for UART line control register **********************************************************************/ -#define UART_LCR_WLEN5 ((uint8_t)(0)) /* UART 5 bit data mode */ -#define UART_LCR_WLEN6 ((uint8_t)(1)) /* UART 6 bit data mode */ -#define UART_LCR_WLEN7 ((uint8_t)(2)) /* UART 7 bit data mode */ -#define UART_LCR_WLEN8 ((uint8_t)(3)) /* UART 8 bit data mode */ -#define UART_LCR_ONE_STOPBIT ((uint8_t)(0)) /* UART One Stop Bits */ -#define UART_LCR_TWO_STOPBIT ((uint8_t)(BIT2)) /* UART Two Stop Bits */ -#define UART_LCR_NO_PARITY ((uint8_t)(0)) /* UART Parity Disabled / No Parity */ -#define UART_LCR_PARITY_EN ((uint8_t)(BIT3)) /* UART Parity Enable */ -#define UART_LCR_PARITY_ODD ((uint8_t)(0)) /* UART Odd Parity Select */ -#define UART_LCR_PARITY_EVEN ((uint8_t)(BIT4)) /* UART Even Parity Select */ -#define UART_LCR_PARITY_SP_1 ((uint8_t)(0x20)) /* UART force 1 stick parity */ -#define UART_LCR_PARITY_SP_0 ((uint8_t)(0x30)) /* UART force 0 stick parity */ -#define UART_LCR_BREAK_EN ((uint8_t)(BIT6)) /* UART Transmission Break enable */ -#define UART_LCR_DLAB_EN ((uint8_t)(BIT7)) /* UART Divisor Latches Access bit enable */ -#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /* UART line control bit mask */ +/* UART 5 bit data mode */ +#define UART_LCR_WLEN5 (0 << 0) +/* UART 6 bit data mode */ +#define UART_LCR_WLEN6 (1 << 0) +/* UART 7 bit data mode */ +#define UART_LCR_WLEN7 (2 << 0) +/* UART 8 bit data mode */ +#define UART_LCR_WLEN8 (3 << 0) +/* UART One Stop Bits */ +#define UART_LCR_ONE_STOPBIT (0 << 2) +/* UART Two Stop Bits */ +#define UART_LCR_TWO_STOPBIT (1 << 2) + +/* UART Parity Disabled / No Parity */ +#define UART_LCR_NO_PARITY (0 << 3) +/* UART Parity Enable */ +#define UART_LCR_PARITY_EN (1 << 3) +/* UART Odd Parity Select */ +#define UART_LCR_PARITY_ODD (0 << 4) +/* UART Even Parity Select */ +#define UART_LCR_PARITY_EVEN (1 << 4) +/* UART force 1 stick parity */ +#define UART_LCR_PARITY_SP_1 (1 << 5) +/* UART force 0 stick parity */ +#define UART_LCR_PARITY_SP_0 ((1 << 5) | (1 << 4)) +/* UART Transmission Break enable */ +#define UART_LCR_BREAK_EN (1 << 6) +/* UART Divisor Latches Access bit enable */ +#define UART_LCR_DLAB_EN (1 << 7) +/* UART line control bit mask */ +#define UART_LCR_BITMASK ((uint8_t)(0xFF)) /********************************************************************** * Macro defines for Macro defines for UART line status register **********************************************************************/ -#define UART_LSR_RDR ((uint8_t)(BIT0)) /* Line status register: Receive data ready */ -#define UART_LSR_OE ((uint8_t)(BIT1)) /* Line status register: Overrun error */ -#define UART_LSR_PE ((uint8_t)(BIT2)) /* Line status register: Parity error */ -#define UART_LSR_FE ((uint8_t)(BIT3)) /* Line status register: Framing error */ -#define UART_LSR_BI ((uint8_t)(BIT4)) /* Line status register: Break interrupt */ -#define UART_LSR_THRE ((uint8_t)(BIT5)) /* Line status register: Transmit holding register empty */ -#define UART_LSR_TEMT ((uint8_t)(BIT6)) /* Line status register: Transmitter empty */ -#define UART_LSR_RXFE ((uint8_t)(BIT7)) /* Error in RX FIFO */ -#define UART_LSR_BITMASK ((uint8_t)(0xFF)) /* UART Line status bit mask */ -#define UART_LSR_ERROR_MASK (UART_LSR_OE|UART_LSR_PE|UART_LSR_FE|UART_LSR_BI|UART_LSR_RXFE) +/* Line status register: Receive data ready */ +#define UART_LSR_RDR (1 << 0) +/* Line status register: Overrun error */ +#define UART_LSR_OE (1 << 1) +/* Line status register: Parity error */ +#define UART_LSR_PE (1 << 2) +/* Line status register: Framing error */ +#define UART_LSR_FE (1 << 3) +/* Line status register: Break interrupt */ +#define UART_LSR_BI (1 << 4) +/* Line status register: Transmit holding register empty */ +#define UART_LSR_THRE (1 << 5) +/* Line status register: Transmitter empty */ +#define UART_LSR_TEMT (1 << 6) +/* Error in RX FIFO */ +#define UART_LSR_RXFE (1 << 7) +/* UART Line status bit mask */ +#define UART_LSR_BITMASK ((uint8_t)(0xFF)) +#define UART_LSR_ERROR_MASK \ + (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE) /********************************************************************** * Macro defines for Macro defines for UART Scratch Pad Register **********************************************************************/ -#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /* UART Scratch Pad bit mask */ + +/* UART Scratch Pad bit mask */ +#define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*********************************************************************** * Macro defines for Macro defines for UART Auto baudrate control register **********************************************************************/ -#define UART_ACR_START ((uint32_t)(BIT0)) /* UART Auto-baud start */ -#define UART_ACR_MODE ((uint32_t)(BIT1)) /* UART Auto baudrate Mode 1 */ -#define UART_ACR_AUTO_RESTART ((uint32_t)(BIT2)) /* UART Auto baudrate restart */ -#define UART_ACR_ABEOINT_CLR ((uint32_t)(BIT8)) /* UART End of auto-baud interrupt clear */ -#define UART_ACR_ABTOINT_CLR ((uint32_t)(BIT9)) /* UART Auto-baud time-out interrupt clear */ -#define UART_ACR_BITMASK ((uint32_t)(0x307)) /* UART Auto Baudrate register bit mask */ + +/* UART Auto-baud start */ +#define UART_ACR_START (1 << 0) +/* UART Auto baudrate Mode 1 */ +#define UART_ACR_MODE (1 << 1) +/* UART Auto baudrate restart */ +#define UART_ACR_AUTO_RESTART (1 << 2) +/* UART End of auto-baud interrupt clear */ +#define UART_ACR_ABEOINT_CLR (1 << 8) +/* UART Auto-baud time-out interrupt clear */ +#define UART_ACR_ABTOINT_CLR (1 << 9) +/* UART Auto Baudrate register bit mask */ +#define UART_ACR_BITMASK ((uint32_t)(0x307)) /********************************************************************* * Macro defines for Macro defines for UART IrDA control register **********************************************************************/ -#define UART_ICR_IRDAEN ((uint32_t)(BIT0)) /* IrDA mode enable */ -#define UART_ICR_IRDAINV ((uint32_t)(BIT1)) /* IrDA serial input inverted */ -#define UART_ICR_FIXPULSE_EN ((uint32_t)(BIT2)) /* IrDA fixed pulse width mode */ -#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /* PulseDiv - Configures the pulse when FixPulseEn = 1 */ -#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /* UART IRDA bit mask */ +/* IrDA mode enable */ +#define UART_ICR_IRDAEN (1 << 0) +/* IrDA serial input inverted */ +#define UART_ICR_IRDAINV (1 << 1) +/* IrDA fixed pulse width mode */ +#define UART_ICR_FIXPULSE_EN (1 << 2) +/* PulseDiv - Configures the pulse when FixPulseEn = 1 */ +#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) +/* UART IRDA bit mask */ +#define UART_ICR_BITMASK ((uint32_t)(0x3F)) /********************************************************************** * Macro defines for Macro defines for UART half duplex register **********************************************************************/ -#define UART_HDEN_HDEN ((uint32_t)(BIT0)) /* enable half-duplex mode*/ +/* enable half-duplex mode*/ +#define UART_HDEN_HDEN (1 << 0) /********************************************************************** * Macro defines for Macro defines for UART smart card interface control register **********************************************************************/ -#define UART_SCICTRL_SCIEN ((uint32_t)(BIT0)) /* enable asynchronous half-duplex smart card interface*/ -#define UART_SCICTRL_NACKDIS ((uint32_t)(BIT1)) /* NACK response is inhibited*/ -#define UART_SCICTRL_PROTSEL_T1 ((uint32_t)(BIT2)) /* ISO7816-3 protocol T1 is selected*/ -#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) /* number of retransmission*/ -#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) /* Extra guard time*/ +/* enable asynchronous half-duplex smart card interface*/ +#define UART_SCICTRL_SCIEN (1 << 0) +/* NACK response is inhibited*/ +#define UART_SCICTRL_NACKDIS (1 << 1) +/* ISO7816-3 protocol T1 is selected*/ +#define UART_SCICTRL_PROTSEL_T1 (1 << 2) +/* number of retransmission*/ +#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) +/* Extra guard time*/ +#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) /********************************************************************* * Macro defines for Macro defines for UART synchronous control register **********************************************************************/ -#define UART_SYNCCTRL_SYNC ((uint32_t)(BIT0)) /* enable synchronous mode*/ -#define UART_SYNCCTRL_CSRC_MASTER ((uint32_t)(BIT1)) /* synchronous master mode*/ -#define UART_SYNCCTRL_FES ((uint32_t)(BIT2)) /* sample on falling edge*/ -#define UART_SYNCCTRL_TSBYPASS ((uint32_t)(BIT3)) /* to be defined*/ -#define UART_SYNCCTRL_CSCEN ((uint32_t)(BIT4)) /* continuous running clock enable (master mode only) */ -#define UART_SYNCCTRL_NOSTARTSTOP ((uint32_t)(BIT5)) /* Do not send start/stop bit */ -#define UART_SYNCCTRL_CCCLR ((uint32_t)(BIT6)) /* stop continuous clock */ +/* enable synchronous mode*/ +#define UART_SYNCCTRL_SYNC (1 << 0) +/* synchronous master mode*/ +#define UART_SYNCCTRL_CSRC_MASTER (1 << 1) +/* sample on falling edge*/ +#define UART_SYNCCTRL_FES (1 << 2) +/* to be defined*/ +#define UART_SYNCCTRL_TSBYPASS (1 << 3) +/* continuous running clock enable (master mode only) */ +#define UART_SYNCCTRL_CSCEN (1 << 4) +/* Do not send start/stop bit */ +#define UART_SYNCCTRL_NOSTARTSTOP (1 << 5) +/* stop continuous clock */ +#define UART_SYNCCTRL_CCCLR (1 << 6) /********************************************************************* * Macro defines for Macro defines for UART Fractional divider register **********************************************************************/ -#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /* Baud-rate generation pre-scaler divisor */ -#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /* Baud-rate pre-scaler multiplier value */ -#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /* UART Fractional Divider register bit mask */ + +/* Baud-rate generation pre-scaler divisor */ +#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) +/* Baud-rate pre-scaler multiplier value */ +#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) +/* UART Fractional Divider register bit mask */ +#define UART_FDR_BITMASK ((uint32_t)(0xFF)) /********************************************************************* * Macro defines for Macro defines for UART Tx Enable register **********************************************************************/ -#define UART_TER_TXEN ((uint8_t)(BIT0)) /* Transmit enable bit */ + +#define UART_TER_TXEN (1 << 0) /* Transmit enable bit */ /********************************************************************** * Macro defines for Macro defines for UART FIFO Level register **********************************************************************/ -#define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F)) /* Reflects the current level of the UART receiver FIFO */ -#define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F)) /* Reflects the current level of the UART transmitter FIFO */ -#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /* UART FIFO Level Register bit mask */ +/* Reflects the current level of the UART receiver FIFO */ +#define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F)) +/* Reflects the current level of the UART transmitter FIFO */ +#define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F)) +/* UART FIFO Level Register bit mask */ +#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /********************************************************************* * UART enum @@ -269,47 +368,54 @@ * UART Databit type definitions */ typedef enum { - UART_DATABIT_5 = UART_LCR_WLEN5, /* UART 5 bit data mode */ - UART_DATABIT_6 = UART_LCR_WLEN6, /* UART 6 bit data mode */ - UART_DATABIT_7 = UART_LCR_WLEN7, /* UART 7 bit data mode */ - UART_DATABIT_8 = UART_LCR_WLEN8 /* UART 8 bit data mode */ + UART_DATABIT_5 = UART_LCR_WLEN5,/* UART 5 bit data mode */ + UART_DATABIT_6 = UART_LCR_WLEN6,/* UART 6 bit data mode */ + UART_DATABIT_7 = UART_LCR_WLEN7,/* UART 7 bit data mode */ + UART_DATABIT_8 = UART_LCR_WLEN8/* UART 8 bit data mode */ } uart_databit_t; /* * UART Stop bit type definitions */ typedef enum { - UART_STOPBIT_1 = UART_LCR_ONE_STOPBIT, /* UART 1 Stop Bits Select */ - UART_STOPBIT_2 = UART_LCR_TWO_STOPBIT /* UART 2 Stop Bits Select */ + /* UART 1 Stop Bits Select */ + UART_STOPBIT_1 = UART_LCR_ONE_STOPBIT, + /* UART 2 Stop Bits Select */ + UART_STOPBIT_2 = UART_LCR_TWO_STOPBIT } uart_stopbit_t; /* * UART Parity type definitions */ typedef enum { - UART_PARITY_NONE = UART_LCR_NO_PARITY, /* No parity */ - UART_PARITY_ODD = (UART_LCR_PARITY_ODD | UART_LCR_PARITY_EN), /* Odd parity */ - UART_PARITY_EVEN = (UART_LCR_PARITY_EVEN | UART_LCR_PARITY_EN), /* Even parity */ - UART_PARITY_SP_1 = (UART_LCR_PARITY_SP_1 | UART_LCR_PARITY_EN), /* Forced 1 stick parity */ - UART_PARITY_SP_0 = (UART_LCR_PARITY_SP_0 | UART_LCR_PARITY_EN) /* Forced 0 stick parity */ + /* No parity */ + UART_PARITY_NONE = UART_LCR_NO_PARITY, + /* Odd parity */ + UART_PARITY_ODD = (UART_LCR_PARITY_ODD | UART_LCR_PARITY_EN), + /* Even parity */ + UART_PARITY_EVEN = (UART_LCR_PARITY_EVEN | UART_LCR_PARITY_EN), + /* Forced 1 stick parity */ + UART_PARITY_SP_1 = (UART_LCR_PARITY_SP_1 | UART_LCR_PARITY_EN), + /* Forced 0 stick parity */ + UART_PARITY_SP_0 = (UART_LCR_PARITY_SP_0 | UART_LCR_PARITY_EN) } uart_parity_t; typedef enum { - UART0_NUM = UART0, - UART1_NUM = UART1, - UART2_NUM = UART2, - UART3_NUM = UART3 + UART0_NUM = UART0, + UART1_NUM = UART1, + UART2_NUM = UART2, + UART3_NUM = UART3 } uart_num_t; typedef enum { - UART_NO_ERROR = 0, - UART_TIMEOUT_ERROR = 1 + UART_NO_ERROR = 0, + UART_TIMEOUT_ERROR = 1 } uart_error_t; typedef enum { - UART_RX_NO_DATA = 0, - UART_RX_DATA_READY = 1, - UART_RX_DATA_ERROR = 2 + UART_RX_NO_DATA = 0, + UART_RX_DATA_READY = 1, + UART_RX_DATA_ERROR = 2 } uart_rx_data_ready_t; /* function prototypes */ @@ -317,20 +423,14 @@ typedef enum { BEGIN_DECLS /* Init UART and set PLL1 as clock source (PCLK) */ -void uart_init(uart_num_t uart_num, - uart_databit_t data_nb_bits, - uart_stopbit_t data_nb_stop, - uart_parity_t data_parity, - uint16_t uart_divisor, - uint8_t uart_divaddval, - uint8_t uart_mulval); +void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits, + uart_stopbit_t data_nb_stop, uart_parity_t data_parity, + uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval); uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num); - uint8_t uart_read(uart_num_t uart_num); - -uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, uart_error_t* error); - +uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, + uart_error_t *error); void uart_write(uart_num_t uart_num, uint8_t data); END_DECLS diff --git a/include/libopencm3/lpc43xx/usb.h b/include/libopencm3/lpc43xx/usb.h index 7848b629..2f1f1565 100644 --- a/include/libopencm3/lpc43xx/usb.h +++ b/include/libopencm3/lpc43xx/usb.h @@ -23,7 +23,8 @@ #include #include -#define BIT_MASK(base_name) (((1 << base_name##_WIDTH) - 1) << base_name##_SHIFT) +#define BIT_MASK(base_name) \ + (((1 << base_name##_WIDTH) - 1) << base_name##_SHIFT) #define BIT_ARG(base_name, x) ((x) << base_name##_SHIFT) /* USB device data structures */ @@ -36,14 +37,16 @@ typedef struct usb_transfer_descriptor_t usb_transfer_descriptor_t; struct usb_transfer_descriptor_t { - volatile usb_transfer_descriptor_t* next_dtd_pointer; + volatile usb_transfer_descriptor_t *next_dtd_pointer; volatile uint32_t total_bytes; volatile uint32_t buffer_pointer_page[5]; volatile uint32_t _reserved; }; #define USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT (0) -#define USB_TD_NEXT_DTD_POINTER_TERMINATE ((volatile usb_transfer_descriptor_t*)(1 << USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT)) +#define USB_TD_NEXT_DTD_POINTER_TERMINATE \ + ((volatile usb_transfer_descriptor_t *) \ + (1 << USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT)) #define USB_TD_DTD_TOKEN_TOTAL_BYTES_SHIFT (16) #define USB_TD_DTD_TOKEN_TOTAL_BYTES_WIDTH (15) @@ -59,24 +62,28 @@ struct usb_transfer_descriptor_t { #define USB_TD_DTD_TOKEN_MULTO(x) BIT_ARG(USB_TD_DTD_TOKEN_MULTO, x) #define USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT (7) -#define USB_TD_DTD_TOKEN_STATUS_ACTIVE (1 << USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT) +#define USB_TD_DTD_TOKEN_STATUS_ACTIVE \ + (1 << USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT) #define USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT (6) -#define USB_TD_DTD_TOKEN_STATUS_HALTED (1 << USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT) +#define USB_TD_DTD_TOKEN_STATUS_HALTED \ + (1 << USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT) #define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT (5) -#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR (1 << USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT) +#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR \ + (1 << USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT) #define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT (3) -#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR (1 << USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT) +#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR \ + (1 << USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT) /* --- Endpoint Queue Head (dQH) ------------------------------------------- */ /* - must be aligned on 64-byte boundaries. */ typedef struct { volatile uint32_t capabilities; - volatile usb_transfer_descriptor_t* current_dtd_pointer; - volatile usb_transfer_descriptor_t* next_dtd_pointer; + volatile usb_transfer_descriptor_t *current_dtd_pointer; + volatile usb_transfer_descriptor_t *next_dtd_pointer; volatile uint32_t total_bytes; volatile uint32_t buffer_pointer_page[5]; volatile uint32_t _reserved_0; @@ -86,7 +93,7 @@ typedef struct { #define USB_QH_CAPABILITIES_IOS_SHIFT (15) #define USB_QH_CAPABILITIES_IOS (1 << USB_QH_CAPABILITIES_IOS_SHIFT) - + #define USB_QH_CAPABILITIES_MPL_SHIFT (16) #define USB_QH_CAPABILITIES_MPL_WIDTH (11) #define USB_QH_CAPABILITIES_MPL_MASK BIT_MASK(USB_QH_CAPABILITIES_MPL) @@ -210,7 +217,8 @@ typedef struct { #define USB0_ENDPTCOMPLETE MMIO32(USB0_BASE + 0x1BC) /* Endpoint control */ -#define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + (logical_ep * 4)) +#define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + \ + (logical_ep * 4)) /* Endpoint control 0 */ #define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0) @@ -232,14 +240,17 @@ typedef struct { /* --- USB0_CAPLENGTH values ------------------------------------ */ -/* CAPLENGTH: Indicates offset to add to the register base address at the beginning of the Operational Register */ +/* CAPLENGTH: Indicates offset to add to the register base address at the + beginning of the Operational Register */ #define USB0_CAPLENGTH_CAPLENGTH_SHIFT (0) #define USB0_CAPLENGTH_CAPLENGTH_MASK (0xff << USB0_CAPLENGTH_CAPLENGTH_SHIFT) #define USB0_CAPLENGTH_CAPLENGTH(x) ((x) << USB0_CAPLENGTH_CAPLENGTH_SHIFT) -/* HCIVERSION: BCD encoding of the EHCI revision number supported by this host controller */ +/* HCIVERSION: BCD encoding of the EHCI revision number supported by this host + controller */ #define USB0_CAPLENGTH_HCIVERSION_SHIFT (8) -#define USB0_CAPLENGTH_HCIVERSION_MASK (0xffff << USB0_CAPLENGTH_HCIVERSION_SHIFT) +#define USB0_CAPLENGTH_HCIVERSION_MASK \ + (0xffff << USB0_CAPLENGTH_HCIVERSION_SHIFT) #define USB0_CAPLENGTH_HCIVERSION(x) ((x) << USB0_CAPLENGTH_HCIVERSION_SHIFT) /* --- USB0_HCSPARAMS values ------------------------------------ */ @@ -357,15 +368,18 @@ typedef struct { #define USB0_USBCMD_H_FS1_SHIFT (3) #define USB0_USBCMD_H_FS1 (1 << USB0_USBCMD_H_FS1_SHIFT) -/* PSE: This bit controls whether the host controller skips processing the periodic schedule */ +/* PSE: This bit controls whether the host controller skips processing the +periodic schedule */ #define USB0_USBCMD_H_PSE_SHIFT (4) #define USB0_USBCMD_H_PSE (1 << USB0_USBCMD_H_PSE_SHIFT) -/* ASE: This bit controls whether the host controller skips processing the asynchronous schedule */ +/* ASE: This bit controls whether the host controller skips processing the +asynchronous schedule */ #define USB0_USBCMD_H_ASE_SHIFT (5) #define USB0_USBCMD_H_ASE (1 << USB0_USBCMD_H_ASE_SHIFT) -/* IAA: This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule */ +/* IAA: This bit is used as a doorbell by software to tell the host controller +to issue an interrupt the next time it advances asynchronous schedule */ #define USB0_USBCMD_H_IAA_SHIFT (6) #define USB0_USBCMD_H_IAA (1 << USB0_USBCMD_H_IAA_SHIFT) @@ -540,7 +554,8 @@ typedef struct { /* FRINDEX13_3: Current frame number of the last frame transmitted */ #define USB0_FRINDEX_D_FRINDEX13_3_SHIFT (3) -#define USB0_FRINDEX_D_FRINDEX13_3_MASK (0x7ff << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) +#define USB0_FRINDEX_D_FRINDEX13_3_MASK \ + (0x7ff << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) #define USB0_FRINDEX_D_FRINDEX13_3(x) ((x) << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) /* --- USB0_FRINDEX_H values ------------------------------------ */ @@ -552,7 +567,8 @@ typedef struct { /* FRINDEX12_3: Frame list current index */ #define USB0_FRINDEX_H_FRINDEX12_3_SHIFT (3) -#define USB0_FRINDEX_H_FRINDEX12_3_MASK (0x3ff << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) +#define USB0_FRINDEX_H_FRINDEX12_3_MASK \ + (0x3ff << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) #define USB0_FRINDEX_H_FRINDEX12_3(x) ((x) << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) /* --- USB0_DEVICEADDR values ----------------------------------- */ @@ -570,22 +586,28 @@ typedef struct { /* PERBASE31_12: Base Address (Low) */ #define USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT (12) -#define USB0_PERIODICLISTBASE_PERBASE31_12_MASK (0xfffff << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) -#define USB0_PERIODICLISTBASE_PERBASE31_12(x) ((x) << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) +#define USB0_PERIODICLISTBASE_PERBASE31_12_MASK \ + (0xfffff << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) +#define USB0_PERIODICLISTBASE_PERBASE31_12(x) \ + ((x) << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) /* --- USB0_ENDPOINTLISTADDR values ----------------------------- */ /* EPBASE31_11: Endpoint list pointer (low) */ #define USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT (11) -#define USB0_ENDPOINTLISTADDR_EPBASE31_11_MASK (0x1fffff << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) -#define USB0_ENDPOINTLISTADDR_EPBASE31_11(x) ((x) << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) +#define USB0_ENDPOINTLISTADDR_EPBASE31_11_MASK \ + (0x1fffff << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) +#define USB0_ENDPOINTLISTADDR_EPBASE31_11(x) \ + ((x) << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) /* --- USB0_ASYNCLISTADDR values -------------------------------- */ /* ASYBASE31_5: Link pointer (Low) LPL */ #define USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT (5) -#define USB0_ASYNCLISTADDR_ASYBASE31_5_MASK (0x7ffffff << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) -#define USB0_ASYNCLISTADDR_ASYBASE31_5(x) ((x) << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) +#define USB0_ASYNCLISTADDR_ASYBASE31_5_MASK \ + (0x7ffffff << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) +#define USB0_ASYNCLISTADDR_ASYBASE31_5(x) \ + ((x) << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) /* --- USB0_TTCTRL values --------------------------------------- */ @@ -615,13 +637,17 @@ typedef struct { /* TXSCHEATLTH: Scheduler health counter */ #define USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT (8) -#define USB0_TXFILLTUNING_TXSCHEATLTH_MASK (0x1f << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) -#define USB0_TXFILLTUNING_TXSCHEATLTH(x) ((x) << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) +#define USB0_TXFILLTUNING_TXSCHEATLTH_MASK \ + (0x1f << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) +#define USB0_TXFILLTUNING_TXSCHEATLTH(x) \ + ((x) << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) /* TXFIFOTHRES: Scheduler overhead */ #define USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT (16) -#define USB0_TXFILLTUNING_TXFIFOTHRES_MASK (0x3f << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) -#define USB0_TXFILLTUNING_TXFIFOTHRES(x) ((x) << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) +#define USB0_TXFILLTUNING_TXFIFOTHRES_MASK \ + (0x3f << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) +#define USB0_TXFILLTUNING_TXFIFOTHRES(x) \ + ((x) << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) /* --- USB0_BINTERVAL values ------------------------------------ */ @@ -953,8 +979,10 @@ typedef struct { /* ENDPSETUPSTAT: Setup endpoint status for logical endpoints 0 to 5 */ #define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0) -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0x3f << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) -#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) ((x) << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK \ + (0x3f << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) \ + ((x) << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) /* --- USB0_ENDPTPRIME values ----------------------------------- */