diff --git a/include/libopencm3/stm32/f4/pwr.h b/include/libopencm3/stm32/f4/pwr.h index b2ff76f1..fc605118 100644 --- a/include/libopencm3/stm32/f4/pwr.h +++ b/include/libopencm3/stm32/f4/pwr.h @@ -72,14 +72,14 @@ LGPL License Terms @ref lgpl_license /* --- Function prototypes ------------------------------------------------- */ -typedef enum { - SCALE1, - SCALE2, -} vos_scale_t; +enum pwr_vos_scale { + PWR_SCALE1, + PWR_SCALE2, +}; BEGIN_DECLS -void pwr_set_vos_scale(vos_scale_t scale); +void pwr_set_vos_scale(enum pwr_vos_scale scale); END_DECLS diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h index 89a720fe..24858cc7 100644 --- a/include/libopencm3/stm32/f4/rcc.h +++ b/include/libopencm3/stm32/f4/rcc.h @@ -546,15 +546,15 @@ extern uint32_t rcc_apb2_frequency; /* --- Function prototypes ------------------------------------------------- */ -typedef enum { - CLOCK_3V3_48MHZ, - CLOCK_3V3_84MHZ, - CLOCK_3V3_120MHZ, - CLOCK_3V3_168MHZ, - CLOCK_3V3_END -} clock_3v3_t; +enum rcc_clock_3v3 { + RCC_CLOCK_3V3_48MHZ, + RCC_CLOCK_3V3_84MHZ, + RCC_CLOCK_3V3_120MHZ, + RCC_CLOCK_3V3_168MHZ, + RCC_CLOCK_3V3_END +}; -typedef struct { +struct rcc_clock_scale { uint8_t pllm; uint16_t plln; uint8_t pllp; @@ -566,15 +566,19 @@ typedef struct { uint8_t power_save; uint32_t apb1_frequency; uint32_t apb2_frequency; -} clock_scale_t; +}; -extern const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END]; -extern const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END]; -extern const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END]; -extern const clock_scale_t hse_25mhz_3v3[CLOCK_3V3_END]; +extern const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END]; +extern const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END]; +extern const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END]; +extern const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END]; enum rcc_osc { - PLL, HSE, HSI, LSE, LSI + RCC_PLL, + RCC_HSE, + RCC_HSI, + RCC_LSE, + RCC_LSI }; #define _REG_BIT(base, bit) (((base) << 5) + (bit)) @@ -854,7 +858,7 @@ void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq); uint32_t rcc_system_clock_source(void); -void rcc_clock_setup_hse_3v3(const clock_scale_t *clock); +void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock); END_DECLS diff --git a/lib/stm32/f4/pwr.c b/lib/stm32/f4/pwr.c index 9b9e579d..499152b1 100644 --- a/lib/stm32/f4/pwr.c +++ b/lib/stm32/f4/pwr.c @@ -36,11 +36,11 @@ #include -void pwr_set_vos_scale(vos_scale_t scale) +void pwr_set_vos_scale(enum pwr_vos_scale scale) { - if (scale == SCALE1) { + if (scale == PWR_SCALE1) { PWR_CR |= PWR_CR_VOS; - } else if (scale == SCALE2) { + } else if (scale == PWR_SCALE2) { PWR_CR &= PWR_CR_VOS; } } diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index e7065053..2f716da7 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -49,7 +49,7 @@ uint32_t rcc_ahb_frequency = 16000000; uint32_t rcc_apb1_frequency = 16000000; uint32_t rcc_apb2_frequency = 16000000; -const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = { +const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { { /* 48MHz */ .pllm = 8, .plln = 96, @@ -106,7 +106,7 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = { }, }; -const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] = { +const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { { /* 48MHz */ .pllm = 12, .plln = 96, @@ -163,7 +163,7 @@ const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] = { }, }; -const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = { +const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { { /* 48MHz */ .pllm = 16, .plln = 96, @@ -220,7 +220,7 @@ const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = { }, }; -const clock_scale_t hse_25mhz_3v3[CLOCK_3V3_END] = { +const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { { /* 48MHz */ .pllm = 25, .plln = 96, @@ -280,19 +280,19 @@ const clock_scale_t hse_25mhz_3v3[CLOCK_3V3_END] = { void rcc_osc_ready_int_clear(enum rcc_osc osc) { switch (osc) { - case PLL: + case RCC_PLL: RCC_CIR |= RCC_CIR_PLLRDYC; break; - case HSE: + case RCC_HSE: RCC_CIR |= RCC_CIR_HSERDYC; break; - case HSI: + case RCC_HSI: RCC_CIR |= RCC_CIR_HSIRDYC; break; - case LSE: + case RCC_LSE: RCC_CIR |= RCC_CIR_LSERDYC; break; - case LSI: + case RCC_LSI: RCC_CIR |= RCC_CIR_LSIRDYC; break; } @@ -301,19 +301,19 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc) void rcc_osc_ready_int_enable(enum rcc_osc osc) { switch (osc) { - case PLL: + case RCC_PLL: RCC_CIR |= RCC_CIR_PLLRDYIE; break; - case HSE: + case RCC_HSE: RCC_CIR |= RCC_CIR_HSERDYIE; break; - case HSI: + case RCC_HSI: RCC_CIR |= RCC_CIR_HSIRDYIE; break; - case LSE: + case RCC_LSE: RCC_CIR |= RCC_CIR_LSERDYIE; break; - case LSI: + case RCC_LSI: RCC_CIR |= RCC_CIR_LSIRDYIE; break; } @@ -322,19 +322,19 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc) void rcc_osc_ready_int_disable(enum rcc_osc osc) { switch (osc) { - case PLL: + case RCC_PLL: RCC_CIR &= ~RCC_CIR_PLLRDYIE; break; - case HSE: + case RCC_HSE: RCC_CIR &= ~RCC_CIR_HSERDYIE; break; - case HSI: + case RCC_HSI: RCC_CIR &= ~RCC_CIR_HSIRDYIE; break; - case LSE: + case RCC_LSE: RCC_CIR &= ~RCC_CIR_LSERDYIE; break; - case LSI: + case RCC_LSI: RCC_CIR &= ~RCC_CIR_LSIRDYIE; break; } @@ -343,19 +343,19 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc) int rcc_osc_ready_int_flag(enum rcc_osc osc) { switch (osc) { - case PLL: + case RCC_PLL: return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); break; - case HSE: + case RCC_HSE: return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); break; - case HSI: + case RCC_HSI: return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); break; - case LSE: + case RCC_LSE: return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); break; - case LSI: + case RCC_LSI: return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); break; } @@ -376,19 +376,19 @@ int rcc_css_int_flag(void) void rcc_wait_for_osc_ready(enum rcc_osc osc) { switch (osc) { - case PLL: + case RCC_PLL: while ((RCC_CR & RCC_CR_PLLRDY) == 0); break; - case HSE: + case RCC_HSE: while ((RCC_CR & RCC_CR_HSERDY) == 0); break; - case HSI: + case RCC_HSI: while ((RCC_CR & RCC_CR_HSIRDY) == 0); break; - case LSE: + case RCC_LSE: while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); break; - case LSI: + case RCC_LSI: while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); break; } @@ -397,13 +397,13 @@ void rcc_wait_for_osc_ready(enum rcc_osc osc) void rcc_wait_for_sysclk_status(enum rcc_osc osc) { switch (osc) { - case PLL: + case RCC_PLL: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL); break; - case HSE: + case RCC_HSE: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE); break; - case HSI: + case RCC_HSI: while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI); break; default: @@ -415,19 +415,19 @@ void rcc_wait_for_sysclk_status(enum rcc_osc osc) void rcc_osc_on(enum rcc_osc osc) { switch (osc) { - case PLL: + case RCC_PLL: RCC_CR |= RCC_CR_PLLON; break; - case HSE: + case RCC_HSE: RCC_CR |= RCC_CR_HSEON; break; - case HSI: + case RCC_HSI: RCC_CR |= RCC_CR_HSION; break; - case LSE: + case RCC_LSE: RCC_BDCR |= RCC_BDCR_LSEON; break; - case LSI: + case RCC_LSI: RCC_CSR |= RCC_CSR_LSION; break; } @@ -436,19 +436,19 @@ void rcc_osc_on(enum rcc_osc osc) void rcc_osc_off(enum rcc_osc osc) { switch (osc) { - case PLL: + case RCC_PLL: RCC_CR &= ~RCC_CR_PLLON; break; - case HSE: + case RCC_HSE: RCC_CR &= ~RCC_CR_HSEON; break; - case HSI: + case RCC_HSI: RCC_CR &= ~RCC_CR_HSION; break; - case LSE: + case RCC_LSE: RCC_BDCR &= ~RCC_BDCR_LSEON; break; - case LSI: + case RCC_LSI: RCC_CSR &= ~RCC_CSR_LSION; break; } @@ -467,15 +467,15 @@ void rcc_css_disable(void) void rcc_osc_bypass_enable(enum rcc_osc osc) { switch (osc) { - case HSE: + case RCC_HSE: RCC_CR |= RCC_CR_HSEBYP; break; - case LSE: + case RCC_LSE: RCC_BDCR |= RCC_BDCR_LSEBYP; break; - case PLL: - case HSI: - case LSI: + case RCC_PLL: + case RCC_HSI: + case RCC_LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } @@ -484,22 +484,20 @@ void rcc_osc_bypass_enable(enum rcc_osc osc) void rcc_osc_bypass_disable(enum rcc_osc osc) { switch (osc) { - case HSE: + case RCC_HSE: RCC_CR &= ~RCC_CR_HSEBYP; break; - case LSE: + case RCC_LSE: RCC_BDCR &= ~RCC_BDCR_LSEBYP; break; - case PLL: - case HSI: - case LSI: + case RCC_PLL: + case RCC_HSI: + case RCC_LSI: /* Do nothing, only HSE/LSE allowed here. */ break; } } - - void rcc_set_sysclk_source(uint32_t clk) { uint32_t reg32; @@ -579,24 +577,24 @@ uint32_t rcc_system_clock_source(void) return (RCC_CFGR & 0x000c) >> 2; } -void rcc_clock_setup_hse_3v3(const clock_scale_t *clock) +void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) { /* Enable internal high-speed oscillator. */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); + rcc_osc_on(RCC_HSI); + rcc_wait_for_osc_ready(RCC_HSI); /* Select HSI as SYSCLK source. */ rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* Enable external high-speed oscillator 8MHz. */ - rcc_osc_on(HSE); - rcc_wait_for_osc_ready(HSE); + rcc_osc_on(RCC_HSE); + rcc_wait_for_osc_ready(RCC_HSE); /* Enable/disable high performance mode */ if (!clock->power_save) { - pwr_set_vos_scale(SCALE1); + pwr_set_vos_scale(PWR_SCALE1); } else { - pwr_set_vos_scale(SCALE2); + pwr_set_vos_scale(PWR_SCALE2); } /* @@ -611,8 +609,8 @@ void rcc_clock_setup_hse_3v3(const clock_scale_t *clock) clock->pllp, clock->pllq); /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); + rcc_osc_on(RCC_PLL); + rcc_wait_for_osc_ready(RCC_PLL); /* Configure flash settings. */ flash_set_ws(clock->flash_config); @@ -621,16 +619,14 @@ void rcc_clock_setup_hse_3v3(const clock_scale_t *clock) rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* Wait for PLL clock to be selected. */ - rcc_wait_for_sysclk_status(PLL); + rcc_wait_for_sysclk_status(RCC_PLL); /* Set the peripheral clock frequencies used. */ rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; /* Disable internal high-speed oscillator. */ - rcc_osc_off(HSI); + rcc_osc_off(RCC_HSI); } - - /**@}*/