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Merge commit '05518094752e450708aced3397cb26146e8ce0d3' into sam-update

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This commit is contained in:
Jason Kotzin 2022-08-01 19:59:54 -07:00
commit d76fd844c9
4 changed files with 11 additions and 12 deletions
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5
scripts/stm32_mem.py
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@ -89,7 +89,10 @@ def stm32_scan(args, test):
exit(-1) exit(-1)
for dev in devs: for dev in devs:
dfudev = dfu.dfu_device(*dev) try:
dfudev = dfu.dfu_device(*dev)
except:
return 0
man = dfudev.handle.getString(dfudev.dev.iManufacturer, 30) man = dfudev.handle.getString(dfudev.dev.iManufacturer, 30)
if man == "Black Sphere Technologies": bmp = bmp + 1 if man == "Black Sphere Technologies": bmp = bmp + 1
if bmp == 0 : if bmp == 0 :

2
src/target/cortexm.c
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@ -413,6 +413,8 @@ void cortexm_detach(target *t)
/* Disable debug */ /* Disable debug */
target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY); target_mem_write32(t, CORTEXM_DHCSR, CORTEXM_DHCSR_DBGKEY);
/* Add some clock cycles to get the CPU running again.*/
target_mem_read32(t, 0);
} }
enum { DB_DHCSR, DB_DCRSR, DB_DCRDR, DB_DEMCR }; enum { DB_DHCSR, DB_DCRSR, DB_DCRDR, DB_DEMCR };

3
src/target/stm32f1.c
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@ -330,6 +330,9 @@ static bool stm32f1_cmd_option(target *t, int argc, char *argv[])
case 0x438: /* STM32F303x6/8 and STM32F328 */ case 0x438: /* STM32F303x6/8 and STM32F328 */
case 0x440: /* STM32F0 */ case 0x440: /* STM32F0 */
case 0x446: /* STM32F303xD/E and STM32F398xE */ case 0x446: /* STM32F303xD/E and STM32F398xE */
case 0x445: /* STM32F04 RM0091 Rev.7, STM32F070x6 RM0360 Rev. 4*/
case 0x448: /* STM32F07 RM0091 Rev.7, STM32F070xB RM0360 Rev. 4*/
case 0x442: /* STM32F09 RM0091 Rev.7, STM32F030xC RM0360 Rev. 4*/
flash_obp_rdp_key = FLASH_OBP_RDP_KEY_F3; flash_obp_rdp_key = FLASH_OBP_RDP_KEY_F3;
break; break;
default: flash_obp_rdp_key = FLASH_OBP_RDP_KEY; default: flash_obp_rdp_key = FLASH_OBP_RDP_KEY;

13
src/target/stm32f4.c
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@ -101,15 +101,6 @@ static int stm32f4_flash_write(struct target_flash *f,
#define DBGMCU_IDCODE 0xE0042000 #define DBGMCU_IDCODE 0xE0042000
#define ARM_CPUID 0xE000ED00 #define ARM_CPUID 0xE000ED00
#define DBGMCU_CR 0xE0042004
#define DBG_STANDBY (1 << 0)
#define DBG_STOP (1 << 1)
#define DBG_SLEEP (1 << 2)
#define DBGMCU_APB1_FZ 0xE0042008
#define DBG_WWDG_STOP (1 << 11)
#define DBG_IWDG_STOP (1 << 12)
#define AXIM_BASE 0x8000000 #define AXIM_BASE 0x8000000
#define ITCM_BASE 0x0200000 #define ITCM_BASE 0x0200000
@ -271,6 +262,7 @@ static bool stm32f4_attach(target *t)
case ID_STM32F76X: /* F76x F77x RM0410 */ case ID_STM32F76X: /* F76x F77x RM0410 */
is_f7 = true; is_f7 = true;
dual_bank = true; dual_bank = true;
large_sectors = true;
flashsize_base = F7_FLASHSIZE; flashsize_base = F7_FLASHSIZE;
break; break;
case ID_STM32F72X: /* F72x F73x RM0431 */ case ID_STM32F72X: /* F72x F73x RM0431 */
@ -280,7 +272,6 @@ static bool stm32f4_attach(target *t)
default: default:
return false; return false;
} }
target_mem_write32(t, DBGMCU_CR, DBG_STANDBY| DBG_STOP | DBG_SLEEP);
bool use_dual_bank = false; bool use_dual_bank = false;
target_mem_map_free(t); target_mem_map_free(t);
uint32_t flashsize = target_mem_read32(t, flashsize_base) & 0xffff; uint32_t flashsize = target_mem_read32(t, flashsize_base) & 0xffff;
@ -310,7 +301,7 @@ static bool stm32f4_attach(target *t)
int split = 0; int split = 0;
uint32_t banksize; uint32_t banksize;
if (use_dual_bank) { if (use_dual_bank) {
banksize = flashsize << 9; /* flas split on two sectors. */ banksize = flashsize << 9; /* flash split on two sectors. */
split = (flashsize == 0x400) ? 8 : 12; split = (flashsize == 0x400) ? 8 : 12;
} }
else else