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* Added SSP Driver (Not Tested).

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* Replaced leading space by tabulations.
This commit is contained in:
TitanMKD 2012-06-05 01:41:54 +02:00
parent 44db38301c
commit d7a7fd9d30
11 changed files with 1087 additions and 710 deletions
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1
examples/lpc43xx/Makefile.include
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@ -94,6 +94,7 @@ clean:
$(Q)rm -f *.hex
$(Q)rm -f *.srec
$(Q)rm -f *.list
$(Q)rm -f *.map
# FIXME: Replace STM32 stuff with proper LPC43XX OpenOCD support later.
ifeq ($(OOCD_SERIAL),)

19
examples/lpc43xx/hackrf-jellybean/jellybean_conf.h
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@ -27,9 +27,9 @@ extern "C"
#include <libopencm3/lpc43xx/scu.h>
/************************/
/* JellyBean SCU PinMux */
/************************/
/*
* JellyBean SCU PinMux
*/
/* GPIO Output PinMux */
#define SCU_PINMUX_LED1 (P4_1) /* GPIO2[1] on P4_1 */
@ -44,12 +44,17 @@ extern "C"
#define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */
#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
/* SSP1 Peripheral PinMux */
#define SCU_SSP1_MISO (P1_3) /* P1_3 */
#define SCU_SSP1_MOSI (P1_4) /* P1_4 */
#define SCU_SSP1_SCK (P1_19) /* P1_19 */
#define SCU_SSP1_SSEL (P1_20) /* P1_20 */
/* TODO add other Pins */
/**********************/
/* JellyBean GPIO Pin */
/**********************/
/*
* JellyBean GPIO Pin
*/
/* GPIO Output */
#define PIN_LED1 (BIT1) /* GPIO2[1] on P4_1 */
#define PIN_LED2 (BIT2) /* GPIO2[2] on P4_2 */

42
examples/lpc43xx/hackrf-jellybean/miniblink/miniblink.c
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@ -1,22 +1,22 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
@ -40,6 +40,12 @@ void gpio_setup(void)
/* Configure SCU I2C0 Peripheral (to be moved later in I2C driver) */
SCU_SFSI2C0 = SCU_I2C0_NOMINAL;
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
/* Configure all GPIO as Input (safe state) */
GPIO0_DIR = 0;
GPIO1_DIR = 0;

24
examples/lpc43xx/hackrf-jellybean/ssp/Makefile Normal file
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@ -0,0 +1,24 @@
##
## This file is part of the libopencm3 project.
##
## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
##
## This library is free software: you can redistribute it and/or modify
## it under the terms of the GNU Lesser General Public License as published by
## the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This library is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU Lesser General Public License for more details.
##
## You should have received a copy of the GNU Lesser General Public License
## along with this library. If not, see <http://www.gnu.org/licenses/>.
##
BINARY = sspdemo
LDSCRIPT = ../jellybean-lpc4330.ld
include ../../Makefile.include

20
examples/lpc43xx/hackrf-jellybean/ssp/README Normal file
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@ -0,0 +1,20 @@
------------------------------------------------------------------------------
README
------------------------------------------------------------------------------
This program exercises the SSP1 peripheral on Jellybean's LPC43xx.
Jellybean (connector)
P9 SPI
|-----------------|
| Pin2 Pin4 Pin6 |
||------| |
|| Pin1 |Pin3 Pin5 |
||------|----------|
|-------|
SSP1_MISO: Jellybean P9 SPI Pin6
SSP1_MOSI: Jellybean P9 SPI Pin4
SSP1_SCK: Jellybean P9 SPI Pin2
SSP1_SSEL: Jellybean P9 SPI Pin3
GND: Can be connected to P12 SD Pin1

99
examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c Normal file
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@ -0,0 +1,99 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/cgu.h>
#include <libopencm3/lpc43xx/ssp.h>
#include "../jellybean_conf.h"
void gpio_setup(void)
{
/* Configure SCU Pin Mux as GPIO */
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
/* Configure all GPIO as Input (safe state) */
GPIO0_DIR = 0;
GPIO1_DIR = 0;
GPIO2_DIR = 0;
GPIO3_DIR = 0;
GPIO4_DIR = 0;
GPIO5_DIR = 0;
GPIO6_DIR = 0;
GPIO7_DIR = 0;
/* Configure GPIO as Output */
GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
}
int main(void)
{
int i;
u8 ssp_val;
u8 serial_clock_rate;
gpio_setup();
/* FIX Me freq */
serial_clock_rate = 128;
ssp_init(SSP1_NUM,
SSP_DATA_8BITS,
SSP_FRAME_SPI,
SSP_CPOL_0_CPHA_0,
serial_clock_rate,
SSP_MODE_NORMAL,
SSP_MASTER,
SSP_SLAVE_OUT_ENABLE);
ssp_val = 0x0;
while (1) {
ssp_write(SSP1_NUM, (u16)ssp_val);
gpio_set(GPIO2, GPIOPIN1); /* LED on */
for (i = 0; i < 1000; i++) /* Wait a bit. */
__asm__("nop");
gpio_clear(GPIO2, GPIOPIN1); /* LED off */
ssp_val++;
}
return 0;
}

234
include/libopencm3/lpc43xx/scu.h
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@ -1,22 +1,22 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_SCU_H
#define LPC43XX_SCU_H
@ -315,75 +315,75 @@
/* SCU I2C0 Configuration */
/**************************/
/*
* Select input glitch filter time constant for the SCL pin.
* 0 = 50 ns glitch filter.
* 1 = 3ns glitch filter.
*/
* Select input glitch filter time constant for the SCL pin.
* 0 = 50 ns glitch filter.
* 1 = 3ns glitch filter.
*/
#define SCU_SCL_EFP (BIT0)
/* BIT1 Reserved. Always write a 0 to this bit. */
/*
* Select I2C mode for the SCL pin.
* 0 = Standard/Fast mode transmit.
* 1 = Fast-mode Plus transmit.
*/
* Select I2C mode for the SCL pin.
* 0 = Standard/Fast mode transmit.
* 1 = Fast-mode Plus transmit.
*/
#define SCU_SCL_EHD (BIT2)
/*
* Enable the input receiver for the SCL pin.
* Always write a 1 to this bit when using the
* I2C0.
* 0 = Disabled.
* 1 = Enabled.
*/
* Enable the input receiver for the SCL pin.
* Always write a 1 to this bit when using the
* I2C0.
* 0 = Disabled.
* 1 = Enabled.
*/
#define SCU_SCL_EZI_EN (BIT3)
/* BIT4-6 Reserved. */
/*
* Enable or disable input glitch filter for the
* SCL pin. The filter time constant is
* determined by bit EFP.
* 0 = Enable input filter.
* 1 = Disable input filter.
*/
* Enable or disable input glitch filter for the
* SCL pin. The filter time constant is
* determined by bit EFP.
* 0 = Enable input filter.
* 1 = Disable input filter.
*/
#define SCU_SCL_ZIF_DIS (BIT7)
/*
* Select input glitch filter time constant for the SDA pin.
* 0 = 50 ns glitch filter.
* 1 = 3ns glitch filter.
*/
* Select input glitch filter time constant for the SDA pin.
* 0 = 50 ns glitch filter.
* 1 = 3ns glitch filter.
*/
#define SCU_SDA_EFP (BIT8)
/* BIT9 Reserved. Always write a 0 to this bit. */
/*
* Select I2C mode for the SDA pin.
* 0 = Standard/Fast mode transmit.
* 1 = Fast-mode Plus transmit.
*/
* Select I2C mode for the SDA pin.
* 0 = Standard/Fast mode transmit.
* 1 = Fast-mode Plus transmit.
*/
#define SCU_SDA_EHD (BIT10)
/*
* Enable the input receiver for the SDA pin.
* Always write a 1 to this bit when using the
* I2C0.
* 0 = Disabled.
* 1 = Enabled.
*/
* Enable the input receiver for the SDA pin.
* Always write a 1 to this bit when using the
* I2C0.
* 0 = Disabled.
* 1 = Enabled.
*/
#define SCU_SDA_EZI_EN (BIT11)
/* BIT 12-14 - Reserved */
/*
* Enable or disable input glitch filter for the
* SDA pin. The filter time constant is
* determined by bit SDA_EFP.
* 0 = Enable input filter.
* 1 = Disable input filter.
*/
* Enable or disable input glitch filter for the
* SDA pin. The filter time constant is
* determined by bit SDA_EFP.
* 0 = Enable input filter.
* 1 = Disable input filter.
*/
#define SCU_SDA_ZIF_DIS (BIT15)
/* Standard mode for I2C SCL/SDA Standard/Fast mode */
@ -394,35 +394,35 @@
SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN)
/*
* SCU PIN Normal Drive:
* The pin configuration registers for normal-drive pins control the following pins:
* - P0_0 and P0_1
* - P1_0 to P1_16 and P1_18 to P1_20
* - P2_0 to P2_2 and P2_6 to P2_13
* - P3_0 to P3_2 and P3_4 to P3_8
* - P4_0 to P4_10
* - P5_0 to P5_7
* - P6_0 to P6_12
* - P7_0 to P7_7
* - P8_3 to P8_8
* - P9_0 to P9_6
* - PA_0 and PA_4
* - PB_0 to PB_6
* - PC_0 to PC_14
* - PE_0 to PE_15
* - PF_0 to PF_11
*
* Pin configuration registers for High-Drive pins.
* The pin configuration registers for high-drive pins control the following pins:
* - P1_17
* - P2_3 to P2_5
* - P8_0 to P8_2
* - PA_1 to PA_3
*
* Pin configuration registers for High-Speed pins.
* This register controls the following pins:
* - P3_3 and pins CLK0 to CLK3.
*/
* SCU PIN Normal Drive:
* The pin configuration registers for normal-drive pins control the following pins:
* - P0_0 and P0_1
* - P1_0 to P1_16 and P1_18 to P1_20
* - P2_0 to P2_2 and P2_6 to P2_13
* - P3_0 to P3_2 and P3_4 to P3_8
* - P4_0 to P4_10
* - P5_0 to P5_7
* - P6_0 to P6_12
* - P7_0 to P7_7
* - P8_3 to P8_8
* - P9_0 to P9_6
* - PA_0 and PA_4
* - PB_0 to PB_6
* - PC_0 to PC_14
* - PE_0 to PE_15
* - PF_0 to PF_11
*
* Pin configuration registers for High-Drive pins.
* The pin configuration registers for high-drive pins control the following pins:
* - P1_17
* - P2_3 to P2_5
* - P8_0 to P8_2
* - PA_1 to PA_3
*
* Pin configuration registers for High-Speed pins.
* This register controls the following pins:
* - P3_3 and pins CLK0 to CLK3.
*/
typedef enum {
/* Group Port 0 */
P0_0 = (PIN_GROUP0+PIN0),
@ -651,13 +651,13 @@ typedef enum {
} scu_grp_pin_t;
/*
* Pin Configuration to be used for scu_pinmux() parameter scu_conf
* For normal-drive pins, high-drive pins, high-speed pins
*/
* Pin Configuration to be used for scu_pinmux() parameter scu_conf
* For normal-drive pins, high-drive pins, high-speed pins
*/
/*
* Function BIT0 to 2.
* Common to normal-drive pins, high-drive pins, high-speed pins.
*/
* Function BIT0 to 2.
* Common to normal-drive pins, high-drive pins, high-speed pins.
*/
#define SCU_CONF_FUNCTION0 (0x0)
#define SCU_CONF_FUNCTION1 (0x1)
#define SCU_CONF_FUNCTION2 (0x2)
@ -668,45 +668,45 @@ typedef enum {
#define SCU_CONF_FUNCTION7 (0x7)
/*
* Enable pull-down resistor at pad
* By default=0 Disable pull-down.
* Available to normal-drive pins, high-drive pins, high-speed pins
*/
* Enable pull-down resistor at pad
* By default=0 Disable pull-down.
* Available to normal-drive pins, high-drive pins, high-speed pins
*/
#define SCU_CONF_EPD_EN_PULLDOWN (BIT3)
/*
* Disable pull-up resistor at pad.
* By default=0 the pull-up resistor is enabled at reset.
* Available to normal-drive pins, high-drive pins, high-speed pins
*/
* Disable pull-up resistor at pad.
* By default=0 the pull-up resistor is enabled at reset.
* Available to normal-drive pins, high-drive pins, high-speed pins
*/
#define SCU_CONF_EPUN_DIS_PULLUP (BIT4)
/*
* Select Slew Rate.
* By Default=0 Slow.
* Available to normal-drive pins and high-speed pins, reserved for high-drive pins.
*/
* Select Slew Rate.
* By Default=0 Slow.
* Available to normal-drive pins and high-speed pins, reserved for high-drive pins.
*/
#define SCU_CONF_EHS_FAST (BIT5)
/*
* Input buffer enable.
* By Default=0 Disable Input Buffer.
* The input buffer is disabled by default at reset and must be enabled.
* for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins).
* Available to normal-drive pins, high-drive pins, high-speed pins.
*/
* Input buffer enable.
* By Default=0 Disable Input Buffer.
* The input buffer is disabled by default at reset and must be enabled.
* for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins).
* Available to normal-drive pins, high-drive pins, high-speed pins.
*/
#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6)
/*
* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.
* Available to normal-drive pins, high-drive pins, high-speed pins.
*/
* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz.
* Available to normal-drive pins, high-drive pins, high-speed pins.
*/
#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7)
/*
* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9).
* Available to high-drive pins, reserved for others.
*/
* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9).
* Available to high-drive pins, reserved for others.
*/
#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100)
#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200)
#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300)

124
include/libopencm3/lpc43xx/ssp.h
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@ -1,21 +1,21 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Michael Ossmann <mike@ossmann.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LPC43XX_SSP_H
#define LPC43XX_SSP_H
@ -52,6 +52,12 @@
#define SSP0_SR SSP_SR(SSP0)
#define SSP1_SR SSP_SR(SSP1)
#define SSP_SR_TFE BIT0
#define SSP_SR_TNF BIT1
#define SSP_SR_RNE BIT2
#define SSP_SR_RFF BIT3
#define SSP_SR_BSY BIT4
/* Clock Prescale Register */
#define SSP_CPSR(port) MMIO32(port + 0x010)
#define SSP0_CPSR SSP_CPSR(SSP0)
@ -82,4 +88,88 @@
#define SSP0_DMACR SSP_DMACR(SSP0)
#define SSP1_DMACR SSP_DMACR(SSP1)
typedef enum {
SSP0_NUM = 0x0,
SSP1_NUM = 0x1
} ssp_num_t;
/*
* SSP Control Register 0
*/
/* SSP Data Size Bits 0 to 3 */
typedef enum {
SSP_DATA_4BITS = 0x3,
SSP_DATA_5BITS = 0x4,
SSP_DATA_6BITS = 0x5,
SSP_DATA_7BITS = 0x6,
SSP_DATA_8BITS = 0x7,
SSP_DATA_9BITS = 0x8,
SSP_DATA_10BITS = 0x9,
SSP_DATA_11BITS = 0xA,
SSP_DATA_12BITS = 0xB,
SSP_DATA_13BITS = 0xC,
SSP_DATA_14BITS = 0xD,
SSP_DATA_15BITS = 0xE,
SSP_DATA_16BITS = 0xF
} ssp_datasize_t;
/* SSP Frame Format/Type Bits 4 & 5 */
typedef enum {
SSP_FRAME_SPI = 0x00,
SSP_FRAME_TI = BIT4,
SSP_FRAM_MICROWIRE = BIT5
} ssp_frame_format_t;
/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */
typedef enum {
SSP_CPOL_0_CPHA_0 = 0x0,
SSP_CPOL_1_CPHA_0 = BIT6,
SSP_CPOL_0_CPHA_1 = BIT7,
SSP_CPOL_1_CPHA_1 = (BIT6|BIT7)
} ssp_cpol_cpha_t;
/*
* SSP Control Register 1
*/
/* SSP Mode Bit0 */
typedef enum {
SSP_MODE_NORMAL = 0x0,
SSP_MODE_LOOPBACK = BIT0
} ssp_mode_t;
/* SSP Enable Bit1 */
#define SSP_ENABLE BIT1
/* SSP Master/Slave Mode Bit2 */
typedef enum {
SSP_MASTER = 0x0,
SSP_SLAVE = BIT2
} ssp_master_slave_t;
/*
* SSP Slave Output Disable Bit3
* Slave Output Disable. This bit is relevant only in slave mode
* (MS = 1). If it is 1, this blocks this SSP controller from driving the
* transmit data line (MISO).
*/
typedef enum {
SSP_SLAVE_OUT_ENABLE = 0x0,
SSP_SLAVE_OUT_DISABLE = BIT3
} ssp_slave_option_t; /* This option is relevant only in slave mode */
void ssp_disable(ssp_num_t ssp_num);
void ssp_init( ssp_num_t ssp_num,
ssp_datasize_t data_size,
ssp_frame_format_t frame_format,
ssp_cpol_cpha_t cpol_cpha_format,
u8 serial_clock_rate,
ssp_mode_t mode,
ssp_master_slave_t master_slave,
ssp_slave_option_t slave_option);
u16 ssp_read(ssp_num_t ssp_num);
void ssp_write(ssp_num_t ssp_num, u16 data);
#endif

2
lib/lpc43xx/Makefile
View File

@ -31,7 +31,7 @@ CFLAGS = -O2 -g -Wall -Wextra -I../../include -fno-common \
-mfloat-abi=hard -mfpu=fpv4-sp-d16
# ARFLAGS = rcsv
ARFLAGS = rcs
OBJS = gpio.o vector.o scu.o
OBJS = gpio.o vector.o scu.o ssp.o
# VPATH += ../usb

34
lib/lpc43xx/scu.c
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@ -1,21 +1,21 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/lpc43xx/scu.h>

132
lib/lpc43xx/ssp.c Normal file
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@ -0,0 +1,132 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/lpc43xx/ssp.h>
#include <libopencm3/lpc43xx/cgu.h>
#define CGU_SRC_32K 0x00
#define CGU_SRC_IRC 0x01
#define CGU_SRC_ENET_RX 0x02
#define CGU_SRC_ENET_TX 0x03
#define CGU_SRC_GP_CLKIN 0x04
#define CGU_SRC_XTAL 0x06
#define CGU_SRC_PLL0USB 0x07
#define CGU_SRC_PLL0AUDIO 0x08
#define CGU_SRC_PLL1 0x09
#define CGU_SRC_IDIVA 0x0C
#define CGU_SRC_IDIVB 0x0D
#define CGU_SRC_IDIVC 0x0E
#define CGU_SRC_IDIVD 0x0F
#define CGU_SRC_IDIVE 0x10
#define CGU_AUTOBLOCK_CLOCK_BIT 11
#define CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
/* Disable SSP */
void ssp_disable(ssp_num_t ssp_num)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
ssp_port = SSP0;
}else
{
ssp_port = SSP1;
}
/* Disable SSP */
SSP_CR1(ssp_port) = 0x0;
}
/*
* SSP Init function
*/
void ssp_init(ssp_num_t ssp_num,
ssp_datasize_t data_size,
ssp_frame_format_t frame_format,
ssp_cpol_cpha_t cpol_cpha_format,
u8 serial_clock_rate,
ssp_mode_t mode,
ssp_master_slave_t master_slave,
ssp_slave_option_t slave_option)
{
u32 ssp_port;
u32 clock;
if(ssp_num == SSP0_NUM)
{
ssp_port = SSP0;
}else
{
ssp_port = SSP1;
}
/* use PLL1 as clock source for SSP1 */
CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1<<CGU_BASE_CLK_SEL_SHIFT) | (1<<CGU_AUTOBLOCK_CLOCK_BIT);
/* Disable SSP before to configure it */
SSP_CR1(ssp_port) = 0x0;
/* Configure SSP */
clock = serial_clock_rate;
SSP_CR0(ssp_port) = (data_size | frame_format | cpol_cpha_format | (clock<<8) );
/* Enable SSP */
SSP_CR1(ssp_port) = (SSP_ENABLE | mode | master_slave | slave_option);
}
/*
* This Function Wait until Data RX Ready, and return Data Read from SSP.
*/
u16 ssp_read(ssp_num_t ssp_num)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
ssp_port = SSP0;
}else
{
ssp_port = SSP1;
}
/* Wait Until Data Received (Rx FIFO not Empty) */
while( (SSP_SR(ssp_port) & SSP_SR_RNE) == 0);
return SSP_DR(ssp_port);
}
/* This Function Wait Data TX Ready, and Write Data to SSP */
void ssp_write(ssp_num_t ssp_num, u16 data)
{
u32 ssp_port;
if(ssp_num == SSP0_NUM)
{
ssp_port = SSP0;
}else
{
ssp_port = SSP1;
}
/* Wait Until FIFO not full */
while( (SSP_SR(ssp_port) & SSP_SR_TNF) == 0);
SSP_DR(ssp_port) = data;
}