Merge commit '7ccbdd98c0bd18c2a672ed50aa1f96aff97dd4af' into sam-update

src/gdb_main.c

@@ -374,7 +374,8 @@ handle_q_packet(char *packet, int len)
 		else if(c == 0)
 			gdb_putpacketz("OK");
 		else
-			gdb_putpacketz("E");
+			gdb_putpacket(hexify(pbuf, "Failed\n", strlen("Failed\n")),
+						  2 * strlen("Failed\n"));
 
 	} else if (!strncmp (packet, "qSupported", 10)) {
 		/* Query supported protocol features */

src/platforms/f4discovery/Readme.md

@@ -54,7 +54,7 @@ To exit from dfu mode press a "key" and "reset", release reset. BMP firmware sho
 10 pin male from pins
 ========================================
 
-| PB3/TDO  | PB7/RX      | PB8/TX     | X          | PA1/TDI |
+| PB3/TDO  | PB7/RX      | PB6/TX     | X          | PA1/TDI |
 | -------- | ----------- | ---------- | ---------- | ------- |
 | PB4/SRST | +3V3/PB8 SW | PA13/SWDIO | PA14/SWCLK | GND     |
 

src/platforms/f4discovery/platform.h

@@ -79,6 +79,26 @@
 #define LED_IDLE_RUN GPIO15
 #define LED_ERROR GPIO14
 #define LED_BOOTLOADER GPIO13
+
+#define USBUSART USART1
+#define USBUSART_CR1 USART1_CR1
+#define USBUSART_DR USART1_DR
+#define USBUSART_IRQ NVIC_USART1_IRQ
+#define USBUSART_CLK RCC_USART1
+#define USBUSART_PORT GPIOB
+#define USBUSART_TX_PIN GPIO6
+#define USBUSART_RX_PIN GPIO7
+#define USBUSART_ISR(x) usart1_isr(x)
+#define USBUSART_DMA_BUS DMA2
+#define USBUSART_DMA_CLK RCC_DMA2
+#define USBUSART_DMA_TX_CHAN DMA_STREAM7
+#define USBUSART_DMA_TX_IRQ NVIC_DMA2_STREAM7_IRQ
+#define USBUSART_DMA_TX_ISR(x) dma2_stream7_isr(x)
+#define USBUSART_DMA_RX_CHAN DMA_STREAM5
+#define USBUSART_DMA_RX_IRQ NVIC_DMA2_STREAM5_IRQ
+#define USBUSART_DMA_RX_ISR(x) dma2_stream5_isr(x)
+/* For STM32F4 DMA trigger source must be specified */
+#define USBUSART_DMA_TRG DMA_SxCR_CHSEL_4
 #else
 #define PLATFORM_IDENT "(F4Discovery) "
 
@@ -127,6 +147,26 @@
 #define LED_IDLE_RUN	GPIO13
 #define LED_ERROR	GPIO14
 #define LED_BOOTLOADER	GPIO15
+
+#define USBUSART USART3
+#define USBUSART_CR1 USART3_CR1
+#define USBUSART_DR USART3_DR
+#define USBUSART_IRQ NVIC_USART3_IRQ
+#define USBUSART_CLK RCC_USART3
+#define USBUSART_PORT GPIOD
+#define USBUSART_TX_PIN GPIO8
+#define USBUSART_RX_PIN GPIO9
+#define USBUSART_ISR(x) usart3_isr(x)
+#define USBUSART_DMA_BUS DMA1
+#define USBUSART_DMA_CLK RCC_DMA1
+#define USBUSART_DMA_TX_CHAN DMA_STREAM3
+#define USBUSART_DMA_TX_IRQ NVIC_DMA1_STREAM3_IRQ
+#define USBUSART_DMA_TX_ISR(x) dma1_stream3_isr(x)
+#define USBUSART_DMA_RX_CHAN DMA_STREAM1
+#define USBUSART_DMA_RX_IRQ NVIC_DMA1_STREAM1_IRQ
+#define USBUSART_DMA_RX_ISR(x) dma1_stream1_isr(x)
+/* For STM32F4 DMA trigger source must be specified */
+#define USBUSART_DMA_TRG DMA_SxCR_CHSEL_4
 #endif
 
 #define BOOTMAGIC0 0xb007da7a
@@ -166,25 +206,6 @@
 #define IRQ_PRI_USBUSART_DMA 	(2 << 4)
 #define IRQ_PRI_TRACE		(0 << 4)
 
-#define USBUSART USART3
-#define USBUSART_CR1 USART3_CR1
-#define USBUSART_DR USART3_DR
-#define USBUSART_IRQ NVIC_USART3_IRQ
-#define USBUSART_CLK RCC_USART3
-#define USBUSART_PORT GPIOD
-#define USBUSART_TX_PIN GPIO8
-#define USBUSART_RX_PIN GPIO9
-#define USBUSART_ISR(x) usart3_isr(x)
-#define USBUSART_DMA_BUS DMA1
-#define USBUSART_DMA_CLK RCC_DMA1
-#define USBUSART_DMA_TX_CHAN DMA_STREAM3
-#define USBUSART_DMA_TX_IRQ NVIC_DMA1_STREAM3_IRQ
-#define USBUSART_DMA_TX_ISR(x) dma1_stream3_isr(x)
-#define USBUSART_DMA_RX_CHAN DMA_STREAM1
-#define USBUSART_DMA_RX_IRQ NVIC_DMA1_STREAM1_IRQ
-#define USBUSART_DMA_RX_ISR(x) dma1_stream1_isr(x)
-/* For STM32F4 DMA trigger source must be specified */
-#define USBUSART_DMA_TRG DMA_SxCR_CHSEL_4
 
 #define TRACE_TIM TIM3
 #define TRACE_TIM_CLK_EN() rcc_periph_clock_enable(RCC_TIM3)

src/platforms/hosted/dap.c

@@ -323,10 +323,14 @@ static void dap_line_reset(void)
 
 static uint32_t wait_word(uint8_t *buf, int size, int len, uint8_t *dp_fault)
 {
+	uint8_t cmd_copy[len];
+	memcpy(cmd_copy, buf, len);
 	do {
 		dbg_dap_cmd(buf, size, len);
 		if (buf[1] < DAP_TRANSFER_WAIT)
 			break;
+		if (buf[1] == DAP_TRANSFER_WAIT)
+			memcpy(buf, cmd_copy, len);
 	} while (buf[1] == DAP_TRANSFER_WAIT);
 
 	if (buf[1] > DAP_TRANSFER_WAIT) {

src/platforms/pc/cl_utils.c

@@ -448,7 +448,9 @@ int cl_execute(BMP_CL_OPTIONS_t *opt)
 			DEBUG_WARN("No test for this core type yet\n");
 		}
 	} else if (opt->opt_mode == BMP_MODE_MONITOR) {
-		command_process(t, opt->opt_monitor);
+		res = command_process(t, opt->opt_monitor);
+		if (res)
+			DEBUG_WARN("Command \"%s\" failed\n", opt->opt_monitor);
 	}
 	if ((opt->opt_mode == BMP_MODE_TEST) ||
 		(opt->opt_mode == BMP_MODE_SWJ_TEST))

src/target/adiv5.c

@@ -330,7 +330,6 @@ static uint32_t cortexm_initial_halt(ADIv5_AP_t *ap)
 	bool use_low_access = (!is_mindp);
 #endif
 	if (use_low_access) {
-		DEBUG_WARN("Using low access\n");
 		/* ap_mem_access_setup() sets ADIV5_AP_CSW_ADDRINC_SINGLE -> unusable!*/
 		adiv5_ap_write(ap, ADIV5_AP_CSW, ap->csw | ADIV5_AP_CSW_SIZE_WORD);
 		adiv5_dp_low_access(ap->dp, ADIV5_LOW_WRITE, ADIV5_AP_TAR, CORTEXM_DHCSR);

src/target/stm32f1.c

@@ -70,6 +70,7 @@ static int stm32f1_flash_write(struct target_flash *f,
 
 #define FLASH_CR_OBL_LAUNCH (1<<13)
 #define FLASH_CR_OPTWRE	(1 << 9)
+#define FLASH_CR_LOCK	(1 << 7)
 #define FLASH_CR_STRT	(1 << 6)
 #define FLASH_CR_OPTER	(1 << 5)
 #define FLASH_CR_OPTPG	(1 << 4)
@@ -242,10 +243,16 @@ bool stm32f1_probe(target *t)
 	return true;
 }
 
-static void stm32f1_flash_unlock(target *t, uint32_t bank_offset)
+static int stm32f1_flash_unlock(target *t, uint32_t bank_offset)
 {
 	target_mem_write32(t, FLASH_KEYR + bank_offset, KEY1);
 	target_mem_write32(t, FLASH_KEYR + bank_offset, KEY2);
+	uint32_t cr = target_mem_read32(t, FLASH_CR);
+	if (cr & FLASH_CR_LOCK) {
+		DEBUG_WARN("unlock failed, cr: 0x%08" PRIx32 "\n", cr);
+		return -1;
+	}
+	return 0;
 }
 
 static int stm32f1_flash_erase(struct target_flash *f,
@@ -256,9 +263,11 @@ static int stm32f1_flash_erase(struct target_flash *f,
 	target_addr start = addr;
 
 	if ((t->idcode == 0x430) && (end >= FLASH_BANK_SPLIT))
-		stm32f1_flash_unlock(t, FLASH_BANK2_OFFSET);
+		if (stm32f1_flash_unlock(t, FLASH_BANK2_OFFSET))
+			return -1;
 	if (addr < FLASH_BANK_SPLIT)
-		stm32f1_flash_unlock(t, 0);
+		if (stm32f1_flash_unlock(t, 0))
+			return -1;
 	while(len) {
 		uint32_t bank_offset = 0;
 		if (addr >= FLASH_BANK_SPLIT)
@@ -358,7 +367,8 @@ static bool stm32f1_cmd_erase_mass(target *t, int argc, const char **argv)
 {
 	(void)argc;
 	(void)argv;
-	stm32f1_flash_unlock(t, 0);
+	if (stm32f1_flash_unlock(t, 0))
+		return false;
 
 	/* Flash mass erase start instruction */
 	target_mem_write32(t, FLASH_CR, FLASH_CR_MER);
@@ -374,7 +384,8 @@ static bool stm32f1_cmd_erase_mass(target *t, int argc, const char **argv)
 	if ((sr & SR_ERROR_MASK) || !(sr & SR_EOP))
 		return false;
 	if (t->idcode == 0x430) {
-		stm32f1_flash_unlock(t, FLASH_BANK2_OFFSET);
+		if (stm32f1_flash_unlock(t, FLASH_BANK2_OFFSET))
+			return false;
 
 		/* Flash mass erase start instruction on bank 2*/
 		target_mem_write32(t, FLASH_CR + FLASH_BANK2_OFFSET, FLASH_CR_MER);
@@ -469,7 +480,8 @@ static bool stm32f1_cmd_option(target *t, int argc, const char **argv)
 	default: flash_obp_rdp_key = FLASH_OBP_RDP_KEY;
 	}
 	rdprt = target_mem_read32(t, FLASH_OBR) & FLASH_OBR_RDPRT;
-	stm32f1_flash_unlock(t, 0);
+	if (stm32f1_flash_unlock(t, 0))
+		return false;
 	target_mem_write32(t, FLASH_OPTKEYR, KEY1);
 	target_mem_write32(t, FLASH_OPTKEYR, KEY2);
 

src/target/target.c

@@ -574,7 +574,7 @@ int target_command(target *t, int argc, const char *argv[])
 	for (struct target_command_s *tc = t->commands; tc; tc = tc->next)
 		for(const struct command_s *c = tc->cmds; c->cmd; c++)
 			if(!strncmp(argv[0], c->cmd, strlen(argv[0])))
-				return !c->handler(t, argc, argv);
+				return (c->handler(t, argc, argv)) ? 0 : 1;
 	return -1;
 }