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Merging pull request #23 Changed markup to get more control over documentation.

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Merge remote-tracking branch 'ksarkies/doc'
This commit is contained in:
Piotr Esden-Tempski 2012-08-25 15:16:50 -07:00
commit d98dab6ae2
19 changed files with 1588 additions and 290 deletions
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22
include/libopencm3/cm3/docmain.h
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@ -1,6 +1,12 @@
/**
* @mainpage libopencm3 Developer Documentation
*
@version 1.0.0
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
@date 18 August 2012
* The libopencm3 project (previously known as libopenstm32) aims to create
* a free/libre/open-source (GPL v3, or later) firmware library for various
* ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03,
@ -31,33 +37,33 @@ program. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup LM3S
/** @defgroup LM3S LM3S
Libraries for Texas instruments LM3S series.
*/
/** @defgroup LPC13xx
/** @defgroup LPC13xx LPC13xx
Libraries for NXP Semiconductor LPC13xx series.
*/
/** @defgroup LPC17xx
/** @defgroup LPC17xx LPC17xx
Libraries for NXP Semiconductor LPC17xx series.
*/
/** @defgroup STM32F
/** @defgroup STM32F STM32F
Libraries for ST Microelectronics STM32F series.
*/
/** @defgroup STM32F1xx
/** @defgroup STM32F1xx STM32F1xx
@ingroup STM32F
Libraries for ST Microelectronics STM32F1xx series.
*/
/** @defgroup STM32F2xx
/** @defgroup STM32F2xx STM32F2xx
@ingroup STM32F
Libraries for ST Microelectronics STM32F2xx series.
*/
/** @defgroup STM32F4xx
/** @defgroup STM32F4xx STM32F4xx
@ingroup STM32F
Libraries for ST Microelectronics STM32F4xx series.
*/

32
include/libopencm3/stm32/dac.h
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@ -1,27 +1,19 @@
/** @file
/** @defgroup STM32F_dac_defines DAC Defines
@ingroup STM32F
@brief <b>libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter </b>
@brief <b>libopencm3 STM32F Digital to Analog Converter</b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Felix Held <felix-libopencm3@felixheld.de>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies
@date 30 June 2012
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F_dac_defines
@brief Defined Constants and Types for the STM32F Digital to Analog Converter
@ingroup STM32F_defines
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@ -41,6 +33,8 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_DAC_H
#define LIBOPENCM3_DAC_H
@ -121,7 +115,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
/*@}*/
/**@}*/
/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
/* Legend:
@ -143,7 +137,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
@{*/
#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
/*@}*/
/**@}*/
/* TSEL2[2:0]: DAC channel2 trigger selection */
/* Legend:
@ -193,7 +187,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
/*@}*/
/**@}*/
/* TEN2: DAC channel2 trigger enable */
#define DAC_CR_TEN2 (1 << 18)
@ -233,7 +227,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
/*@}*/
/**@}*/
/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
/* Legend:
@ -256,7 +250,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
@{*/
#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
/*@}*/
/**@}*/
/* TSEL1[2:0]: DAC channel1 trigger selection */
/* Legend:
@ -306,7 +300,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
/*@}*/
/**@}*/
/* TEN1: DAC channel1 trigger enable */
#define DAC_CR_TEN1 (1 << 2)
@ -416,3 +410,5 @@ void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data
void dac_software_trigger(data_channel dac_channel);
#endif
/**@}*/

15
include/libopencm3/stm32/doc-stm32f.h
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@ -1,13 +1,24 @@
/** @defgroup STM32F_defines
/** @defgroup STM32F_defines STM32F Top Level Defines
@brief Defined Constants and Types for the STM32F series
@ingroup STM32F
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
@version 1.0.0
@date 8 July 2012
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F-files STM32F Top Level Files
@brief Common Files for ST Microelectronics STM32F series.
@ingroup STM32F
*/

38
include/libopencm3/stm32/f1/dma.h
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@ -1,3 +1,17 @@
/** @defgroup STM32F1xx_dma_defines DMA Defines
@ingroup STM32F1xx_defines
@brief Defined Constants and Types for the STM32F1xx DMA Controller
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@ -18,6 +32,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_DMA_H
#define LIBOPENCM3_DMA_H
@ -241,24 +257,39 @@
#define DMA_CCR_MEM2MEM (1 << 14)
/* PL[13:12]: Channel priority level */
/** @defgroup dma_ch_pri DMA Channel Priority Levels
@ingroup STM32F1xx_dma_defines
@{*/
#define DMA_CCR_PL_LOW (0x0 << 12)
#define DMA_CCR_PL_MEDIUM (0x1 << 12)
#define DMA_CCR_PL_HIGH (0x2 << 12)
#define DMA_CCR_PL_VERY_HIGH (0x3 << 12)
/**@}*/
#define DMA_CCR_PL_MASK (0x3 << 12)
#define DMA_CCR_PL_SHIFT 12
/* MSIZE[11:10]: Memory size */
/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width
@ingroup STM32F1xx_dma_defines
@{*/
#define DMA_CCR_MSIZE_8BIT (0x0 << 10)
#define DMA_CCR_MSIZE_16BIT (0x1 << 10)
#define DMA_CCR_MSIZE_32BIT (0x2 << 10)
/**@}*/
#define DMA_CCR_MSIZE_MASK (0x3 << 10)
#define DMA_CCR_MSIZE_SHIFT 10
/* PSIZE[9:8]: Peripheral size */
/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width
@ingroup STM32F1xx_dma_defines
@{*/
#define DMA_CCR_PSIZE_8BIT (0x0 << 8)
#define DMA_CCR_PSIZE_16BIT (0x1 << 8)
#define DMA_CCR_PSIZE_32BIT (0x2 << 8)
/**@}*/
#define DMA_CCR_PSIZE_MASK (0x3 << 8)
#define DMA_CCR_PSIZE_SHIFT 8
@ -300,6 +331,10 @@
/* --- Generic values ------------------------------------------------------ */
/** @defgroup dma_ch DMA Channel Number
@ingroup STM32F1xx_dma_defines
@{*/
#define DMA_CHANNEL1 1
#define DMA_CHANNEL2 2
#define DMA_CHANNEL3 3
@ -307,6 +342,7 @@
#define DMA_CHANNEL5 5
#define DMA_CHANNEL6 6
#define DMA_CHANNEL7 7
/**@}*/
/* --- function prototypes ------------------------------------------------- */
@ -333,3 +369,5 @@ void dma_set_memory_address(u32 dma, u8 channel, u32 address);
void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
#endif
/**@}*/

6
include/libopencm3/stm32/f1/doc-stm32f1.h
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@ -1,12 +1,14 @@
/** @defgroup STM32F1xx_defines
/** @defgroup STM32F1xx_defines STM32F1xx Defines
@brief Defined Constants and Types for the STM32F1xx series
@ingroup STM32F1xx
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
@version 1.0.0
@date 24 May 2012
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/

254
include/libopencm3/stm32/f1/gpio.h
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@ -1,3 +1,18 @@
/** @defgroup STM32F1xx_gpio_defines GPIO Defines
@brief <b>Defined Constants and Types for the STM32F1xx General Purpose I/O</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
@date 1 July 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@ -17,6 +32,7 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_GPIO_H
#define LIBOPENCM3_GPIO_H
@ -27,6 +43,10 @@
/* --- Convenience macros -------------------------------------------------- */
/* GPIO port base addresses (for convenience) */
/** @defgroup gpio_port_id GPIO Port IDs
@ingroup STM32F1xx_gpio_defines
@{*/
#define GPIOA GPIO_PORT_A_BASE
#define GPIOB GPIO_PORT_B_BASE
#define GPIOC GPIO_PORT_C_BASE
@ -34,8 +54,13 @@
#define GPIOE GPIO_PORT_E_BASE
#define GPIOF GPIO_PORT_F_BASE
#define GPIOG GPIO_PORT_G_BASE
/**@}*/
/* GPIO number definitions (for convenience) */
/** @defgroup gpio_pin_id GPIO Pin Identifiers
@ingroup STM32F1xx_gpio_defines
@{*/
#define GPIO0 (1 << 0)
#define GPIO1 (1 << 1)
#define GPIO2 (1 << 2)
@ -53,6 +78,7 @@
#define GPIO14 (1 << 14)
#define GPIO15 (1 << 15)
#define GPIO_ALL 0xffff
/**@}*/
/* --- Alternate function GPIOs -------------------------------------------- */
@ -593,22 +619,50 @@
/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */
/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
#define GPIO_CNF_INPUT_ANALOG 0x00
#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */
#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02
/** @defgroup gpio_cnf GPIO Pin Configuration
@ingroup STM32F1xx_gpio_defines
If mode specifies input, configuration can be
@li Analog input
@li Floating input
@li Pull up/down input
/* Output mode (MODE[1:0]) values */
#define GPIO_MODE_INPUT 0x00 /* Default */
If mode specifies output, configuration can be
@li Digital push-pull
@li Digital open drain
@li Alternate function push-pull or analog output
@li Alternate function open drain or analog output
@{*/
/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
/** Analog Input */
#define GPIO_CNF_INPUT_ANALOG 0x00
/** Digital Input Floating */
#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */
/** Digital Input Pull Up and Down */
#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02
/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
/** Digital Output Pushpull */
#define GPIO_CNF_OUTPUT_PUSHPULL 0x00
/** Digital Output Open Drain */
#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01
/** Alternate Function Output Pushpull */
#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02
/** Alternate Function Output Open Drain */
#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03
/**@}*/
/* Pin mode (MODE[1:0]) values */
/** @defgroup gpio_mode GPIO Pin Mode
@ingroup STM32F1xx_gpio_defines
@li Input (default after reset)
@li Output mode at 10 MHz maximum speed
@li Output mode at 2 MHz maximum speed
@li Output mode at 50 MHz maximum speed
@{*/
#define GPIO_MODE_INPUT 0x00 /* Default */
#define GPIO_MODE_OUTPUT_10_MHZ 0x01
#define GPIO_MODE_OUTPUT_2_MHZ 0x02
#define GPIO_MODE_OUTPUT_50_MHZ 0x03
/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
#define GPIO_CNF_OUTPUT_PUSHPULL 0x00
#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01
#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02
#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03
/**@}*/
/* --- GPIO_IDR values ----------------------------------------------------- */
@ -652,19 +706,31 @@
/* External interrupt configuration register 4 (AFIO_EXTICR4) */
#define AFIO_EXTICR4 MMIO32(AFIO_BASE + 0x14)
/* AF remap and debug I/O configuration register (AFIO_MAPR) */
#define AFIO_MAPR2 MMIO32(AFIO_BASE + 0x1C)
/* --- AFIO_EVCR values ---------------------------------------------------- */
/* EVOE: Event output enable */
#define AFIO_EVCR_EVOE (1 << 7)
/* PORT[2:0]: Port selection */
/** @defgroup afio_evcr_port EVENTOUT Port selection
@ingroup STM32F1xx_gpio_defines
@{*/
#define AFIO_EVCR_PORT_PA (0x0 << 4)
#define AFIO_EVCR_PORT_PB (0x1 << 4)
#define AFIO_EVCR_PORT_PC (0x2 << 4)
#define AFIO_EVCR_PORT_PD (0x3 << 4)
#define AFIO_EVCR_PORT_PE (0x4 << 4)
/**@}*/
/* PIN[3:0]: Pin selection */
/** @defgroup afio_evcr_pin EVENTOUT Pin selection
@ingroup STM32F1xx_gpio_defines
@{*/
#define AFIO_EVCR_PIN_Px0 (0x0 << 0)
#define AFIO_EVCR_PIN_Px1 (0x1 << 0)
#define AFIO_EVCR_PIN_Px2 (0x2 << 0)
@ -681,117 +747,206 @@
#define AFIO_EVCR_PIN_Px13 (0xD << 0)
#define AFIO_EVCR_PIN_Px14 (0xE << 0)
#define AFIO_EVCR_PIN_Px15 (0xF << 0)
/**@}*/
/* --- AFIO_MAPR values ---------------------------------------------------- */
/* 31 reserved */
/* PTP_PPS_REMAP: Ethernet PTP PPS remapping
/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity
Line Devices only
@ingroup STM32F1xx_gpio_defines
@{*/
/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping
* (only connectivity line devices) */
#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30)
/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
/* TIM2ITR1_IREMAP: *//** TIM2 internal trigger 1 remapping
* (only connectivity line devices) */
#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29)
/* SPI3_REMAP: SPI3/I2S3 remapping
/* SPI3_REMAP: *//** SPI3/I2S3 remapping
* (only connectivity line devices) */
#define AFIO_MAPR_SPI3_REMAP (1 << 28)
/* MII_REMAP: */ /** MII or RMII selection
* (only connectivity line devices) */
#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
/* CAN2_REMAP: */ /** CAN2 I/O remapping
* (only connectivity line devices) */
#define AFIO_MAPR_CAN2_REMAP (1 << 22)
/* ETH_REMAP: */ /** Ethernet MAC I/O remapping
* (only connectivity line devices) */
#define AFIO_MAPR_ETH_REMAP (1 << 21)
/**@}*/
/* 27 reserved */
/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
/** @defgroup afio_swj_disable Serial Wire JTAG disables
@ingroup STM32F1xx_gpio_defines
@{*/
#define AFIO_MAPR_SWJ_MASK (0x7 << 24)
/** Full Serial Wire JTAG capability */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
/** Full Serial Wire JTAG capability without JNTRST */
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
/** JTAG-DP disabled with SW-DP enabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
/** JTAG-DP disabled and SW-DP disabled */
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24)
/**@}*/
/* MII_REMAP: MII or RMII selection
* (only connectivity line devices) */
#define AFIO_MAPR_MII_RMII_SEL (1 << 23)
/** @defgroup afio_remap Alternate Function Remap Controls
@ingroup STM32F1xx_gpio_defines
/* CAN2_REMAP: CAN2 I/O remapping
* (only connectivity line devices) */
#define AFIO_MAPR_CAN2_REMAP (1 << 22)
/* ETH_REMAP: Ethernet MAC I/O remapping
* (only connectivity line devices) */
#define AFIO_MAPR_ETH_REMAP (1 << 21)
/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping
@{*/
/* ADC2_ETRGREG_REMAP: */ /** ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping
/* ADC2_ETRGINJ_REMAP: */ /** ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping
/* ADC1_ETRGREG_REMAP: */ /** ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping
/* ADC1_ETRGINJ_REMAP: */ /** ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) */
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */
/* TIM5CH4_IREMAP: */ /** TIM5 channel4 internal remap */
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
/* PD01_REMAP: */ /** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_MAPR_PD01_REMAP (1 << 15)
/* TIM4_REMAP: */ /** TIM4 remapping */
#define AFIO_MAPR_TIM4_REMAP (1 << 12)
/* USART2_REMAP[1:0]: */ /** USART2 remapping */
#define AFIO_MAPR_USART2_REMAP (1 << 3)
/* USART1_REMAP[1:0]: */ /** USART1 remapping */
#define AFIO_MAPR_USART1_REMAP (1 << 2)
/* I2C1_REMAP[1:0]: */ /** I2C1 remapping */
#define AFIO_MAPR_I2C1_REMAP (1 << 1)
/* SPI1_REMAP[1:0]: */ /** SPI1 remapping */
#define AFIO_MAPR_SPI1_REMAP (1 << 0)
/**@}*/
/* CAN_REMAP[1:0]: CAN1 alternate function remapping */
/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1
@ingroup STM32F1xx_gpio_defines
@{*/
#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13)
#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */
#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13)
/* TIM4_REMAP: TIM4 remapping */
#define AFIO_MAPR_TIM4_REMAP (1 << 12)
/**@}*/
/* TIM3_REMAP[1:0]: TIM3 remapping */
/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3
@ingroup STM32F1xx_gpio_defines
@{*/
#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10)
#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10)
#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10)
/**@}*/
/* TIM2_REMAP[1:0]: TIM2 remapping */
/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2
@ingroup STM32F1xx_gpio_defines
@{*/
#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8)
#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8)
#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8)
/**@}*/
/* TIM1_REMAP[1:0]: TIM1 remapping */
/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1
@ingroup STM32F1xx_gpio_defines
@{*/
#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6)
#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6)
#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6)
/**@}*/
/* USART3_REMAP[1:0]: USART3 remapping */
/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3
@ingroup STM32F1xx_gpio_defines
@{*/
#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4)
#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4)
#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4)
/**@}*/
/* USART2_REMAP[1:0]: USART2 remapping */
#define AFIO_MAPR_USART2_REMAP (1 << 3)
/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set
@ingroup STM32F1xx_gpio_defines
/* USART1_REMAP[1:0]: USART1 remapping */
#define AFIO_MAPR_USART1_REMAP (1 << 2)
@{*/
/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */
#define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10)
/* I2C1_REMAP[1:0]: I2C1 remapping */
#define AFIO_MAPR_I2C1_REMAP (1 << 1)
/* TIM14_REMAP: */ /** TIM14 remapping */
#define AFIO_MAPR2_TIM14_REMAP (1 << 9)
/* SPI1_REMAP[1:0]: SPI1 remapping */
#define AFIO_MAPR_SPI1_REMAP (1 << 0)
/* TIM13_REMAP: */ /** TIM13 remapping */
#define AFIO_MAPR2_TIM13_REMAP (1 << 8)
/* TIM11_REMAP: */ /** TIM11 remapping */
#define AFIO_MAPR2_TIM11_REMAP (1 << 7)
/* TIM10_REMAP: */ /** TIM10 remapping */
#define AFIO_MAPR2_TIM10_REMAP (1 << 6)
/* TIM9_REMAP: */ /** TIM9 remapping */
#define AFIO_MAPR2_TIM9_REMAP (1 << 5)
/**@}*/
/* --- AFIO_EXTICR1 values ------------------------------------------------- */
/* --- AFIO_EXTICR2 values ------------------------------------------------- */
/* --- AFIO_EXTICR3 values ------------------------------------------------- */
/* --- AFIO_EXTICR4 values ------------------------------------------------- */
/* EXTI0 - EXTI15 interrupt source selection registers */
/** @defgroup afio_exti Alternate Function EXTI pin number
@ingroup STM32F1xx_gpio_defines
/* Note: For using them we should define a function that calculates the right
* registers, using definitions is probably not a good idea.
*/
@{*/
#define AFIO_EXTI0 0
#define AFIO_EXTI1 1
#define AFIO_EXTI2 2
#define AFIO_EXTI3 3
#define AFIO_EXTI4 4
#define AFIO_EXTI5 5
#define AFIO_EXTI6 6
#define AFIO_EXTI7 7
#define AFIO_EXTI8 8
#define AFIO_EXTI9 9
#define AFIO_EXTI10 10
#define AFIO_EXTI11 11
#define AFIO_EXTI12 12
#define AFIO_EXTI13 13
#define AFIO_EXTI14 14
#define AFIO_EXTI15 15
/**@}*/
/* --- Function prototypes ------------------------------------------------- */
@ -803,5 +958,10 @@ void gpio_toggle(u32 gpioport, u16 gpios);
u16 gpio_port_read(u32 gpioport);
void gpio_port_write(u32 gpioport, u16 data);
void gpio_port_config_lock(u32 gpioport, u16 gpios);
void gpio_set_eventout(u8 evoutport, u8 evoutpin);
void gpio_primary_remap(u8 swjenable, u32 maps);
void gpio_secondary_remap(u32 maps);
#endif
/**@}*/

96
include/libopencm3/stm32/f1/rcc.h
View File

@ -1,26 +1,17 @@
/** @file
@ingroup STM32F1xx
/** @defgroup STM32F1xx_rcc_defines RCC Defines
@brief <b>libopencm3 STM32F1xx Reset and Clock Control</b>
@ingroup STM32F1xx_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@date 18 May 2012
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F1xx_rcc_defines
@brief Defined Constants and Types for the STM32F1xx Reset and Clock Control
@ingroup STM32F1xx_defines
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
@ -41,6 +32,7 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_RCC_H
#define LIBOPENCM3_RCC_H
@ -86,6 +78,10 @@ LGPL License Terms @ref lgpl_license
/* --- RCC_CFGR values ----------------------------------------------------- */
/* MCO: Microcontroller clock output */
/** @defgroup rcc_cfgr_co RCC_CFGR Microcontroller Clock Output Source
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_MCO_NOCLK 0x0
#define RCC_CFGR_MCO_SYSCLK 0x4
#define RCC_CFGR_MCO_HSICLK 0x5
@ -95,16 +91,26 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */
#define RCC_CFGR_MCO_XT1 0xa /* (**) */
#define RCC_CFGR_MCO_PLL3 0xb /* (**) */
/**@}*/
/* USBPRE: USB prescaler (RCC_CFGR[22]) */
/** @defgroup rcc_cfgr_usbpre RCC_CFGR USB prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0
#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1
/**@}*/
/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0
#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1
/* PLLMUL: PLL multiplication factor */
/** @defgroup rcc_cfgr_pmf RCC_CFGR PLL Multiplication Factor
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2
@ -122,38 +128,69 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */
#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */
// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */
/**@}*/
/* TODO: conn. line differs. */
/* PLLXTPRE: HSE divider for PLL entry */
/** @defgroup rcc_cfgr_hsepre RCC_CFGR HSE Divider for PLL
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0
#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1
/**@}*/
/* PLLSRC: PLL entry clock source */
/** @defgroup rcc_cfgr_pcs RCC_CFGR PLL Clock Source
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0
#define RCC_CFGR_PLLSRC_HSE_CLK 0x1
#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */
/**@}*/
/* ADCPRE: ADC prescaler */
/****************************************************************************/
/** @defgroup rcc_cfgr_adcpre RCC ADC Clock Prescaler enable values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
/**@}*/
/* PPRE2: APB high-speed prescaler (APB2) */
/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 Prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
/**@}*/
/* PPRE1: APB low-speed prescaler (APB1) */
/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 Prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
/**@}*/
/* HPRE: AHB prescaler */
/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB Prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
@ -163,6 +200,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
/**@}*/
/* SWS: System clock switch status */
#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0
@ -170,9 +208,14 @@ LGPL License Terms @ref lgpl_license
#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2
/* SW: System clock switch */
/** @defgroup rcc_cfgr_scs RCC_CFGR System Clock Selection
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0
#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1
#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2
/**@}*/
/* --- RCC_CIR values ------------------------------------------------------ */
@ -211,6 +254,10 @@ LGPL License Terms @ref lgpl_license
/* --- RCC_APB2RSTR values ------------------------------------------------- */
/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */
#define RCC_APB2RSTR_USART1RST (1 << 14)
#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */
@ -226,9 +273,14 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB2RSTR_IOPBRST (1 << 3)
#define RCC_APB2RSTR_IOPARST (1 << 2)
#define RCC_APB2RSTR_AFIORST (1 << 0)
/**@}*/
/* --- RCC_APB1RSTR values ------------------------------------------------- */
/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_APB1RSTR_DACRST (1 << 29)
#define RCC_APB1RSTR_PWRRST (1 << 28)
#define RCC_APB1RSTR_BKPRST (1 << 27)
@ -251,6 +303,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB1RSTR_TIM4RST (1 << 2)
#define RCC_APB1RSTR_TIM3RST (1 << 1)
#define RCC_APB1RSTR_TIM2RST (1 << 0)
/**@}*/
/* --- RCC_AHBENR values --------------------------------------------------- */
@ -269,7 +322,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_AHBENR_SRAMEN (1 << 2)
#define RCC_AHBENR_DMA2EN (1 << 1)
#define RCC_AHBENR_DMA1EN (1 << 0)
/*@}*/
/**@}*/
/* --- RCC_APB2ENR values -------------------------------------------------- */
@ -292,7 +345,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB2ENR_IOPBEN (1 << 3)
#define RCC_APB2ENR_IOPAEN (1 << 2)
#define RCC_APB2ENR_AFIOEN (1 << 0)
/*@}*/
/**@}*/
/* --- RCC_APB1ENR values -------------------------------------------------- */
@ -322,7 +375,7 @@ LGPL License Terms @ref lgpl_license
#define RCC_APB1ENR_TIM4EN (1 << 2)
#define RCC_APB1ENR_TIM3EN (1 << 1)
#define RCC_APB1ENR_TIM2EN (1 << 0)
/*@}*/
/**@}*/
/* --- RCC_BDCR values ----------------------------------------------------- */
@ -347,8 +400,13 @@ LGPL License Terms @ref lgpl_license
/* --- RCC_AHBRSTR values -------------------------------------------------- */
/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values
@ingroup STM32F1xx_rcc_defines
@{*/
#define RCC_AHBRSTR_ETHMACRST (1 << 14)
#define RCC_AHBRSTR_OTGFSRST (1 << 12)
/**@}*/
/* --- RCC_CFGR2 values ---------------------------------------------------- */
@ -447,10 +505,6 @@ void rcc_set_usbpre(u32 usbpre);
u32 rcc_get_system_clock_source(int i);
void rcc_clock_setup_in_hsi_out_64mhz(void);
void rcc_clock_setup_in_hsi_out_48mhz(void);
/**
* Maximum speed possible for F100 (Value Line) on HSI
*/
void rcc_clock_setup_in_hsi_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
@ -459,3 +513,5 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
void rcc_backupdomain_reset(void);
#endif
/**@}*/

28
include/libopencm3/stm32/iwdg.h
View File

@ -1,3 +1,17 @@
/** @defgroup STM32F_iwdg_defines IWDG Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F Independent Watchdog Timer</b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@ -17,6 +31,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_IWDG_H
#define LIBOPENCM3_IWDG_H
@ -42,9 +58,14 @@
/* Bits [31:16]: Reserved. */
/* KEY[15:0]: Key value (write-only, reads as 0x0000) */
/** @defgroup iwdg_key IWDG Key Values
@ingroup STM32F_iwdg_defines
@{*/
#define IWDG_KR_RESET 0xaaaa
#define IWDG_KR_UNLOCK 0x5555
#define IWDG_KR_START 0xcccc
/**@}*/
/* --- IWDG_PR values ------------------------------------------------------ */
@ -52,6 +73,10 @@
/* PR[2:0]: Prescaler divider */
#define IWDG_PR_LSB 0
/** @defgroup iwdg_prediv IWDG Prescaler divider
@ingroup STM32F_iwdg_defines
@{*/
#define IWDG_PR_DIV4 0x0
#define IWDG_PR_DIV8 0x1
#define IWDG_PR_DIV16 0x2
@ -59,6 +84,7 @@
#define IWDG_PR_DIV64 0x4
#define IWDG_PR_DIV128 0x5
#define IWDG_PR_DIV256 0x6
/**@}*/
/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
/* #define IWDG_PR_DIV256 0x7 */
@ -87,3 +113,5 @@ bool iwdg_prescaler_busy(void);
void iwdg_reset(void);
#endif
/**@}*/

56
include/libopencm3/stm32/pwr.h
View File

@ -1,3 +1,17 @@
/** @defgroup STM32F1xx_pwr_defines PWR Defines
@ingroup STM32F_defines
@brief <b>libopencm3 STM32F Power Control</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 17 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@ -17,6 +31,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_PWR_H
#define LIBOPENCM3_PWR_H
@ -40,14 +56,20 @@
/* PLS[7:5]: PVD level selection */
#define PWR_CR_PLS_LSB 5
#define PWR_CR_PLS_2V2 0x0
#define PWR_CR_PLS_2V3 0x1
#define PWR_CR_PLS_2V4 0x2
#define PWR_CR_PLS_2V5 0x3
#define PWR_CR_PLS_2V6 0x4
#define PWR_CR_PLS_2V7 0x5
#define PWR_CR_PLS_2V8 0x6
#define PWR_CR_PLS_2V9 0x7
/** @defgroup pwr_pls PVD level selection
@ingroup STM32F_pwr_defines
@{*/
#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
/**@}*/
#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
/* PVDE: Power voltage detector enable */
#define PWR_CR_PVDE (1 << 4)
@ -84,6 +106,22 @@
/* --- PWR function prototypes ------------------------------------------- */
/* TODO */
void pwr_disable_backup_domain_write_protect(void);
void pwr_enable_backup_domain_write_protect(void);
void pwr_enable_power_voltage_detect(u32 pvd_level);
void pwr_disable_power_voltage_detect(void);
void pwr_clear_standby_flag(void);
void pwr_clear_wakeup_flag(void);
void pwr_set_standby_mode(void);
void pwr_set_stop_mode(void);
void pwr_voltage_regulator_on_in_stop(void);
void pwr_voltage_regulator_low_power_in_stop(void);
void pwr_enable_wakeup_pin(void);
void pwr_disable_wakeup_pin(void);
bool pwr_voltage_high(void);
bool pwr_get_standby_flag(void);
bool pwr_get_wakeup_flag(void);
#endif
/**@}*/

25
include/libopencm3/stm32/systick.h
View File

@ -1,3 +1,18 @@
/** @defgroup STM32F_systick_defines SysTick Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F SysTick </b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 19 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@ -17,6 +32,8 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_SYSTICK_H
#define LIBOPENCM3_SYSTICK_H
@ -45,8 +62,14 @@
/* CLKSOURCE: Clock source selection */
#define STK_CTRL_CLKSOURCE (1 << 2)
#define STK_CTRL_CLKSOURCE_LSB 2
/** @defgroup systick_clksource Clock source selection
@ingroup STM32F_systick_defines
@{*/
#define STK_CTRL_CLKSOURCE_AHB_DIV8 0
#define STK_CTRL_CLKSOURCE_AHB 1
/**@}*/
/* TICKINT: SysTick exception request enable */
#define STK_CTRL_TICKINT (1 << 1)
/* ENABLE: Counter enable */
@ -80,3 +103,5 @@ void systick_counter_disable(void);
u8 systick_get_countflag(void);
#endif
/**@}*/

44
include/libopencm3/stm32/timer.h
View File

@ -1,8 +1,8 @@
/** @file
/** @defgroup STM32F_tim_defines Timers Defines
@ingroup STM32F1xx
@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx Timers</b>
@brief <b>libopencm3 STM32F1xx Timers</b>
@ingroup STM32F_defines
@version 1.0.0
@ -11,15 +11,6 @@
@date 18 May 2012
LGPL License Terms @ref lgpl_license
*/
/** @defgroup STM32F1xx_tim_defines
@brief Defined Constants and Types for the STM32F1xx Timers
@ingroup STM32F1xx_defines
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
@ -40,6 +31,8 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#ifndef LIBOPENCM3_TIMER_H
#define LIBOPENCM3_TIMER_H
@ -62,7 +55,7 @@ LGPL License Terms @ref lgpl_license
#define TIM6 TIM6_BASE
#define TIM7 TIM7_BASE
#define TIM8 TIM8_BASE
/*@}*/
/**@}*/
/* --- Timer registers ----------------------------------------------------- */
@ -266,7 +259,7 @@ LGPL License Terms @ref lgpl_license
#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8)
#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8)
#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8)
/*@}*/
/**@}*/
/* ARPE: Auto-reload preload enable */
#define TIM_CR1_ARPE (1 << 7)
@ -282,7 +275,7 @@ LGPL License Terms @ref lgpl_license
#define TIM_CR1_CMS_CENTER_2 (0x2 << 5)
#define TIM_CR1_CMS_CENTER_3 (0x3 << 5)
#define TIM_CR1_CMS_MASK (0x3 << 5)
/*@}*/
/**@}*/
/* DIR: Direction */
/****************************************************************************/
@ -292,7 +285,7 @@ LGPL License Terms @ref lgpl_license
@{*/
#define TIM_CR1_DIR_UP (0 << 4)
#define TIM_CR1_DIR_DOWN (1 << 4)
/*@}*/
/**@}*/
/* OPM: One pulse mode */
#define TIM_CR1_OPM (1 << 3)
@ -334,7 +327,7 @@ LGPL License Terms @ref lgpl_license
/* OIS1:*//** Output idle state 1 (OC1 output) */
#define TIM_CR2_OIS1 (1 << 8)
#define TIM_CR2_OIS_MASK (0x7f << 8)
/*@}*/
/**@}*/
/* TI1S: TI1 selection */
#define TIM_CR2_TI1S (1 << 7)
@ -354,7 +347,7 @@ LGPL License Terms @ref lgpl_license
#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4)
#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4)
#define TIM_CR2_MMS_MASK (0x7 << 4)
/*@}*/
/**@}*/
/* CCDS: Capture/compare DMA selection */
#define TIM_CR2_CCDS (1 << 3)
@ -424,7 +417,7 @@ LGPL License Terms @ref lgpl_license
/** External Trigger input (ETRF) */
#define TIM_SMCR_TS_ETRF (0x7 << 4)
#define TIM_SMCR_TS_MASK (0x7 << 4)
/*@}*/
/**@}*/
/* SMS[2:0]: Slave mode selection */
/** @defgroup tim_sms SMS Slave mode selection
@ -452,7 +445,7 @@ and generates an update of the registers. */
/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. */
#define TIM_SMCR_SMS_ECM1 (0x7 << 0)
#define TIM_SMCR_SMS_MASK (0x7 << 0)
/*@}*/
/**@}*/
/* --- TIMx_DIER values ---------------------------------------------------- */
@ -505,7 +498,7 @@ and generates an update of the registers. */
/* UIE:*//** Update interrupt enable */
#define TIM_DIER_UIE (1 << 0)
/*@}*/
/**@}*/
/* --- TIMx_SR values ------------------------------------------------------ */
/****************************************************************************/
@ -549,7 +542,7 @@ and generates an update of the registers. */
/* UIF:*//** Update interrupt flag */
#define TIM_SR_UIF (1 << 0)
/*@}*/
/**@}*/
/* --- TIMx_EGR values ----------------------------------------------------- */
@ -582,7 +575,7 @@ and generates an update of the registers. */
/* UG:*//** Update generation */
#define TIM_EGR_UG (1 << 0)
/*@}*/
/**@}*/
/* --- TIMx_CCMR1 values --------------------------------------------------- */
@ -923,7 +916,7 @@ and generates an update of the registers. */
#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8)
#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8)
#define TIM_BDTR_LOCK_MASK (0x3 << 8)
/*@}*/
/**@}*/
/* DTG[7:0]: Dead-time generator set-up */
#define TIM_BDTR_DTG_MASK 0x00FF
@ -1107,6 +1100,7 @@ void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc);
void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol);
void timer_slave_set_mode(u32 timer, u8 mode);
void timer_slave_set_trigger(u32 timer, u8 trigger);
void timer_force_event(u32 timer, u8 event);
#endif
/**@}*/

47
lib/stm32/dac.c
View File

@ -1,6 +1,6 @@
/** @file
/** @defgroup STM32F-dac-file DAC
@ingroup STM32F
@ingroup STM32F-files
@brief <b>libopencm3 STM32Fxx Digital to Analog Converter</b>
@ -8,7 +8,7 @@
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies
@date 30 June 2012
@date 18 August 2012
This library supports the Digital to Analog Conversion System in the
STM32F series of ARM Cortex Microcontrollers by ST Microelectronics.
@ -121,6 +121,8 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/dac.h>
#define MASK8 0xFF
@ -133,7 +135,7 @@ Enable a digital to analog converter channel. After setting this enable, the DAC
requires a t<sub>wakeup</sub> time typically around 10 microseconds before it
actually wakes up.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_channel enum ::data_channel.
*/
void dac_enable(data_channel dac_channel)
@ -156,7 +158,7 @@ void dac_enable(data_channel dac_channel)
Disable a digital to analog converter channel.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_channel enum ::data_channel.
*/
void dac_disable(data_channel dac_channel)
@ -182,7 +184,7 @@ amplifying buffer that provides additional drive for the output signal. The
buffer is enabled by default after a reset and needs to be explicitly disabled
if required.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_channel enum ::data_channel.
*/
void dac_buffer_enable(data_channel dac_channel)
@ -206,7 +208,7 @@ Disable a digital to analog converter channel output drive buffer. Disabling thi
reduce power consumption slightly and will increase the output impedance of the DAC.
The buffers are enabled by default after a reset.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_channel enum ::data_channel.
*/
void dac_buffer_disable(data_channel dac_channel)
@ -230,7 +232,7 @@ Enable a digital to analog converter channel DMA mode (connected to DMA2 channel
3 for DAC channel 1 and DMA2 channel 4 for DAC channel 2). A DMA request is
generated following an external trigger.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_channel enum ::data_channel.
*/
void dac_dma_enable(data_channel dac_channel)
@ -253,7 +255,7 @@ void dac_dma_enable(data_channel dac_channel)
Disable a digital to analog converter channel DMA mode.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_channel enum ::data_channel.
*/
void dac_dma_disable(data_channel dac_channel)
@ -279,7 +281,7 @@ external trigger to initiate register transfers from the buffer register to the
output register, followed by a DMA transfer to the buffer register if DMA is enabled.
The trigger source must also be selected.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_channel enum ::data_channel.
*/
void dac_trigger_enable(data_channel dac_channel)
@ -302,7 +304,7 @@ void dac_trigger_enable(data_channel dac_channel)
Disable a digital to analog converter channel external trigger.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_channel enum ::data_channel.
*/
void dac_trigger_disable(data_channel dac_channel)
@ -326,7 +328,7 @@ void dac_trigger_disable(data_channel dac_channel)
Sets the digital to analog converter trigger source, which can be taken from various
timers, an external trigger or a software trigger.
@param[in] u32 dac_trig_src. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or
@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or
a logical OR of one of each of these to set both channels simultaneously.
*/
@ -344,7 +346,7 @@ in the DAC output registers.
@note The DAC trigger must be enabled for this to work.
@param[in] u32 dac_trig_src. Taken from @ref dac_wave1_en or @ref dac_wave2_en or
@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en or
a logical OR of one of each of these to set both channels simultaneously.
*/
@ -358,7 +360,7 @@ void dac_set_waveform_generation(u32 dac_wave_ens)
Disable a digital to analog converter channel superimposed waveform generation.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_channel enum ::data_channel.
*/
void dac_disable_waveform_generation(data_channel dac_channel)
@ -390,7 +392,7 @@ signal output.
@note This must be called before enabling the DAC as the settings will then become read-only.
@note The DAC trigger must be enabled for this to work.
@param[in] u32 dac_mamp. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR
@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR
of one of each of these to set both channels simultaneously.
*/
@ -414,9 +416,9 @@ formatted according to the datasheets:
@li right-aligned 12 bit data in bits 0-11 for channel 1 and 16-27 for channel 2
@li left aligned 12 bit data in bits 4-15 for channel 1 and 20-31 for channel 2
@param[in] u32 dac_data with appropriate alignment.
@param[in] enum ::data_align, dac_data_format. Alignment and size.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_data u32 with appropriate alignment.
@param[in] dac_data_format enum ::data_align. Alignment and size.
@param[in] dac_channel enum ::data_channel.
*/
void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel)
@ -471,9 +473,9 @@ Loads the appropriate digital to analog converter dual data register with 12 or
simultaneous or independent analog output. The data in both channels are aligned
identically.
@param[in] u32 dac_data for channel 1 with appropriate alignment.
@param[in] u32 dac_data for channel 2 with appropriate alignment.
@param[in] enum ::data_align, dac_data_format. Right or left aligned, and 8 or 12 bit.
@param[in] dac_data1 u32 for channel 1 with appropriate alignment.
@param[in] dac_data2 u32 for channel 2 with appropriate alignment.
@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or 12 bit.
*/
void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format)
@ -497,7 +499,7 @@ void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data
If the trigger source is set to be a software trigger, cause a trigger to occur.
The trigger is cleared by hardware after conversion.
@param[in] enum ::data_channel, dac_channel.
@param[in] dac_channel enum ::data_channel.
*/
void dac_software_trigger(data_channel dac_channel)
@ -514,4 +516,5 @@ void dac_software_trigger(data_channel dac_channel)
break;
}
}
/**@}*/

229
lib/stm32/f1/dma.c
View File

@ -1,3 +1,24 @@
/** @defgroup STM32F1xx-dma-file DMA
@ingroup STM32F1xx
@brief <b>libopencm3 STM32F1xx DMA Controller</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 18 August 2012
This library supports the DMA
Control System in the STM32F1xx series of ARM Cortex Microcontrollers
by ST Microelectronics. It can provide for two DMA controllers,
one with 7 channels and one with 5. Channels are hardware dedicated
and each is shared with a number of different sources (only one can be
used at a time, under the responsibility of the programmer).
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@ -17,8 +38,19 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/f1/dma.h>
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Reset
The channel is disabled and configuration registers are cleared.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_channel_reset(u32 dma, u8 channel)
{
/* Disable channel. */
@ -35,18 +67,51 @@ void dma_channel_reset(u32 dma, u8 channel)
DMA_IFCR(dma) |= DMA_IFCR_CIF(channel);
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Memory to Memory Transfers
Memory to memory transfers do not require a trigger to activate each transfer.
Transfers begin immediately the channel has been enabled, and proceed without
intervention.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_mem2mem_mode(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM;
DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Set Priority
Channel Priority has four levels: low to very high. This has precedence over the
hardware priority.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@param[in] prio unsigned int32. Priority level @ref dma_ch_pri.
*/
void dma_set_priority(u32 dma, u8 channel, u32 prio)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK);
DMA_CCR(dma, channel) |= prio;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Set Memory Word Width
Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
alignment information if the source and destination widths do not match.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@param[in] mem_size unsigned int32. Memory word width @ref dma_ch_memwidth.
*/
void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
{
@ -54,89 +119,249 @@ void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
DMA_CCR(dma, channel) |= mem_size;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Set Peripheral Word Width
Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
alignment information if the source and destination widths do not match, or
if the peripheral does not support byte or half-word writes.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_ch_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
DMA_CCR(dma, channel) |= peripheral_size;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Memory Increment after Transfer
Following each transfer the current memory address is incremented by
1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The
value held by the base memory address register is unchanged.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_memory_increment_mode(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_MINC;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Memory Increment after Transfer
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_PINC;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Memory Circular Mode
After the number of bytes/words to be transferred has been completed, the
original transfer block size, memory and peripheral base addresses are
reloaded and the process repeats.
@note This cannot be used with memory to memory mode, which is explictly
disabled here.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_circular_mode(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_CIRC;
DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Transfers from a Peripheral
The data direction is set to read from a peripheral.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_set_read_from_peripheral(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Transfers from Memory
The data direction is set to read from memory.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_set_read_from_memory(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_DIR;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Interrupt on Transfer Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Interrupt on Transfer Error
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Interrupt on Transfer Half Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Interrupt on Transfer Half Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Enable Interrupt on Transfer Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Disable Interrupt on Transfer Complete
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Enable
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_channel(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_EN;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Disable
@note The DMA channel registers retain their values when the channel is disabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_channel(u32 dma, u8 channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Set the Peripheral Address
Set the address of the peripheral register to or from which data is to be transferred.
Refer to the documentation for the specific peripheral.
@note The DMA channel must be disabled before setting this address. This function
has no effect if the channel is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@param[in] address unsigned int32. Peripheral Address.
*/
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
{
DMA_CPAR(dma, channel) = (u32) address;
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
DMA_CPAR(dma, channel) = (u32) address;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Set the Base Memory Address
@note The DMA channel must be disabled before setting this address. This function
has no effect if the channel is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@param[in] address unsigned int32. Memory Initial Address.
*/
void dma_set_memory_address(u32 dma, u8 channel, u32 address)
{
DMA_CMAR(dma, channel) = (u32) address;
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN))
DMA_CMAR(dma, channel) = (u32) address;
}
/*-----------------------------------------------------------------------------*/
/** @brief DMA Channel Set the Transfer Block Size
@note The DMA channel must be disabled before setting this count value. The count
is not changed if the channel is enabled.
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
@param[in] number unsigned int16. Number of data words to transfer (65535 maximum).
*/
void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
{
DMA_CNDTR(dma, channel) = number;
}
/**@}*/

229
lib/stm32/f1/gpio.c
View File

@ -1,3 +1,61 @@
/** @defgroup STM32F1xx_gpio_file GPIO
@ingroup STM32F1xx
@brief <b>libopencm3 STM32F1xx General Purpose I/O</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 18 August 2012
This library supports the General Purpose I/O System in the STM32F1xx series
of ARM Cortex Microcontrollers by ST Microelectronics.
Each I/O port has 16 individually configurable bits. Many I/O pins share GPIO
functionality with a number of alternate functions and must be configured to the
alternate function mode if these are to be accessed. A feature is available to
remap alternative functions to a limited set of alternative pins in the event
of a clash of requirements.
The data registers associated with each port for input and output are 32 bit with
the upper 16 bits unused. The output buffer must be written as a 32 bit word, but
individual bits may be set or reset separately in atomic operations to avoid race
conditions during interrupts. Bits may also be individually locked to prevent
accidental configuration changes. Once locked the configuration cannot be changed
until after the next reset.
Each port bit can be configured as analog or digital input, the latter can be
floating or pulled up or down. As outputs they can be configured as either
push-pull or open drain, digital I/O or alternate function, and with maximum
output speeds of 2MHz, 10MHz, or 50MHz.
On reset all ports are configured as digital floating input.
@section gpio_api_ex Basic GPIO Handling API.
Example 1: Push-pull digital output actions on ports C2 and C9
@code
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO2 | GPIO9);
gpio_set(GPIOC, GPIO2 | GPIO9);
gpio_clear(GPIOC, GPIO2);
gpio_toggle(GPIOC, GPIO2 | GPIO9);
gpio_port_write(GPIOC, 0x204);
@endcode
Example 1: Digital input on port C12
@code
gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT, GPIO12);
reg16 = gpio_port_read(GPIOC);
@endcode
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@ -33,9 +91,23 @@
* TODO:
* - GPIO remapping support
*/
/**@{*/
#include <libopencm3/stm32/f1/gpio.h>
/*-----------------------------------------------------------------------------*/
/** @brief Set GPIO Pin Mode
Sets the mode (input/output) and configuration (analog/digitial and
open drain/push pull), for a set of GPIO pins on a given GPIO port.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] mode Unsigned int8. Pin mode @ref gpio_mode
@param[in] cnf Unsigned int8. Pin configuration @ref gpio_cnf
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be set, use logical OR '|' to separate them.
*/
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
{
u16 i, offset = 0;
@ -73,69 +145,99 @@ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
GPIO_CRH(gpioport) = crh;
}
/**
* Set one or more pins of the given GPIO port to 1.
*
* @param gpioport The GPIO port to use (GPIOA - GPIOG).
* @param gpios The GPIO pin(s) to set to 1 (GPIO0 - GPIO15, or GPIO_ALL).
* If multiple pins shall be set, use '|' to separate them.
*/
/*-----------------------------------------------------------------------------*/
/** @brief Set a Group of Pins Atomic
Set one or more pins of the given GPIO port to 1 in an atomic operation.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be changed, use logical OR '|' to separate them.
*/
void gpio_set(u32 gpioport, u16 gpios)
{
GPIO_BSRR(gpioport) = gpios;
}
/**
* Clear one or more pins of the given GPIO port to 0.
*
* @param gpioport The GPIO port to use (GPIOA - GPIOG).
* @param gpios The GPIO pin(s) to set to 0 (GPIO0 - GPIO15, or GPIO_ALL).
* If multiple pins shall be cleared, use '|' to separate them.
*/
/*-----------------------------------------------------------------------------*/
/** @brief Clear a Group of Pins Atomic
Clear one or more pins of the given GPIO port to 0 in an atomic operation.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be changed, use logical OR '|' to separate them.
*/
void gpio_clear(u32 gpioport, u16 gpios)
{
GPIO_BRR(gpioport) = gpios;
}
/*-----------------------------------------------------------------------------*/
/** @brief Read a Group of Pins.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be read, use logical OR '|' to separate them.
@return Unsigned int16 value of the pin values. The bit position of the pin value
returned corresponds to the pin number.
*/
u16 gpio_get(u32 gpioport, u16 gpios)
{
return gpio_port_read(gpioport) & gpios;
}
/**
* Toggle one or more pins of the given GPIO port.
*
* @param gpioport The GPIO port to use (GPIOA - GPIOG).
* @param gpios The GPIO pin(s) to toggle (GPIO0 - GPIO15, or GPIO_ALL).
* If multiple pins shall be toggled, use '|' to separate them.
*/
/*-----------------------------------------------------------------------------*/
/** @brief Toggle a Group of Pins
Toggle one or more pins of the given GPIO port. This is not an atomic operation.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be changed, use logical OR '|' to separate them.
*/
void gpio_toggle(u32 gpioport, u16 gpios)
{
GPIO_ODR(gpioport) ^= gpios;
}
/**
* Read the current value of the given GPIO port.
*
* @param gpioport The GPIO port to read (GPIOA - GPIOG).
* @return The value of the current GPIO port.
*/
/*-----------------------------------------------------------------------------*/
/** @brief Read from a Port
Read the current value of the given GPIO port. Only the lower 16 bits contain
valid pin data.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@return Unsigned int16. The value held in the specified GPIO port.
*/
u16 gpio_port_read(u32 gpioport)
{
return (u16)GPIO_IDR(gpioport);
}
/**
* Write to the given GPIO port.
*
* @param gpioport The GPIO port to write to (GPIOA - GPIOG).
* @param data The data to write to the specified GPIO port.
*/
/*-----------------------------------------------------------------------------*/
/** @brief Write to a Port
Write a value to the given GPIO port.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] data Unsigned int16. The value to be written to the GPIO port.
*/
void gpio_port_write(u32 gpioport, u16 data)
{
GPIO_ODR(gpioport) = data;
}
/*-----------------------------------------------------------------------------*/
/** @brief Lock the Configuration of a Group of Pins
The configuration of one or more pins of the given GPIO port is locked. There is
no mechanism to unlock these via software. Unlocking occurs at the next reset.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id
If multiple pins are to be locked, use logical OR '|' to separate them.
*/
void gpio_port_config_lock(u32 gpioport, u16 gpios)
{
u32 reg32;
@ -152,3 +254,64 @@ void gpio_port_config_lock(u32 gpioport, u16 gpios)
/* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
}
/*-----------------------------------------------------------------------------*/
/** @brief Map the EVENTOUT signal
Enable the EVENTOUT signal and select the port and pin to be used.
@param[in] evoutport Unsigned int8. Port for EVENTOUT signal @ref afio_evcr_port
@param[in] evoutpin Unsigned int8. Pin for EVENTOUT signal @ref afio_evcr_pin
*/
void gpio_set_eventout(u8 evoutport, u8 evoutpin)
{
AFIO_EVCR = AFIO_EVCR_EVOE | evoutport | evoutpin;
}
/*-----------------------------------------------------------------------------*/
/** @brief Map Alternate Function Port Bits (Main Set)
A number of alternate function ports can be remapped to defined alternative
port bits to avoid clashes in cases where multiple alternate functions are present.
Refer to the datasheets for the particular mapping desired. This provides the main
set of remap functionality. See @ref gpio_secondary_remap for a number of lesser used
remaps.
The AFIO remapping feature is used only with the STM32F10x series.
@note The Serial Wire JTAG disable controls allow certain GPIO ports to become available
in place of some of the SWJ signals. Full SWJ capability is obtained by setting this to
zero. The value of this must be specified for every call to this function as its current
value cannot be ascertained from the hardware.
@param[in] swjdisable Unsigned int8. Disable parts of the SWJ capability @ref afio_swj_disable.
@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref afio_remap,
@ref afio_remap_can1, @ref afio_remap_tim3, @ref afio_remap_tim2, @ref afio_remap_tim1,
@ref afio_remap_usart3. For connectivity line devices only @ref afio_remap_cld are
also available.
*/
void gpio_primary_remap(u8 swjdisable, u32 maps)
{
AFIO_MAPR = swjdisable | (maps & 0x1FFFFF);
}
/*-----------------------------------------------------------------------------*/
/** @brief Map Alternate Function Port Bits (Secondary Set)
A number of alternate function ports can be remapped to defined alternative
port bits to avoid clashes in cases where multiple alternate functions are present.
Refer to the datasheets for the particular mapping desired. This provides the second
smaller and less used set of remap functionality. See @ref gpio_primary_remap for
the main set of remaps.
The AFIO remapping feature is used only with the STM32F10x series.
@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref afio_remap2
*/
void gpio_secondary_remap(u32 maps)
{
AFIO_MAPR2 = maps;
}
/**@}*/

217
lib/stm32/f1/pwr.c Normal file
View File

@ -0,0 +1,217 @@
/** @defgroup STM32F1xx-pwr-file PWR
@ingroup STM32F1xx
@brief <b>libopencm3 STM32F1xx Power Control</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 18 August 2012
This library supports the power control system for the
STM32F1 series of ARM Cortex Microcontrollers by ST Microelectronics.
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/pwr.h>
/*---------------------------------------------------------------------------*/
/** @brief Disable Backup Domain Write Protection.
This allows backup domain registers to be changed. These registers are write
protected after a reset.
*/
void pwr_disable_backup_domain_write_protect(void)
{
PWR_CR |= PWR_CR_DBP;
}
/*---------------------------------------------------------------------------*/
/** @brief Re-enable Backup Domain Write Protection.
This protects backup domain registers from inadvertent change.
*/
void pwr_enable_backup_domain_write_protect(void)
{
PWR_CR &= ~PWR_CR_DBP;
}
/*---------------------------------------------------------------------------*/
/** @brief Enable Power Voltage Detector.
This provides voltage level threshold detection. The result of detection is
provided in the power voltage detector output flag (see @ref pwr_voltage_high)
or by setting the EXTI16 interrupt (see datasheet for configuration details).
@param[in] pvd_level u32. Taken from @ref pwr_pls.
*/
void pwr_enable_power_voltage_detect(u32 pvd_level)
{
PWR_CR &= ~PWR_CR_PLS_MASK;
PWR_CR |= (PWR_CR_PVDE | pvd_level);
}
/*---------------------------------------------------------------------------*/
/** @brief Disable Power Voltage Detector.
*/
void pwr_disable_power_voltage_detect(void)
{
PWR_CR &= ~PWR_CR_PVDE;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the Standby Flag.
This is set when the processor returns from a standby mode.
*/
void pwr_clear_standby_flag(void)
{
PWR_CR |= PWR_CR_CSBF;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear the Wakeup Flag.
This is set when the processor receives a wakeup signal.
*/
void pwr_clear_wakeup_flag(void)
{
PWR_CR |= PWR_CR_CWUF;
}
/*---------------------------------------------------------------------------*/
/** @brief Set Standby Mode in Deep Sleep.
*/
void pwr_set_standby_mode(void)
{
PWR_CR |= PWR_CR_PDDS;
}
/*---------------------------------------------------------------------------*/
/** @brief Set Stop Mode in Deep Sleep.
*/
void pwr_set_stop_mode(void)
{
PWR_CR &= ~PWR_CR_PDDS;
}
/*---------------------------------------------------------------------------*/
/** @brief Voltage Regulator On in Stop Mode.
*/
void pwr_voltage_regulator_on_in_stop(void)
{
PWR_CR &= ~PWR_CR_LPDS;
}
/*---------------------------------------------------------------------------*/
/** @brief Voltage Regulator Low Power in Stop Mode.
*/
void pwr_voltage_regulator_low_power_in_stop(void)
{
PWR_CR |= PWR_CR_LPDS;
}
/*---------------------------------------------------------------------------*/
/** @brief Enable Wakeup Pin.
The wakeup pin is used for waking the processor from standby mode.
*/
void pwr_enable_wakeup_pin(void)
{
PWR_CSR |= PWR_CR_EWUP;
}
/*---------------------------------------------------------------------------*/
/** @brief Release Wakeup Pin.
The wakeup pin is used for general purpose I/O.
*/
void pwr_disable_wakeup_pin(void)
{
PWR_CSR &= ~PWR_CR_EWUP;
}
/*---------------------------------------------------------------------------*/
/** @brief Get Voltage Detector Output.
The voltage detector threshold must be set when the power voltage detector is
enabled, see @ref pwr_enable_power_voltage_detect.
@returns boolean: TRUE if the power voltage is above the preset voltage
threshold.
*/
bool pwr_voltage_high(void)
{
return (PWR_CSR & PWR_CR_PVDO);
}
/*---------------------------------------------------------------------------*/
/** @brief Get Standby Flag.
The standby flag is set when the processor returns from a standby state. It is
cleared by software (see @ref pwr_clear_standby_flag).
@returns boolean: TRUE if the processor was in standby state.
*/
bool pwr_get_standby_flag(void)
{
return (PWR_CSR & PWR_CR_SBF);
}
/*---------------------------------------------------------------------------*/
/** @brief Get Wakeup Flag.
The wakeup flag is set when a wakeup event has been received. It is
cleared by software (see @ref pwr_clear_wakeup_flag).
@returns boolean: TRUE if a wakeup event was received.
*/
bool pwr_get_wakeup_flag(void)
{
return (PWR_CSR & PWR_CR_WUF);
}
/**@}*/

315
lib/stm32/f1/rcc.c
View File

@ -1,4 +1,4 @@
/** @file
/** @defgroup STM32F1xx-rcc-file RCC
@ingroup STM32F1xx
@ -10,25 +10,26 @@
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 18 May 2012
@date 18 August 2012
This library supports the Reset and Clock
Control System in the STM32F1xx series of ARM Cortex Microcontrollers
by ST Microelectronics.
This library supports the Reset and Clock Control System in the STM32F1xx
series of ARM Cortex Microcontrollers by ST Microelectronics.
@note Full support for connection line devices is not yet provided.
Clock settings and resets for many peripherals are given here rather than in the
peripheral library.
corresponding peripheral library.
The library also provides a number of common configurations for the processor
system clock. Not all possible configurations are given here.
@bugs None known
system clock. Not all possible configurations are included.
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
*
* This library is free software: you can redistribute it and/or modify
@ -45,6 +46,7 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/f1/rcc.h>
#include <libopencm3/stm32/f1/flash.h>
@ -54,12 +56,12 @@ u32 rcc_ppre1_frequency = 8000000;
/** Default ppre2 peripheral clock frequency after reset. */
u32 rcc_ppre2_frequency = 8000000;
//-----------------------------------------------------------------------------
/** @brief RCC Clear the Oscillator Ready Interrupt
/*-----------------------------------------------------------------------------*/
/** @brief RCC Clear the Oscillator Ready Interrupt Flag
Clear the interrupt flag that was set when a clock oscillator became ready to use.
@param[in] enum ::osc_t. Oscillator ID
@param[in] osc enum ::osc_t. Oscillator ID
*/
void rcc_osc_ready_int_clear(osc_t osc)
@ -83,6 +85,12 @@ void rcc_osc_ready_int_clear(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Enable the Oscillator Ready Interrupt
@param[in] osc enum ::osc_t. Oscillator ID
*/
void rcc_osc_ready_int_enable(osc_t osc)
{
switch (osc) {
@ -104,6 +112,12 @@ void rcc_osc_ready_int_enable(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Disable the Oscillator Ready Interrupt
@param[in] osc enum ::osc_t. Oscillator ID
*/
void rcc_osc_ready_int_disable(osc_t osc)
{
switch (osc) {
@ -125,6 +139,13 @@ void rcc_osc_ready_int_disable(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Read the Oscillator Ready Interrupt Flag
@param[in] osc enum ::osc_t. Oscillator ID
@returns int. Boolean value for flag set.
*/
int rcc_osc_ready_int_flag(osc_t osc)
{
switch (osc) {
@ -149,16 +170,33 @@ int rcc_osc_ready_int_flag(osc_t osc)
return -1;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Clear the Clock Security System Interrupt Flag
*/
void rcc_css_int_clear(void)
{
RCC_CIR |= RCC_CIR_CSSC;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Read the Clock Security System Interrupt Flag
@returns int. Boolean value for flag set.
*/
int rcc_css_int_flag(void)
{
return ((RCC_CIR & RCC_CIR_CSSF) != 0);
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Wait for Oscillator Ready.
@param[in] osc enum ::osc_t. Oscillator ID
*/
void rcc_wait_for_osc_ready(osc_t osc)
{
switch (osc) {
@ -180,6 +218,20 @@ void rcc_wait_for_osc_ready(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Turn on an Oscillator.
Enable an oscillator and power on. Each oscillator requires an amount of time to
settle to a usable state. Refer to datasheets for time delay information. A status
flag is available to indicate when the oscillator becomes ready (see
@ref rcc_osc_ready_int_flag and @ref rcc_wait_for_osc_ready).
@note The LSE clock is in the backup domain and cannot be enabled until the
backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect).
@param[in] osc enum ::osc_t. Oscillator ID
*/
void rcc_osc_on(osc_t osc)
{
switch (osc) {
@ -201,6 +253,20 @@ void rcc_osc_on(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Turn off an Oscillator.
Disable an oscillator and power off.
@note An oscillator cannot be turned off if it is selected as the system clock.
@note The LSE clock is in the backup domain and cannot be disabled until the
backup domain write protection has been removed (see
@ref pwr_disable_backup_domain_write_protect) or the backup domain has been
(see reset @ref rcc_backupdomain_reset).
@param[in] osc enum ::osc_t. Oscillator ID
*/
void rcc_osc_off(osc_t osc)
{
switch (osc) {
@ -222,16 +288,39 @@ void rcc_osc_off(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Enable the Clock Security System.
*/
void rcc_css_enable(void)
{
RCC_CR |= RCC_CR_CSSON;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Disable the Clock Security System.
*/
void rcc_css_disable(void)
{
RCC_CR &= ~RCC_CR_CSSON;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Enable Bypass.
Enable an external clock to bypass the internal clock (high speed and low speed
clocks only). The external clock must be enabled (see @ref rcc_osc_on)
and the internal clock must be disabled (see @ref rcc_osc_off) for this to have effect.
@note The LSE clock is in the backup domain and cannot be bypassed until the
backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect).
@param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
*/
void rcc_osc_bypass_enable(osc_t osc)
{
switch (osc) {
@ -249,6 +338,19 @@ void rcc_osc_bypass_enable(osc_t osc)
}
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Disable Bypass.
Re-enable the internal clock (high speed and low speed clocks only). The internal
clock must be disabled (see @ref rcc_osc_off) for this to have effect.
@note The LSE clock is in the backup domain and cannot have bypass removed until the
backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect)
or the backup domain has been reset (see @ref rcc_backupdomain_reset).
@param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
*/
void rcc_osc_bypass_disable(osc_t osc)
{
switch (osc) {
@ -266,18 +368,20 @@ void rcc_osc_bypass_disable(osc_t osc)
}
}
//-----------------------------------------------------------------------------
/** @brief RCC Enable a peripheral clock.
/*-----------------------------------------------------------------------------*/
/** @brief RCC Enable Peripheral Clocks.
Enable the clock on a particular peripheral. Several peripherals could be
enabled simultaneously if they are controlled by the same register.
Enable the clock on particular peripherals. There are three registers
involved, each one controlling the enabling of clocks associated with the AHB,
APB1 and APB2 respectively. Several peripherals could be
enabled simultaneously <em>only if they are controlled by the same register</em>.
@param[in] Unsigned int32 *reg. Pointer to a Clock Enable Register
(either RCC_AHBENR, RCC_APB1RENR or RCC_APB2RENR)
@param[in] Unsigned int32 en. OR of all enables to be set
@param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
@param[in] en Unsigned int32. Logical OR of all enables to be set
@li If register is RCC_AHBER, from @ref rcc_ahbenr_en
@li If register is RCC_APB1RENR, from @ref rcc_apb1enr_en
@li If register is RCC_APB2RENR, from @ref rcc_apb2enr_en
@li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
*/
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
@ -285,21 +389,75 @@ void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
*reg |= en;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Disable Peripheral Clocks.
Enable the clock on particular peripherals. There are three registers
involved, each one controlling the enabling of clocks associated with the AHB,
APB1 and APB2 respectively. Several peripherals could be
disabled simultaneously <em>only if they are controlled by the same register</em>.
@param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
@param[in] en Unsigned int32. Logical OR of all enables to be used for disabling.
@li If register is RCC_AHBER, from @ref rcc_ahbenr_en
@li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
*/
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
{
*reg &= ~en;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Reset Peripherals.
Reset particular peripherals. There are three registers
involved, each one controlling reset of peripherals associated with the AHB,
APB1 and APB2 respectively. Several peripherals could be reset simultaneously
<em>only if they are controlled by the same register</em>.
@param[in] *reg Unsigned int32. Pointer to a Reset Register
(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
@param[in] reset Unsigned int32. Logical OR of all resets.
@li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
@li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
@li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
*/
void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
{
*reg |= reset;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Remove Reset on Peripherals.
Remove the reset on particular peripherals. There are three registers
involved, each one controlling reset of peripherals associated with the AHB,
APB1 and APB2 respectively. Several peripherals could have the reset removed
simultaneously <em>only if they are controlled by the same register</em>.
@param[in] *reg Unsigned int32. Pointer to a Reset Register
(either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
@param[in] clear_reset Unsigned int32. Logical OR of all resets to be removed:
@li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
@li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
@li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
*/
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
{
*reg &= ~clear_reset;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set the Source for the System Clock.
@param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs
*/
void rcc_set_sysclk_source(u32 clk)
{
u32 reg32;
@ -309,6 +467,14 @@ void rcc_set_sysclk_source(u32 clk)
RCC_CFGR = (reg32 | clk);
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set the PLL Multiplication Factor.
@note This only has effect when the PLL is disabled.
@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
*/
void rcc_set_pll_multiplication_factor(u32 mul)
{
u32 reg32;
@ -318,6 +484,14 @@ void rcc_set_pll_multiplication_factor(u32 mul)
RCC_CFGR = (reg32 | (mul << 18));
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set the PLL Clock Source.
@note This only has effect when the PLL is disabled.
@param[in] pllsrc Unsigned int32. PLL clock source @ref rcc_cfgr_pcs
*/
void rcc_set_pll_source(u32 pllsrc)
{
u32 reg32;
@ -327,6 +501,14 @@ void rcc_set_pll_source(u32 pllsrc)
RCC_CFGR = (reg32 | (pllsrc << 16));
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set the HSE Frequency Divider used as PLL Clock Source.
@note This only has effect when the PLL is disabled.
@param[in] pllxtpre Unsigned int32. HSE division factor @ref rcc_cfgr_hsepre
*/
void rcc_set_pllxtpre(u32 pllxtpre)
{
u32 reg32;
@ -336,6 +518,14 @@ void rcc_set_pllxtpre(u32 pllxtpre)
RCC_CFGR = (reg32 | (pllxtpre << 17));
}
/*-----------------------------------------------------------------------------*/
/** @brief ADC Setup the A/D Clock
The ADC's have a common clock prescale setting.
@param[in] adcpre u32. Prescale divider taken from @ref rcc_cfgr_adcpre
*/
void rcc_set_adcpre(u32 adcpre)
{
u32 reg32;
@ -345,6 +535,12 @@ void rcc_set_adcpre(u32 adcpre)
RCC_CFGR = (reg32 | (adcpre << 14));
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set the APB2 Prescale Factor.
@param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre
*/
void rcc_set_ppre2(u32 ppre2)
{
u32 reg32;
@ -354,6 +550,14 @@ void rcc_set_ppre2(u32 ppre2)
RCC_CFGR = (reg32 | (ppre2 << 11));
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set the APB1 Prescale Factor.
@note The APB1 clock frequency must not exceed 36MHz.
@param[in] ppre1 Unsigned int32. APB1 prescale factor @ref rcc_cfgr_apb1pre
*/
void rcc_set_ppre1(u32 ppre1)
{
u32 reg32;
@ -363,6 +567,12 @@ void rcc_set_ppre1(u32 ppre1)
RCC_CFGR = (reg32 | (ppre1 << 8));
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set the AHB Prescale Factor.
@param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
*/
void rcc_set_hpre(u32 hpre)
{
u32 reg32;
@ -372,6 +582,17 @@ void rcc_set_hpre(u32 hpre)
RCC_CFGR = (reg32 | (hpre << 4));
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set the USB Prescale Factor.
The prescale factor can be set to 1 (no prescale) for use when the PLL clock is
48MHz, or 1.5 to generate the 48MHz USB clock from a 64MHz PLL clock.
@note This bit cannot be reset while the USB clock is enabled.
@param[in] usbpre Unsigned int32. USB prescale factor @ref rcc_cfgr_usbpre
*/
void rcc_set_usbpre(u32 usbpre)
{
u32 reg32;
@ -381,16 +602,31 @@ void rcc_set_usbpre(u32 usbpre)
RCC_CFGR = (reg32 | (usbpre << 22));
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Get the System Clock Source.
@returns Unsigned int32. System clock source:
@li 00 indicates HSE
@li 01 indicates LSE
@li 02 indicates PLL
*/
u32 rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return ((RCC_CFGR & 0x000c) >> 2);
}
/*-----------------------------------------------------------------------------*/
/*
* These functions are setting up the whole clock system for the most common
* input clock and output clock configurations.
*/
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 64MHz from HSI
*/
void rcc_clock_setup_in_hsi_out_64mhz(void)
{
/* Enable internal high-speed oscillator. */
@ -438,6 +674,11 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
rcc_ppre2_frequency = 64000000;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 48MHz from HSI
*/
void rcc_clock_setup_in_hsi_out_48mhz(void)
{
/* Enable internal high-speed oscillator. */
@ -486,6 +727,11 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
rcc_ppre2_frequency = 48000000;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 24MHz from HSI
*/
void rcc_clock_setup_in_hsi_out_24mhz(void) {
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
@ -532,6 +778,10 @@ void rcc_clock_setup_in_hsi_out_24mhz(void) {
rcc_ppre2_frequency = 24000000;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 8MHz
*/
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
{
@ -591,6 +841,11 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
rcc_ppre2_frequency = 24000000;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 72MHz from HSE at 8MHz
*/
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
{
/* Enable internal high-speed oscillator. */
@ -649,6 +904,11 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
rcc_ppre2_frequency = 72000000;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 12MHz
*/
void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
{
/* Enable internal high-speed oscillator. */
@ -707,6 +967,11 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
rcc_ppre2_frequency = 72000000;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Set System Clock PLL at 24MHz from HSE at 16MHz
*/
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
{
/* Enable internal high-speed oscillator. */
@ -765,6 +1030,12 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
rcc_ppre2_frequency = 72000000;
}
/*-----------------------------------------------------------------------------*/
/** @brief RCC Reset the backup domain
The backup domain register is reset to disable all controls.
*/
void rcc_backupdomain_reset(void)
{
/* Set the backup domain software reset. */
@ -773,3 +1044,5 @@ void rcc_backupdomain_reset(void)
/* Clear the backup domain software reset. */
RCC_BDCR &= ~RCC_BDCR_BDRST;
}
/**@}*/

132
lib/stm32/f1/timer.c
View File

@ -1,4 +1,4 @@
/** @file
/** @defgroup STM32F1xx-timer-file Timers
@ingroup STM32F1xx
@ -8,7 +8,7 @@
@author @htmlonly &copy; @endhtmlonly 2010 Edward Cheeseman <evbuilder@users.sourceforge.org>
@date 8 July 2012
@date 18 August 2012
This library supports the General Purpose and Advanced Control Timers for
the STM32F1xx series of ARM Cortex Microcontrollers by ST Microelectronics.
@ -93,6 +93,8 @@ push-pull outputs where the PWM output will appear.
* TIM_CR1_CMS_CENTRE_3, TIM_CR1_DIR_UP);
*/
/**@{*/
#include <libopencm3/stm32/timer.h>
#include <libopencm3/stm32/f1/rcc.h>
@ -561,8 +563,8 @@ void timer_set_dma_on_update_event(u32 timer_peripheral)
/** @brief Enable Timer Capture/Compare Control Update with Trigger.
If the capture/compare control bits CCxE, CCxNE and OCxM are set to be
preloaded, they are updated by software setting the COM bit (@ref ) or when a
rising edge occurs on the trigger input TRGI.
preloaded, they are updated by software generating the COMG event (@ref
timer_generate_event) or when a rising edge occurs on the trigger input TRGI.
@note This setting is only valid for the advanced timer channels with complementary
outputs.
@ -580,7 +582,8 @@ void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral)
/** @brief Disable Timer Capture/Compare Control Update with Trigger.
If the capture/compare control bits CCxE, CCxNE and OCxM are set to be
preloaded, they are updated by software setting the COM bit (@ref ).
preloaded, they are updated by software generating the COMG event (@ref
timer_generate_event).
@note This setting is only valid for the advanced timer channels with complementary
outputs.
@ -1391,7 +1394,7 @@ the Break and Deadtime Register.
@note This setting is only valid for the advanced timers.
@note It is necessary to call this function to enable the output on an advanced
timer <b>even if break or deadtime features are not being used<\b>.
timer <b>even if break or deadtime features are not being used</b>.
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8
*/
@ -1681,24 +1684,24 @@ Set the input filter parameters for an input channel, specifying:
@param[in] flt ::tim_ic_filter. Input Capture Filter identifier.
*/
void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt)
void timer_ic_set_filter(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_filter flt)
{
switch (ic) {
case TIM_IC1:
TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1F_MASK;
TIM_CCMR1(timer) |= flt << 4;
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC1F_MASK;
TIM_CCMR1(timer_peripheral) |= flt << 4;
break;
case TIM_IC2:
TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2F_MASK;
TIM_CCMR1(timer) |= flt << 12;
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC2F_MASK;
TIM_CCMR1(timer_peripheral) |= flt << 12;
break;
case TIM_IC3:
TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3F_MASK;
TIM_CCMR2(timer) |= flt << 4;
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC3F_MASK;
TIM_CCMR2(timer_peripheral) |= flt << 4;
break;
case TIM_IC4:
TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4F_MASK;
TIM_CCMR2(timer) |= flt << 12;
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC4F_MASK;
TIM_CCMR2(timer_peripheral) |= flt << 12;
break;
}
}
@ -1713,24 +1716,24 @@ Set the number of events between each capture.
@param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler.
*/
void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc)
void timer_ic_set_prescaler(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_psc psc)
{
switch (ic) {
case TIM_IC1:
TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1PSC_MASK;
TIM_CCMR1(timer) |= psc << 2;
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC1PSC_MASK;
TIM_CCMR1(timer_peripheral) |= psc << 2;
break;
case TIM_IC2:
TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2PSC_MASK;
TIM_CCMR1(timer) |= psc << 10;
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_IC2PSC_MASK;
TIM_CCMR1(timer_peripheral) |= psc << 10;
break;
case TIM_IC3:
TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3PSC_MASK;
TIM_CCMR2(timer) |= psc << 4;
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC3PSC_MASK;
TIM_CCMR2(timer_peripheral) |= psc << 4;
break;
case TIM_IC4:
TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4PSC_MASK;
TIM_CCMR2(timer) |= psc << 10;
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_IC4PSC_MASK;
TIM_CCMR2(timer_peripheral) |= psc << 10;
break;
}
}
@ -1756,7 +1759,7 @@ internal trigger input selected through TS bit
@param[in] in ::tim_ic_input. Input Capture channel direction and source input.
*/
void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in)
void timer_ic_set_input(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_input in)
{
in &= 3;
@ -1768,20 +1771,20 @@ void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in)
switch (ic) {
case TIM_IC1:
TIM_CCMR1(timer) &= ~TIM_CCMR1_CC1S_MASK;
TIM_CCMR1(timer) |= in;
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK;
TIM_CCMR1(timer_peripheral) |= in;
break;
case TIM_IC2:
TIM_CCMR1(timer) &= ~TIM_CCMR1_CC2S_MASK;
TIM_CCMR1(timer) |= in << 8;
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK;
TIM_CCMR1(timer_peripheral) |= in << 8;
break;
case TIM_IC3:
TIM_CCMR2(timer) &= ~TIM_CCMR2_CC3S_MASK;
TIM_CCMR2(timer) |= in;
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
TIM_CCMR2(timer_peripheral) |= in;
break;
case TIM_IC4:
TIM_CCMR2(timer) &= ~TIM_CCMR2_CC4S_MASK;
TIM_CCMR2(timer) |= in << 8;
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
TIM_CCMR2(timer_peripheral) |= in << 8;
break;
}
}
@ -1794,12 +1797,12 @@ void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in)
@param[in] pol ::tim_ic_pol. Input Capture polarity.
*/
void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol)
void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_pol pol)
{
if (pol)
TIM_CCER(timer) |= (0x2 << (ic * 4));
TIM_CCER(timer_peripheral) |= (0x2 << (ic * 4));
else
TIM_CCER(timer) &= ~(0x2 << (ic * 4));
TIM_CCER(timer_peripheral) &= ~(0x2 << (ic * 4));
}
/*---------------------------------------------------------------------------*/
@ -1809,9 +1812,9 @@ void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol)
@param[in] ic ::tim_ic_id. Input Capture channel designator.
*/
void timer_ic_enable(u32 timer, enum tim_ic_id ic)
void timer_ic_enable(u32 timer_peripheral, enum tim_ic_id ic)
{
TIM_CCER(timer) |= (0x1 << (ic * 4));
TIM_CCER(timer_peripheral) |= (0x1 << (ic * 4));
}
/*---------------------------------------------------------------------------*/
@ -1821,9 +1824,9 @@ void timer_ic_enable(u32 timer, enum tim_ic_id ic)
@param[in] ic ::tim_ic_id. Input Capture channel designator.
*/
void timer_ic_disable(u32 timer, enum tim_ic_id ic)
void timer_ic_disable(u32 timer_peripheral, enum tim_ic_id ic)
{
TIM_CCER(timer) &= ~(0x1 << (ic * 4));
TIM_CCER(timer_peripheral) &= ~(0x1 << (ic * 4));
}
/*---------------------------------------------------------------------------*/
@ -1838,10 +1841,10 @@ Set the input filter parameters for the external trigger, specifying:
@param[in] flt ::tim_ic_filter. Input Capture Filter identifier.
*/
void timer_slave_set_filter(u32 timer, enum tim_ic_filter flt)
void timer_slave_set_filter(u32 timer_peripheral, enum tim_ic_filter flt)
{
TIM_SMCR(timer) &= ~TIM_SMCR_ETF_MASK;
TIM_SMCR(timer) |= flt << 8;
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETF_MASK;
TIM_SMCR(timer_peripheral) |= flt << 8;
}
/*---------------------------------------------------------------------------*/
@ -1853,10 +1856,10 @@ Set the external trigger frequency division ratio.
@param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler.
*/
void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc)
void timer_slave_set_prescaler(u32 timer_peripheral, enum tim_ic_psc psc)
{
TIM_SMCR(timer) &= ~TIM_SMCR_ETPS_MASK;
TIM_SMCR(timer) |= psc << 12;
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETPS_MASK;
TIM_SMCR(timer_peripheral) |= psc << 12;
}
/*---------------------------------------------------------------------------*/
@ -1866,12 +1869,12 @@ void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc)
@param[in] pol ::tim_ic_pol. Input Capture polarity.
*/
void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol)
void timer_slave_set_polarity(u32 timer_peripheral, enum tim_ic_pol pol)
{
if (pol)
TIM_SMCR(timer) |= TIM_SMCR_ETP;
TIM_SMCR(timer_peripheral) |= TIM_SMCR_ETP;
else
TIM_SMCR(timer) &= ~TIM_SMCR_ETP;
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETP;
}
/*---------------------------------------------------------------------------*/
@ -1881,10 +1884,10 @@ void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol)
@param[in] mode Unsigned int8. Slave mode @ref tim_sms
*/
void timer_slave_set_mode(u32 timer, u8 mode)
void timer_slave_set_mode(u32 timer_peripheral, u8 mode)
{
TIM_SMCR(timer) &= ~TIM_SMCR_SMS_MASK;
TIM_SMCR(timer) |= mode;
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_SMS_MASK;
TIM_SMCR(timer_peripheral) |= mode;
}
/*---------------------------------------------------------------------------*/
@ -1894,28 +1897,13 @@ void timer_slave_set_mode(u32 timer, u8 mode)
@param[in] trigger Unsigned int8. Slave trigger source @ref tim_ts
*/
void timer_slave_set_trigger(u32 timer, u8 trigger)
void timer_slave_set_trigger(u32 timer_peripheral, u8 trigger)
{
TIM_SMCR(timer) &= ~TIM_SMCR_TS_MASK;
TIM_SMCR(timer) |= trigger;
}
/*---------------------------------------------------------------------------*/
/** @brief Force Timer Event
A number of events can be forced by software action. All events are cleared by
hardware on completion.
@param[in] timer_peripheral Unsigned int32. Timer register address base
@param[in] event Unsigned int8. Event identifier @ref tim_event_gen.
More than one event can be forced at the same time by logical OR of the event
identifiers.
*/
void timer_force_event(u32 timer, u8 event)
{
TIM_EGR(timer) = event;
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_TS_MASK;
TIM_SMCR(timer_peripheral) |= trigger;
}
/* TODO Timer DMA burst */
/**@}*/

18
lib/stm32/iwdg.c
View File

@ -1,6 +1,6 @@
/** @file
/** @defgroup STM32F-iwdg-file IWDG
@ingroup STM32F
@ingroup STM32F-files
@brief <b>libopencm3 STM32F1xx Independent Watchdog Timer</b>
@ -8,7 +8,7 @@
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
@date 11 June 2012
@date 18 August 2012
This library supports the Independent Watchdog Timer System in the STM32F1xx
series of ARM Cortex Microcontrollers by ST Microelectronics.
@ -22,8 +22,6 @@ Note that the User Configuration option byte provides a means of automatically
enabling the IWDG timer at power on (with counter value 0xFFF). If the
relevant bit is not set, the IWDG timer must be enabled by software.
@bugs None known
@note: Tested: CPU STM32F103RET6, Board ET-ARM Stamp STM32
LGPL License Terms @ref lgpl_license
@ -45,9 +43,13 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/iwdg.h>
#define LSI_FREQUENCY 32000
#define COUNT_LENGTH 12
#define COUNT_MASK ((1 << COUNT_LENGTH)-1)
/*-----------------------------------------------------------------------------*/
/** @brief IWDG Enable Watchdog Timer
@ -73,13 +75,10 @@ A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds)
can occasionally occur if the prescale or preload registers are currently busy
loading a previous value.
@param[in] u32 Period in milliseconds (< 32760) from a watchdog reset until
@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset until
a system reset is issued.
*/
#define COUNT_LENGTH 12
#define COUNT_MASK ((1 << COUNT_LENGTH)-1)
void iwdg_set_period_ms(u32 period)
{
u32 count, prescale, reload, exponent;
@ -141,4 +140,5 @@ void iwdg_reset(void)
{
IWDG_KR = IWDG_KR_RESET;
}
/**@}*/

75
lib/stm32/systick.c
View File

@ -1,3 +1,23 @@
/** @defgroup STM32F-systick-file SysTick
@ingroup STM32F-files
@brief <b>libopencm3 STM32Fxx System Tick Timer</b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 19 August 2012
This library supports the System Tick timer in the
STM32F series of ARM Cortex Microcontrollers by ST Microelectronics.
The System Tick timer is part of the ARM Cortex core. It is a 24 bit
down counter that can be configured with an automatical reload value.
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@ -17,44 +37,97 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/systick.h>
/*-----------------------------------------------------------------------------*/
/** @brief SysTick Set the Automatic Reload Value.
The counter is set to the reload value when the counter starts and after it
reaches zero.
@param[in] value u32. 24 bit reload value.
*/
void systick_set_reload(u32 value)
{
STK_LOAD = (value & 0x00FFFFFF);
}
/*-----------------------------------------------------------------------------*/
/** @brief SysTick Read the Automatic Reload Value.
@returns 24 bit reload value as u32.
*/
u32 systick_get_value(void)
{
return STK_VAL;
}
/*-----------------------------------------------------------------------------*/
/** @brief Set the SysTick Clock Source.
The clock source can be either the AHB clock or the same clock divided by 8.
@param[in] clocksource u8. Clock source from @ref systick_clksource.
*/
void systick_set_clocksource(u8 clocksource)
{
if (clocksource < 2)
STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB);
}
/*-----------------------------------------------------------------------------*/
/** @brief Enable SysTick Interrupt.
*/
void systick_interrupt_enable(void)
{
STK_CTRL |= STK_CTRL_TICKINT;
}
/*-----------------------------------------------------------------------------*/
/** @brief Disable SysTick Interrupt.
*/
void systick_interrupt_disable(void)
{
STK_CTRL &= ~STK_CTRL_TICKINT;
}
/*-----------------------------------------------------------------------------*/
/** @brief Enable SysTick Counter.
*/
void systick_counter_enable(void)
{
STK_CTRL |= STK_CTRL_ENABLE;
}
/*-----------------------------------------------------------------------------*/
/** @brief Disable SysTick Counter.
*/
void systick_counter_disable(void)
{
STK_CTRL &= ~STK_CTRL_ENABLE;
}
/*-----------------------------------------------------------------------------*/
/** @brief SysTick Read the Counter Flag.
The count flag is set when the timer count becomes zero, and is cleared when the
flag is read.
@returns Boolean if flag set.
*/
u8 systick_get_countflag(void)
{
if (STK_CTRL & STK_CTRL_COUNTFLAG)
@ -62,3 +135,5 @@ u8 systick_get_countflag(void)
else
return 0;
}
/**@}*/