Some more whitespace + cosmetics.
This commit is contained in:
Uwe Hermann
parent
b5727a6c73
commit
d9f6f200c1
@ -37,7 +37,6 @@
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/* Status register (IWDG_SR) */
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#define IWDG_SR MMIO32(IWDG_BASE + 0x0C)
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/* --- IWDG_KR values ------------------------------------------------------ */
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/* KEY[15:0]: Key value */
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@ -62,7 +62,6 @@
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/* STIR: Software Trigger Interrupt Register */
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#define NVIC_STIR MMIO32(STIR_BASE)
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/* --- IRQ channel numbers-------------------------------------------------- */
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/* Cortex M3 System Interrupts */
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@ -140,7 +139,6 @@
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#define NVIC_DMA2_CHANNEL3_IRQ 58
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#define NVIC_DMA2_CHANNEL4_5_IRQ 59
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/* --- NVIC functions ------------------------------------------------------ */
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void nvic_enable_irq(u8 irqn);
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@ -31,7 +31,6 @@
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/* Power control/status register (PWR_CSR) */
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#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
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/* --- PWR_CR values ------------------------------------------------------- */
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/* DBP: Disable backup domain write protection */
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@ -60,10 +59,9 @@
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/* PDDS: Power down deepsleep */
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#define PWR_CR_PDDS (1 << 1)
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/* LPDS: Low-power deepsleep */
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/* LPDS: Low-power deepsleep */
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#define PWR_CR_LPDS (1 << 0)
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/* --- PWR_CSR values ------------------------------------------------------ */
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/* EWUP: Enable WKUP pin */
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@ -116,7 +116,7 @@
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/* Bits [31:30]: reserved - must be kept cleared */
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/* TBLOFF[29:9]: Vector table base offset field */
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#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
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#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
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/* --- SCB_AIRCR values ---------------------------------------------------- */
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@ -174,24 +174,24 @@
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/* --- SCB_SHPR1 values ---------------------------------------------------- */
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/* Bits [31:24]: reserved - must be kept cleared */
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/* PRI_6[23:16]: Priority of system handler 6, usage fault */
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/* PRI_6[23:16]: Priority of system handler 6, usage fault */
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#define SCB_SHPR1_PRI_6_LSB 16
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/* PRI_5[15:8]: Priority of system handler 5, bus fault */
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/* PRI_5[15:8]: Priority of system handler 5, bus fault */
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#define SCB_SHPR1_PRI_5_LSB 8
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/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
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/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
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#define SCB_SHPR1_PRI_4_LSB 0
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/* --- SCB_SHPR2 values ---------------------------------------------------- */
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/* PRI_11[31:24]: Priority of system handler 11, SVCall */
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/* PRI_11[31:24]: Priority of system handler 11, SVCall */
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#define SCB_SHPR2_PRI_11_LSB 24
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/* Bits [23:0]: reserved - must be kept cleared */
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/* --- SCB_SHPR3 values ---------------------------------------------------- */
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/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
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/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
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#define SCB_SHPR3_PRI_15_LSB 24
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/* PRI_14[23:16]: Priority of system handler 14, PendSV */
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/* PRI_14[23:16]: Priority of system handler 14, PendSV */
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#define SCB_SHPR3_PRI_14_LSB 16
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/* Bits [15:0]: reserved - must be kept cleared */
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@ -249,7 +249,7 @@
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/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
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#define SCB_CFSR_BFARVALID (1 << 15)
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/* Bits [14:13]: reserved - must be kept cleared */
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/* STKERR: Bus fault on stacking for exception entry */
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/* STKERR: Bus fault on stacking for exception entry */
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#define SCB_CFSR_STKERR (1 << 12)
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/* UNSTKERR: Bus fault on unstacking for a return from exception */
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#define SCB_CFSR_UNSTKERR (1 << 11)
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@ -130,7 +130,7 @@
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#define SPI_CR1_SPE (1 << 6)
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/* BR[2:0]: Baud rate control */
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
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@ -138,7 +138,7 @@
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
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#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
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#define SPI_CR1_BR_FPCLK_DIV_2 0x0
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#define SPI_CR1_BR_FPCLK_DIV_2 0x0
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#define SPI_CR1_BR_FPCLK_DIV_4 0x1
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#define SPI_CR1_BR_FPCLK_DIV_8 0x2
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#define SPI_CR1_BR_FPCLK_DIV_16 0x3
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@ -407,7 +407,6 @@
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/* UIE: Update interrupt enable */
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#define TIM_DIER_UIE (1 << 0)
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/* --- TIMx_SR values ------------------------------------------------------ */
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/* CC4OF: Capture/compare 4 overcapture flag */
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@ -24,16 +24,11 @@
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#include <libopenstm32/common.h>
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#include <libopenstm32/tools.h>
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/******************************************************************************
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* USB base addresses
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******************************************************************************/
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/* --- USB base addresses -------------------------------------------------- */
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#define USB_PMA_BASE (0x40006000L) /* USB packet buffer memory base
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address */
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#define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */
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/******************************************************************************
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* USB general registers
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******************************************************************************/
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/* --- USB general registers ----------------------------------------------- */
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/* USB Control register */
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#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40))
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@ -48,31 +43,26 @@
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/* USB EP register */
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#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP))
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/******************************************************************************
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* USB control register masks / bits
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******************************************************************************/
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/* --- USB control register masks / bits ----------------------------------- */
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/* Interrupt mask bits, set to 1 to enable interrupt generation */
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#define USB_CNTR_CTRM (0x8000)
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#define USB_CNTR_PMAOVRM (0x4000)
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#define USB_CNTR_ERRM (0x2000)
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#define USB_CNTR_WKUPM (0x1000)
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#define USB_CNTR_SUSPM (0x0800)
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#define USB_CNTR_RESETM (0x0400)
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#define USB_CNTR_SOFM (0x0200)
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#define USB_CNTR_ESOFM (0x0100)
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#define USB_CNTR_CTRM 0x8000
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#define USB_CNTR_PMAOVRM 0x4000
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#define USB_CNTR_ERRM 0x2000
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#define USB_CNTR_WKUPM 0x1000
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#define USB_CNTR_SUSPM 0x0800
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#define USB_CNTR_RESETM 0x0400
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#define USB_CNTR_SOFM 0x0200
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#define USB_CNTR_ESOFM 0x0100
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/* Request/Force bits */
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#define USB_CNTR_RESUME 0x0010 /* Resume request */
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#define USB_CNTR_FSUSP 0x0008 /* Force suspend */
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#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */
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#define USB_CNTR_PWDN 0x0002 /* Power down */
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#define USB_CNTR_FRES 0x0001 /* Force reset */
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#define USB_CNTR_RESUME (0x0010) /* Resume request */
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#define USB_CNTR_FSUSP (0x0008) /* Force suspend */
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#define USB_CNTR_LP_MODE (0x0004) /* Low-power mode */
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#define USB_CNTR_PWDN (0x0002) /* Power down */
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#define USB_CNTR_FRES (0x0001) /* Force reset */
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/******************************************************************************
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* USB interrupt status register masks / bits
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******************************************************************************/
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/* --- USB interrupt status register masks / bits -------------------------- */
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#define USB_ISTR_CTR 0x8000 /* Correct Transfer */
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#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */
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@ -85,11 +75,9 @@
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#define USB_ISTR_DIR 0x0010 /* Direction of transaction */
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#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */
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/******************************************************************************
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* USB interrupt status register manipulators
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******************************************************************************/
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/* --- USB interrupt status register manipulators -------------------------- */
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//#define USB_CLR_ISTR_CTR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_CTR) /* CTR is read only! */
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/* Note: CTR is read only! */
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#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)
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#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)
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#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)
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@ -98,58 +86,50 @@
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#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
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#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
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/******************************************************************************
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* USB device addres register masks / bits
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******************************************************************************/
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/* --- USB device addres register masks / bits ----------------------------- */
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#define USB_DADDR_ENABLE 0x0080
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#define USB_DADDR_ADDR 0x007F
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/******************************************************************************
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* USB device addres register manipulators
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******************************************************************************/
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/* --- USB device addres register manipulators ----------------------------- */
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/******************************************************************************
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* USB endpoint register offsets
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******************************************************************************/
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/* --- USB endpoint register offsets --------------------------------------- */
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#define USB_EP0 ((u8)0)
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#define USB_EP1 ((u8)1)
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#define USB_EP2 ((u8)2)
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#define USB_EP3 ((u8)3)
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#define USB_EP4 ((u8)4)
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#define USB_EP5 ((u8)5)
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#define USB_EP6 ((u8)6)
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#define USB_EP7 ((u8)7)
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#define USB_EP0 0
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#define USB_EP1 1
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#define USB_EP2 2
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#define USB_EP3 3
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#define USB_EP4 4
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#define USB_EP5 5
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#define USB_EP6 6
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#define USB_EP7 7
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/******************************************************************************
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* USB endpoint register masks / bits
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******************************************************************************/
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/* --- USB endpoint register masks / bits ---------------------------------- */
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/* masks and toggle bits */
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#define USB_EP_RX_CTR (0x8000) /* Correct transfer RX */
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#define USB_EP_RX_DTOG (0x4000) /* Data toggle RX */
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#define USB_EP_RX_STAT (0x3000) /* Endpoint status for RX */
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/* Masks and toggle bits */
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#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */
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#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */
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#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */
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#define USB_EP_SETUP (0x0800) /* Setup transaction completed */
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#define USB_EP_TYPE (0x0600) /* Endpoint type */
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#define USB_EP_KIND (0x0100) /* Endpoint kind.
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* When set and type=bulk -> double buffer
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* When set and type=control -> status out
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*/
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#define USB_EP_SETUP 0x0800 /* Setup transaction completed */
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#define USB_EP_TYPE 0x0600 /* Endpoint type */
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#define USB_EP_KIND 0x0100 /* Endpoint kind.
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* When set and type=bulk -> double buffer
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* When set and type=control -> status out
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*/
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#define USB_EP_TX_CTR (0x0080) /* Correct transfer TX */
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#define USB_EP_TX_DTOG (0x0040) /* Data toggle TX */
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#define USB_EP_TX_STAT (0x0030) /* Endpoint status for TX */
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#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */
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#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */
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#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */
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#define USB_EP_ADDR (0x000F) /* Endpoint Address */
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#define USB_EP_ADDR 0x000F /* Endpoint Address */
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/* Masking all toggle bits */
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#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \
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USB_EP_SETUP | \
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USB_EP_TYPE | \
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USB_EP_KIND | \
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USB_EP_TX_CTR | \
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#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \
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USB_EP_SETUP | \
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USB_EP_TYPE | \
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USB_EP_KIND | \
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USB_EP_TX_CTR | \
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USB_EP_ADDR)
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/* All non toggle bits plus EP_RX toggle bits */
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@ -158,61 +138,52 @@
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#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)
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/* Endpoint status bits for USB_EP_RX_STAT bit field */
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#define USB_EP_RX_STAT_DISABLED (0x0000)
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#define USB_EP_RX_STAT_STALL (0x1000)
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#define USB_EP_RX_STAT_NAK (0x2000)
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#define USB_EP_RX_STAT_VALID (0x3000)
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#define USB_EP_RX_STAT_DISABLED 0x0000
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#define USB_EP_RX_STAT_STALL 0x1000
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#define USB_EP_RX_STAT_NAK 0x2000
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#define USB_EP_RX_STAT_VALID 0x3000
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/* Endpoint status bits for USB_EP_TX_STAT bit field */
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#define USB_EP_TX_STAT_DISABLED (0x0000)
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#define USB_EP_TX_STAT_STALL (0x0010)
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#define USB_EP_TX_STAT_NAK (0x0020)
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#define USB_EP_TX_STAT_VALID (0x0030)
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#define USB_EP_TX_STAT_DISABLED 0x0000
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#define USB_EP_TX_STAT_STALL 0x0010
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#define USB_EP_TX_STAT_NAK 0x0020
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#define USB_EP_TX_STAT_VALID 0x0030
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/* Endpoint type bits for USB_EP_TYPE bit field */
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#define USB_EP_TYPE_BULK (0x0000)
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#define USB_EP_TYPE_CONTROL (0x0200)
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#define USB_EP_TYPE_ISO (0x0400)
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#define USB_EP_TYPE_INTERRUPT (0x0600)
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#define USB_EP_TYPE_BULK 0x0000
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#define USB_EP_TYPE_CONTROL 0x0200
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#define USB_EP_TYPE_ISO 0x0400
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#define USB_EP_TYPE_INTERRUPT 0x0600
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/******************************************************************************
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* USB endpoint register manipulators
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******************************************************************************/
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/* --- USB endpoint register manipulators ---------------------------------- */
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/* Set USB endpoint tx/rx status.
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/*
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* Set USB endpoint tx/rx status.
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*
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* USB status field is changed using an awkward toggle mechanism, that
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* is why we use some helper macros for that.
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*/
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#define USB_SET_EP_RX_STAT(EP, STAT) \
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TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), \
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USB_EP_RX_STAT_TOG_MSK, \
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STAT)
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#define USB_SET_EP_RX_STAT(EP, STAT) \
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TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT)
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#define USB_SET_EP_TX_STAT(EP, STAT) \
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TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), \
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USB_EP_TX_STAT_TOG_MSK, \
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STAT)
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#define USB_SET_EP_TX_STAT(EP, STAT) \
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TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT)
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/* Macros for clearing and setting USB endpoint register bits that do
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/*
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* Macros for clearing and setting USB endpoint register bits that do
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* not use the toggle mechanism.
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*
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* Because the register contains some bits that use the toggle
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* mechanism we need a helper macro here. Otherwise the code gets
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* really messy.
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* mechanism we need a helper macro here. Otherwise the code gets really messy.
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*/
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#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \
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CLR_REG_BIT_MSK(USB_EP_REG(EP), \
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USB_EP_NTOGGLE_MSK, \
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BIT)
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#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \
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CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT)
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#define USB_CLR_EP_RX_CTR(EP) \
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USB_CLR_EP_NTOGGLE_BIT(EP, \
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USB_EP_RX_CTR)
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#define USB_CLR_EP_RX_CTR(EP) \
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USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR)
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#define USB_CLR_EP_TX_CTR(EP) \
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USB_CLR_EP_NTOGGLE_BIT(EP, \
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USB_EP_TX_CTR)
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#define USB_CLR_EP_TX_CTR(EP) \
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USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR)
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#define USB_SET_EP_TYPE(EP, TYPE) \
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SET_REG(USB_EP_REG(EP), \
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@ -226,17 +197,13 @@
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(USB_EP_NTOGGLE_MSK & \
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(~USB_EP_KIND))) | USB_EP_KIND)
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#define USB_CLR_EP_KIND(EP) \
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SET_REG(USB_EP_REG(EP), \
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(GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK & \
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(~USB_EP_KIND))))
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#define USB_CLR_EP_KIND(EP) \
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SET_REG(USB_EP_REG(EP), \
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(GET_REG(USB_EP_REG(EP)) & \
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(USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))
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#define USB_SET_EP_STAT_OUT(EP) \
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USB_SET_EP_KIND(EP)
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#define USB_CLR_EP_STAT_OUT(EP) \
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USB_CLR_EP_KIND(EP)
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#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)
|
||||
#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)
|
||||
|
||||
#define USB_SET_EP_ADDR(EP, ADDR) \
|
||||
SET_REG(USB_EP_REG(EP), \
|
||||
@ -255,58 +222,37 @@
|
||||
GET_REG(USB_EP_REG(EP)) & \
|
||||
(USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG))
|
||||
|
||||
/* --- USB BTABLE registers ------------------------------------------------ */
|
||||
|
||||
/******************************************************************************
|
||||
* USB BTABLE registers
|
||||
******************************************************************************/
|
||||
#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
|
||||
|
||||
#define USB_EP_TX_ADDR(EP) ((u32 *)(USB_PMA_BASE + \
|
||||
(USB_GET_BTABLE+EP*8 ) * 2))
|
||||
#define USB_EP_TX_ADDR(EP) \
|
||||
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
|
||||
|
||||
#define USB_EP_TX_COUNT(EP) ((u32 *)(USB_PMA_BASE + \
|
||||
(USB_GET_BTABLE+EP*8+2) * 2))
|
||||
#define USB_EP_TX_COUNT(EP) \
|
||||
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2))
|
||||
|
||||
#define USB_EP_RX_ADDR(EP) ((u32 *)(USB_PMA_BASE + \
|
||||
(USB_GET_BTABLE+EP*8+4) * 2))
|
||||
#define USB_EP_RX_ADDR(EP) \
|
||||
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2))
|
||||
|
||||
#define USB_EP_RX_COUNT(EP) ((u32 *)(USB_PMA_BASE + \
|
||||
(USB_GET_BTABLE+EP*8+6) * 2))
|
||||
#define USB_EP_RX_COUNT(EP) \
|
||||
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2))
|
||||
|
||||
/******************************************************************************
|
||||
* USB BTABLE manipulators
|
||||
******************************************************************************/
|
||||
/* --- USB BTABLE manipulators --------------------------------------------- */
|
||||
|
||||
#define USB_GET_EP_TX_ADDR(EP) \
|
||||
GET_REG(USB_EP_TX_ADDR(EP))
|
||||
#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))
|
||||
#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))
|
||||
#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))
|
||||
#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))
|
||||
#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)
|
||||
#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)
|
||||
#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)
|
||||
#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
|
||||
|
||||
#define USB_GET_EP_TX_COUNT(EP) \
|
||||
GET_REG(USB_EP_TX_COUNT(EP))
|
||||
#define USB_GET_EP_TX_BUFF(EP) \
|
||||
(USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2))
|
||||
|
||||
#define USB_GET_EP_RX_ADDR(EP) \
|
||||
GET_REG(USB_EP_RX_ADDR(EP))
|
||||
|
||||
#define USB_GET_EP_RX_COUNT(EP) \
|
||||
GET_REG(USB_EP_RX_COUNT(EP))
|
||||
|
||||
#define USB_SET_EP_TX_ADDR(EP, ADDR) \
|
||||
SET_REG(USB_EP_TX_ADDR(EP), ADDR)
|
||||
|
||||
#define USB_SET_EP_TX_COUNT(EP, COUNT) \
|
||||
SET_REG(USB_EP_TX_COUNT(EP), COUNT)
|
||||
|
||||
#define USB_SET_EP_RX_ADDR(EP, ADDR) \
|
||||
SET_REG(USB_EP_RX_ADDR(EP), ADDR)
|
||||
|
||||
#define USB_SET_EP_RX_COUNT(EP, COUNT) \
|
||||
SET_REG(USB_EP_RX_COUNT(EP), COUNT)
|
||||
|
||||
#define USB_GET_EP_TX_BUFF(EP) \
|
||||
(USB_PMA_BASE + \
|
||||
(u8 *)(USB_GET_EP_TX_ADDR(EP) * 2))
|
||||
|
||||
#define USB_GET_EP_RX_BUFF(EP) \
|
||||
(USB_PMA_BASE + \
|
||||
(u8 *)(USB_GET_EP_RX_ADDR(EP) * 2))
|
||||
#define USB_GET_EP_RX_BUFF(EP) \
|
||||
(USB_PMA_BASE + (u8 *)(USB_GET_EP_RX_ADDR(EP) * 2))
|
||||
|
||||
#endif
|
||||
|
||||
@ -21,80 +21,81 @@
|
||||
#define LIBOPENSTM32_USB_DESC
|
||||
|
||||
/* Descriptor types */
|
||||
#define USB_DT_DEVICE 0x01
|
||||
#define USB_DT_CONF 0x02
|
||||
#define USB_DT_STRING 0x03
|
||||
#define USB_DT_INTERFACE 0x04
|
||||
#define USB_DT_ENDPOINT 0x05
|
||||
#define USB_DT_DEVICE 0x01
|
||||
#define USB_DT_CONF 0x02
|
||||
#define USB_DT_STRING 0x03
|
||||
#define USB_DT_INTERFACE 0x04
|
||||
#define USB_DT_ENDPOINT 0x05
|
||||
|
||||
struct usb_desc_head {
|
||||
u8 length; /* Descriptor size 0x012 */
|
||||
u8 type; /* Descriptor type id */
|
||||
u8 length; /* Descriptor size 0x012 */
|
||||
u8 type; /* Descriptor type ID */
|
||||
};
|
||||
|
||||
struct usb_device_desc {
|
||||
struct usb_desc_head h; /* Size 0x12, Id 0x01 */
|
||||
u16 bcd_usb; /* USB Version */
|
||||
u8 class; /* Device class */
|
||||
u8 sub_class; /* Subclass code */
|
||||
u8 protocol; /* Protocol code */
|
||||
u8 max_psize; /* Maximum packet size -> 64bytes */
|
||||
u16 vendor; /* Vendor number */
|
||||
u16 product; /* Device number */
|
||||
u16 bcd_dev; /* Device version */
|
||||
u8 man_desc; /* Index of manufacturer string desc */
|
||||
u8 prod_desc; /* Index of product string desc */
|
||||
u8 sn_desc; /* Index of serial number string desc */
|
||||
u8 num_conf; /* Number of possible configurations */
|
||||
struct usb_desc_head h; /* Size 0x12, ID 0x01 */
|
||||
u16 bcd_usb; /* USB Version */
|
||||
u8 class; /* Device class */
|
||||
u8 sub_class; /* Subclass code */
|
||||
u8 protocol; /* Protocol code */
|
||||
u8 max_psize; /* Maximum packet size -> 64bytes */
|
||||
u16 vendor; /* Vendor number */
|
||||
u16 product; /* Device number */
|
||||
u16 bcd_dev; /* Device version */
|
||||
u8 man_desc; /* Index of manufacturer string desc */
|
||||
u8 prod_desc; /* Index of product string desc */
|
||||
u8 sn_desc; /* Index of serial number string desc */
|
||||
u8 num_conf; /* Number of possible configurations */
|
||||
};
|
||||
|
||||
struct usb_conf_desc_header {
|
||||
struct usb_desc_head h; /* Size 0x09, Id 0x02 */
|
||||
u16 tot_leng; /* Total length of data */
|
||||
u8 num_int; /* Number of interfaces */
|
||||
u8 conf_val; /* Configuration selector */
|
||||
u8 conf_desc; /* Index of conf string desc */
|
||||
u8 attr; /* Attribute bitmap:
|
||||
7 : Bus powered
|
||||
6 : Self powered
|
||||
5 : Remote wakeup
|
||||
4..0 : Reserved -> 0000 */
|
||||
u8 max_power; /* Maximum power consumption in 2mA steps */
|
||||
struct usb_desc_head h; /* Size 0x09, Id 0x02 */
|
||||
u16 tot_leng; /* Total length of data */
|
||||
u8 num_int; /* Number of interfaces */
|
||||
u8 conf_val; /* Configuration selector */
|
||||
u8 conf_desc; /* Index of conf string desc */
|
||||
u8 attr; /* Attribute bitmap:
|
||||
* 7 : Bus powered
|
||||
* 6 : Self powered
|
||||
* 5 : Remote wakeup
|
||||
* 4..0 : Reserved -> 0000
|
||||
*/
|
||||
u8 max_power; /* Maximum power consumption in 2mA steps */
|
||||
};
|
||||
|
||||
struct usb_int_desc_header {
|
||||
struct usb_desc_head h; /* Size 0x09, Id 0x04 */
|
||||
u8 iface_num; /* Interface id number */
|
||||
u8 alt_setting; /* Alternative setting selector */
|
||||
u8 num_endp; /* Endpoints used */
|
||||
u8 class; /* Interface class */
|
||||
u8 sub_class; /* Subclass code */
|
||||
u8 protocol; /* Protocol code */
|
||||
u8 iface_desc; /* Index of interface string desc */
|
||||
struct usb_desc_head h; /* Size 0x09, Id 0x04 */
|
||||
u8 iface_num; /* Interface id number */
|
||||
u8 alt_setting; /* Alternative setting selector */
|
||||
u8 num_endp; /* Endpoints used */
|
||||
u8 class; /* Interface class */
|
||||
u8 sub_class; /* Subclass code */
|
||||
u8 protocol; /* Protocol code */
|
||||
u8 iface_desc; /* Index of interface string desc */
|
||||
};
|
||||
|
||||
struct usb_ep_desc {
|
||||
struct usb_desc_head h; /* Size 0x07, Id 0x05 */
|
||||
u8 ep_addr; /* Endpoint address:
|
||||
0..3 : Endpoint Number
|
||||
4..6 : Reserved -> 0
|
||||
7 : Direction 0=out 1=in */
|
||||
u8 ep_attr; /* Endpoint attributes */
|
||||
u16 max_psize; /* Maximum packet size -> 64bytes */
|
||||
u8 interval; /* Interval for polling endpoint
|
||||
data. Ignored for bulk & control
|
||||
endpoints. */
|
||||
struct usb_desc_head h; /* Size 0x07, Id 0x05 */
|
||||
u8 ep_addr; /* Endpoint address:
|
||||
0..3 : Endpoint Number
|
||||
4..6 : Reserved -> 0
|
||||
7 : Direction 0=out 1=in */
|
||||
u8 ep_attr; /* Endpoint attributes */
|
||||
u16 max_psize; /* Maximum packet size -> 64bytes */
|
||||
u8 interval; /* Interval for polling endpoint
|
||||
data. Ignored for bulk & control
|
||||
endpoints. */
|
||||
};
|
||||
|
||||
struct usb_conf_desc {
|
||||
struct usb_conf_desc_header cdh;
|
||||
struct usb_int_desc_header idh;
|
||||
struct usb_ep_desc ep[];
|
||||
struct usb_conf_desc_header cdh;
|
||||
struct usb_int_desc_header idh;
|
||||
struct usb_ep_desc ep[];
|
||||
};
|
||||
|
||||
struct usb_string_desc {
|
||||
struct usb_desc_head h; /* Size > 0x02, Id 0x03 */
|
||||
u16 string[]; /* String UTF16 encoded */
|
||||
struct usb_desc_head h; /* Size > 0x02, Id 0x03 */
|
||||
u16 string[]; /* String UTF16 encoded */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@ -34,7 +34,6 @@
|
||||
/* Status register (WWDG_SR) */
|
||||
#define WWDG_SR MMIO32(WWDG_BASE + 0x08)
|
||||
|
||||
|
||||
/* --- WWDG_CR values ------------------------------------------------------ */
|
||||
|
||||
/* WDGA: Activation bit */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user