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Some more whitespace + cosmetics.

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This commit is contained in:
Uwe Hermann 2010-12-29 18:29:47 +01:00
parent b5727a6c73
commit d9f6f200c1
9 changed files with 173 additions and 233 deletions
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1
include/libopenstm32/iwdg.h
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@ -37,7 +37,6 @@
/* Status register (IWDG_SR) */ /* Status register (IWDG_SR) */
#define IWDG_SR MMIO32(IWDG_BASE + 0x0C) #define IWDG_SR MMIO32(IWDG_BASE + 0x0C)
/* --- IWDG_KR values ------------------------------------------------------ */ /* --- IWDG_KR values ------------------------------------------------------ */
/* KEY[15:0]: Key value */ /* KEY[15:0]: Key value */

2
include/libopenstm32/nvic.h
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@ -62,7 +62,6 @@
/* STIR: Software Trigger Interrupt Register */ /* STIR: Software Trigger Interrupt Register */
#define NVIC_STIR MMIO32(STIR_BASE) #define NVIC_STIR MMIO32(STIR_BASE)
/* --- IRQ channel numbers-------------------------------------------------- */ /* --- IRQ channel numbers-------------------------------------------------- */
/* Cortex M3 System Interrupts */ /* Cortex M3 System Interrupts */
@ -140,7 +139,6 @@
#define NVIC_DMA2_CHANNEL3_IRQ 58 #define NVIC_DMA2_CHANNEL3_IRQ 58
#define NVIC_DMA2_CHANNEL4_5_IRQ 59 #define NVIC_DMA2_CHANNEL4_5_IRQ 59
/* --- NVIC functions ------------------------------------------------------ */ /* --- NVIC functions ------------------------------------------------------ */
void nvic_enable_irq(u8 irqn); void nvic_enable_irq(u8 irqn);

4
include/libopenstm32/pwr.h
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@ -31,7 +31,6 @@
/* Power control/status register (PWR_CSR) */ /* Power control/status register (PWR_CSR) */
#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) #define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
/* --- PWR_CR values ------------------------------------------------------- */ /* --- PWR_CR values ------------------------------------------------------- */
/* DBP: Disable backup domain write protection */ /* DBP: Disable backup domain write protection */
@ -60,10 +59,9 @@
/* PDDS: Power down deepsleep */ /* PDDS: Power down deepsleep */
#define PWR_CR_PDDS (1 << 1) #define PWR_CR_PDDS (1 << 1)
/* LPDS: Low-power deepsleep */ /* LPDS: Low-power deepsleep */
#define PWR_CR_LPDS (1 << 0) #define PWR_CR_LPDS (1 << 0)
/* --- PWR_CSR values ------------------------------------------------------ */ /* --- PWR_CSR values ------------------------------------------------------ */
/* EWUP: Enable WKUP pin */ /* EWUP: Enable WKUP pin */

16
include/libopenstm32/scb.h
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@ -116,7 +116,7 @@
/* Bits [31:30]: reserved - must be kept cleared */ /* Bits [31:30]: reserved - must be kept cleared */
/* TBLOFF[29:9]: Vector table base offset field */ /* TBLOFF[29:9]: Vector table base offset field */
#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ #define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
/* --- SCB_AIRCR values ---------------------------------------------------- */ /* --- SCB_AIRCR values ---------------------------------------------------- */
@ -174,24 +174,24 @@
/* --- SCB_SHPR1 values ---------------------------------------------------- */ /* --- SCB_SHPR1 values ---------------------------------------------------- */
/* Bits [31:24]: reserved - must be kept cleared */ /* Bits [31:24]: reserved - must be kept cleared */
/* PRI_6[23:16]: Priority of system handler 6, usage fault */ /* PRI_6[23:16]: Priority of system handler 6, usage fault */
#define SCB_SHPR1_PRI_6_LSB 16 #define SCB_SHPR1_PRI_6_LSB 16
/* PRI_5[15:8]: Priority of system handler 5, bus fault */ /* PRI_5[15:8]: Priority of system handler 5, bus fault */
#define SCB_SHPR1_PRI_5_LSB 8 #define SCB_SHPR1_PRI_5_LSB 8
/* PRI_4[7:0]: Priority of system handler 4, memory management fault */ /* PRI_4[7:0]: Priority of system handler 4, memory management fault */
#define SCB_SHPR1_PRI_4_LSB 0 #define SCB_SHPR1_PRI_4_LSB 0
/* --- SCB_SHPR2 values ---------------------------------------------------- */ /* --- SCB_SHPR2 values ---------------------------------------------------- */
/* PRI_11[31:24]: Priority of system handler 11, SVCall */ /* PRI_11[31:24]: Priority of system handler 11, SVCall */
#define SCB_SHPR2_PRI_11_LSB 24 #define SCB_SHPR2_PRI_11_LSB 24
/* Bits [23:0]: reserved - must be kept cleared */ /* Bits [23:0]: reserved - must be kept cleared */
/* --- SCB_SHPR3 values ---------------------------------------------------- */ /* --- SCB_SHPR3 values ---------------------------------------------------- */
/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ /* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
#define SCB_SHPR3_PRI_15_LSB 24 #define SCB_SHPR3_PRI_15_LSB 24
/* PRI_14[23:16]: Priority of system handler 14, PendSV */ /* PRI_14[23:16]: Priority of system handler 14, PendSV */
#define SCB_SHPR3_PRI_14_LSB 16 #define SCB_SHPR3_PRI_14_LSB 16
/* Bits [15:0]: reserved - must be kept cleared */ /* Bits [15:0]: reserved - must be kept cleared */
@ -249,7 +249,7 @@
/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ /* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
#define SCB_CFSR_BFARVALID (1 << 15) #define SCB_CFSR_BFARVALID (1 << 15)
/* Bits [14:13]: reserved - must be kept cleared */ /* Bits [14:13]: reserved - must be kept cleared */
/* STKERR: Bus fault on stacking for exception entry */ /* STKERR: Bus fault on stacking for exception entry */
#define SCB_CFSR_STKERR (1 << 12) #define SCB_CFSR_STKERR (1 << 12)
/* UNSTKERR: Bus fault on unstacking for a return from exception */ /* UNSTKERR: Bus fault on unstacking for a return from exception */
#define SCB_CFSR_UNSTKERR (1 << 11) #define SCB_CFSR_UNSTKERR (1 << 11)

4
include/libopenstm32/spi.h
View File

@ -130,7 +130,7 @@
#define SPI_CR1_SPE (1 << 6) #define SPI_CR1_SPE (1 << 6)
/* BR[2:0]: Baud rate control */ /* BR[2:0]: Baud rate control */
#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3)
@ -138,7 +138,7 @@
#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) #define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
#define SPI_CR1_BR_FPCLK_DIV_2 0x0 #define SPI_CR1_BR_FPCLK_DIV_2 0x0
#define SPI_CR1_BR_FPCLK_DIV_4 0x1 #define SPI_CR1_BR_FPCLK_DIV_4 0x1
#define SPI_CR1_BR_FPCLK_DIV_8 0x2 #define SPI_CR1_BR_FPCLK_DIV_8 0x2
#define SPI_CR1_BR_FPCLK_DIV_16 0x3 #define SPI_CR1_BR_FPCLK_DIV_16 0x3

1
include/libopenstm32/timer.h
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@ -407,7 +407,6 @@
/* UIE: Update interrupt enable */ /* UIE: Update interrupt enable */
#define TIM_DIER_UIE (1 << 0) #define TIM_DIER_UIE (1 << 0)
/* --- TIMx_SR values ------------------------------------------------------ */ /* --- TIMx_SR values ------------------------------------------------------ */
/* CC4OF: Capture/compare 4 overcapture flag */ /* CC4OF: Capture/compare 4 overcapture flag */

268
include/libopenstm32/usb.h
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@ -24,16 +24,11 @@
#include <libopenstm32/common.h> #include <libopenstm32/common.h>
#include <libopenstm32/tools.h> #include <libopenstm32/tools.h>
/****************************************************************************** /* --- USB base addresses -------------------------------------------------- */
* USB base addresses
******************************************************************************/
#define USB_PMA_BASE (0x40006000L) /* USB packet buffer memory base #define USB_PMA_BASE 0x40006000L /* USB packet buffer memory base addr. */
address */
/****************************************************************************** /* --- USB general registers ----------------------------------------------- */
* USB general registers
******************************************************************************/
/* USB Control register */ /* USB Control register */
#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40)) #define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40))
@ -48,31 +43,26 @@
/* USB EP register */ /* USB EP register */
#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP)) #define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP))
/****************************************************************************** /* --- USB control register masks / bits ----------------------------------- */
* USB control register masks / bits
******************************************************************************/
/* Interrupt mask bits, set to 1 to enable interrupt generation */ /* Interrupt mask bits, set to 1 to enable interrupt generation */
#define USB_CNTR_CTRM (0x8000) #define USB_CNTR_CTRM 0x8000
#define USB_CNTR_PMAOVRM (0x4000) #define USB_CNTR_PMAOVRM 0x4000
#define USB_CNTR_ERRM (0x2000) #define USB_CNTR_ERRM 0x2000
#define USB_CNTR_WKUPM (0x1000) #define USB_CNTR_WKUPM 0x1000
#define USB_CNTR_SUSPM (0x0800) #define USB_CNTR_SUSPM 0x0800
#define USB_CNTR_RESETM (0x0400) #define USB_CNTR_RESETM 0x0400
#define USB_CNTR_SOFM (0x0200) #define USB_CNTR_SOFM 0x0200
#define USB_CNTR_ESOFM (0x0100) #define USB_CNTR_ESOFM 0x0100
/* Request/Force bits */ /* Request/Force bits */
#define USB_CNTR_RESUME 0x0010 /* Resume request */
#define USB_CNTR_FSUSP 0x0008 /* Force suspend */
#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */
#define USB_CNTR_PWDN 0x0002 /* Power down */
#define USB_CNTR_FRES 0x0001 /* Force reset */
#define USB_CNTR_RESUME (0x0010) /* Resume request */ /* --- USB interrupt status register masks / bits -------------------------- */
#define USB_CNTR_FSUSP (0x0008) /* Force suspend */
#define USB_CNTR_LP_MODE (0x0004) /* Low-power mode */
#define USB_CNTR_PWDN (0x0002) /* Power down */
#define USB_CNTR_FRES (0x0001) /* Force reset */
/******************************************************************************
* USB interrupt status register masks / bits
******************************************************************************/
#define USB_ISTR_CTR 0x8000 /* Correct Transfer */ #define USB_ISTR_CTR 0x8000 /* Correct Transfer */
#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */ #define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */
@ -85,11 +75,9 @@
#define USB_ISTR_DIR 0x0010 /* Direction of transaction */ #define USB_ISTR_DIR 0x0010 /* Direction of transaction */
#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */ #define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */
/****************************************************************************** /* --- USB interrupt status register manipulators -------------------------- */
* USB interrupt status register manipulators
******************************************************************************/
//#define USB_CLR_ISTR_CTR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_CTR) /* CTR is read only! */ /* Note: CTR is read only! */
#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR) #define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR)
#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR) #define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR)
#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP) #define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP)
@ -98,58 +86,50 @@
#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF) #define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF) #define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
/****************************************************************************** /* --- USB device addres register masks / bits ----------------------------- */
* USB device addres register masks / bits
******************************************************************************/
#define USB_DADDR_ENABLE 0x0080 #define USB_DADDR_ENABLE 0x0080
#define USB_DADDR_ADDR 0x007F #define USB_DADDR_ADDR 0x007F
/****************************************************************************** /* --- USB device addres register manipulators ----------------------------- */
* USB device addres register manipulators
******************************************************************************/
/****************************************************************************** /* --- USB endpoint register offsets --------------------------------------- */
* USB endpoint register offsets
******************************************************************************/
#define USB_EP0 ((u8)0) #define USB_EP0 0
#define USB_EP1 ((u8)1) #define USB_EP1 1
#define USB_EP2 ((u8)2) #define USB_EP2 2
#define USB_EP3 ((u8)3) #define USB_EP3 3
#define USB_EP4 ((u8)4) #define USB_EP4 4
#define USB_EP5 ((u8)5) #define USB_EP5 5
#define USB_EP6 ((u8)6) #define USB_EP6 6
#define USB_EP7 ((u8)7) #define USB_EP7 7
/****************************************************************************** /* --- USB endpoint register masks / bits ---------------------------------- */
* USB endpoint register masks / bits
******************************************************************************/
/* masks and toggle bits */ /* Masks and toggle bits */
#define USB_EP_RX_CTR (0x8000) /* Correct transfer RX */ #define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */
#define USB_EP_RX_DTOG (0x4000) /* Data toggle RX */ #define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */
#define USB_EP_RX_STAT (0x3000) /* Endpoint status for RX */ #define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */
#define USB_EP_SETUP (0x0800) /* Setup transaction completed */ #define USB_EP_SETUP 0x0800 /* Setup transaction completed */
#define USB_EP_TYPE (0x0600) /* Endpoint type */ #define USB_EP_TYPE 0x0600 /* Endpoint type */
#define USB_EP_KIND (0x0100) /* Endpoint kind. #define USB_EP_KIND 0x0100 /* Endpoint kind.
* When set and type=bulk -> double buffer * When set and type=bulk -> double buffer
* When set and type=control -> status out * When set and type=control -> status out
*/ */
#define USB_EP_TX_CTR (0x0080) /* Correct transfer TX */ #define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */
#define USB_EP_TX_DTOG (0x0040) /* Data toggle TX */ #define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */
#define USB_EP_TX_STAT (0x0030) /* Endpoint status for TX */ #define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */
#define USB_EP_ADDR (0x000F) /* Endpoint Address */ #define USB_EP_ADDR 0x000F /* Endpoint Address */
/* Masking all toggle bits */ /* Masking all toggle bits */
#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \ #define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \
USB_EP_SETUP | \ USB_EP_SETUP | \
USB_EP_TYPE | \ USB_EP_TYPE | \
USB_EP_KIND | \ USB_EP_KIND | \
USB_EP_TX_CTR | \ USB_EP_TX_CTR | \
USB_EP_ADDR) USB_EP_ADDR)
/* All non toggle bits plus EP_RX toggle bits */ /* All non toggle bits plus EP_RX toggle bits */
@ -158,61 +138,52 @@
#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK) #define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK)
/* Endpoint status bits for USB_EP_RX_STAT bit field */ /* Endpoint status bits for USB_EP_RX_STAT bit field */
#define USB_EP_RX_STAT_DISABLED (0x0000) #define USB_EP_RX_STAT_DISABLED 0x0000
#define USB_EP_RX_STAT_STALL (0x1000) #define USB_EP_RX_STAT_STALL 0x1000
#define USB_EP_RX_STAT_NAK (0x2000) #define USB_EP_RX_STAT_NAK 0x2000
#define USB_EP_RX_STAT_VALID (0x3000) #define USB_EP_RX_STAT_VALID 0x3000
/* Endpoint status bits for USB_EP_TX_STAT bit field */ /* Endpoint status bits for USB_EP_TX_STAT bit field */
#define USB_EP_TX_STAT_DISABLED (0x0000) #define USB_EP_TX_STAT_DISABLED 0x0000
#define USB_EP_TX_STAT_STALL (0x0010) #define USB_EP_TX_STAT_STALL 0x0010
#define USB_EP_TX_STAT_NAK (0x0020) #define USB_EP_TX_STAT_NAK 0x0020
#define USB_EP_TX_STAT_VALID (0x0030) #define USB_EP_TX_STAT_VALID 0x0030
/* Endpoint type bits for USB_EP_TYPE bit field */ /* Endpoint type bits for USB_EP_TYPE bit field */
#define USB_EP_TYPE_BULK (0x0000) #define USB_EP_TYPE_BULK 0x0000
#define USB_EP_TYPE_CONTROL (0x0200) #define USB_EP_TYPE_CONTROL 0x0200
#define USB_EP_TYPE_ISO (0x0400) #define USB_EP_TYPE_ISO 0x0400
#define USB_EP_TYPE_INTERRUPT (0x0600) #define USB_EP_TYPE_INTERRUPT 0x0600
/****************************************************************************** /* --- USB endpoint register manipulators ---------------------------------- */
* USB endpoint register manipulators
******************************************************************************/
/* Set USB endpoint tx/rx status. /*
* Set USB endpoint tx/rx status.
* *
* USB status field is changed using an awkward toggle mechanism, that * USB status field is changed using an awkward toggle mechanism, that
* is why we use some helper macros for that. * is why we use some helper macros for that.
*/ */
#define USB_SET_EP_RX_STAT(EP, STAT) \ #define USB_SET_EP_RX_STAT(EP, STAT) \
TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), \ TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT)
USB_EP_RX_STAT_TOG_MSK, \
STAT)
#define USB_SET_EP_TX_STAT(EP, STAT) \ #define USB_SET_EP_TX_STAT(EP, STAT) \
TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), \ TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT)
USB_EP_TX_STAT_TOG_MSK, \
STAT)
/* Macros for clearing and setting USB endpoint register bits that do /*
* Macros for clearing and setting USB endpoint register bits that do
* not use the toggle mechanism. * not use the toggle mechanism.
* *
* Because the register contains some bits that use the toggle * Because the register contains some bits that use the toggle
* mechanism we need a helper macro here. Otherwise the code gets * mechanism we need a helper macro here. Otherwise the code gets really messy.
* really messy.
*/ */
#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \ #define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \
CLR_REG_BIT_MSK(USB_EP_REG(EP), \ CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT)
USB_EP_NTOGGLE_MSK, \
BIT)
#define USB_CLR_EP_RX_CTR(EP) \ #define USB_CLR_EP_RX_CTR(EP) \
USB_CLR_EP_NTOGGLE_BIT(EP, \ USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR)
USB_EP_RX_CTR)
#define USB_CLR_EP_TX_CTR(EP) \ #define USB_CLR_EP_TX_CTR(EP) \
USB_CLR_EP_NTOGGLE_BIT(EP, \ USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR)
USB_EP_TX_CTR)
#define USB_SET_EP_TYPE(EP, TYPE) \ #define USB_SET_EP_TYPE(EP, TYPE) \
SET_REG(USB_EP_REG(EP), \ SET_REG(USB_EP_REG(EP), \
@ -226,17 +197,13 @@
(USB_EP_NTOGGLE_MSK & \ (USB_EP_NTOGGLE_MSK & \
(~USB_EP_KIND))) | USB_EP_KIND) (~USB_EP_KIND))) | USB_EP_KIND)
#define USB_CLR_EP_KIND(EP) \ #define USB_CLR_EP_KIND(EP) \
SET_REG(USB_EP_REG(EP), \ SET_REG(USB_EP_REG(EP), \
(GET_REG(USB_EP_REG(EP)) & \ (GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK & \ (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND))))
(~USB_EP_KIND))))
#define USB_SET_EP_STAT_OUT(EP) \ #define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP)
USB_SET_EP_KIND(EP) #define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP)
#define USB_CLR_EP_STAT_OUT(EP) \
USB_CLR_EP_KIND(EP)
#define USB_SET_EP_ADDR(EP, ADDR) \ #define USB_SET_EP_ADDR(EP, ADDR) \
SET_REG(USB_EP_REG(EP), \ SET_REG(USB_EP_REG(EP), \
@ -255,58 +222,37 @@
GET_REG(USB_EP_REG(EP)) & \ GET_REG(USB_EP_REG(EP)) & \
(USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG)) (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG))
/* --- USB BTABLE registers ------------------------------------------------ */
/******************************************************************************
* USB BTABLE registers
******************************************************************************/
#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG) #define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
#define USB_EP_TX_ADDR(EP) ((u32 *)(USB_PMA_BASE + \ #define USB_EP_TX_ADDR(EP) \
(USB_GET_BTABLE+EP*8 ) * 2)) ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
#define USB_EP_TX_COUNT(EP) ((u32 *)(USB_PMA_BASE + \ #define USB_EP_TX_COUNT(EP) \
(USB_GET_BTABLE+EP*8+2) * 2)) ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2))
#define USB_EP_RX_ADDR(EP) ((u32 *)(USB_PMA_BASE + \ #define USB_EP_RX_ADDR(EP) \
(USB_GET_BTABLE+EP*8+4) * 2)) ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2))
#define USB_EP_RX_COUNT(EP) ((u32 *)(USB_PMA_BASE + \ #define USB_EP_RX_COUNT(EP) \
(USB_GET_BTABLE+EP*8+6) * 2)) ((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2))
/****************************************************************************** /* --- USB BTABLE manipulators --------------------------------------------- */
* USB BTABLE manipulators
******************************************************************************/
#define USB_GET_EP_TX_ADDR(EP) \ #define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP))
GET_REG(USB_EP_TX_ADDR(EP)) #define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP))
#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP))
#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP))
#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR)
#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT)
#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR)
#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
#define USB_GET_EP_TX_COUNT(EP) \ #define USB_GET_EP_TX_BUFF(EP) \
GET_REG(USB_EP_TX_COUNT(EP)) (USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2))
#define USB_GET_EP_RX_ADDR(EP) \ #define USB_GET_EP_RX_BUFF(EP) \
GET_REG(USB_EP_RX_ADDR(EP)) (USB_PMA_BASE + (u8 *)(USB_GET_EP_RX_ADDR(EP) * 2))
#define USB_GET_EP_RX_COUNT(EP) \
GET_REG(USB_EP_RX_COUNT(EP))
#define USB_SET_EP_TX_ADDR(EP, ADDR) \
SET_REG(USB_EP_TX_ADDR(EP), ADDR)
#define USB_SET_EP_TX_COUNT(EP, COUNT) \
SET_REG(USB_EP_TX_COUNT(EP), COUNT)
#define USB_SET_EP_RX_ADDR(EP, ADDR) \
SET_REG(USB_EP_RX_ADDR(EP), ADDR)
#define USB_SET_EP_RX_COUNT(EP, COUNT) \
SET_REG(USB_EP_RX_COUNT(EP), COUNT)
#define USB_GET_EP_TX_BUFF(EP) \
(USB_PMA_BASE + \
(u8 *)(USB_GET_EP_TX_ADDR(EP) * 2))
#define USB_GET_EP_RX_BUFF(EP) \
(USB_PMA_BASE + \
(u8 *)(USB_GET_EP_RX_ADDR(EP) * 2))
#endif #endif

109
include/libopenstm32/usb_desc.h
View File

@ -21,80 +21,81 @@
#define LIBOPENSTM32_USB_DESC #define LIBOPENSTM32_USB_DESC
/* Descriptor types */ /* Descriptor types */
#define USB_DT_DEVICE 0x01 #define USB_DT_DEVICE 0x01
#define USB_DT_CONF 0x02 #define USB_DT_CONF 0x02
#define USB_DT_STRING 0x03 #define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04 #define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05 #define USB_DT_ENDPOINT 0x05
struct usb_desc_head { struct usb_desc_head {
u8 length; /* Descriptor size 0x012 */ u8 length; /* Descriptor size 0x012 */
u8 type; /* Descriptor type id */ u8 type; /* Descriptor type ID */
}; };
struct usb_device_desc { struct usb_device_desc {
struct usb_desc_head h; /* Size 0x12, Id 0x01 */ struct usb_desc_head h; /* Size 0x12, ID 0x01 */
u16 bcd_usb; /* USB Version */ u16 bcd_usb; /* USB Version */
u8 class; /* Device class */ u8 class; /* Device class */
u8 sub_class; /* Subclass code */ u8 sub_class; /* Subclass code */
u8 protocol; /* Protocol code */ u8 protocol; /* Protocol code */
u8 max_psize; /* Maximum packet size -> 64bytes */ u8 max_psize; /* Maximum packet size -> 64bytes */
u16 vendor; /* Vendor number */ u16 vendor; /* Vendor number */
u16 product; /* Device number */ u16 product; /* Device number */
u16 bcd_dev; /* Device version */ u16 bcd_dev; /* Device version */
u8 man_desc; /* Index of manufacturer string desc */ u8 man_desc; /* Index of manufacturer string desc */
u8 prod_desc; /* Index of product string desc */ u8 prod_desc; /* Index of product string desc */
u8 sn_desc; /* Index of serial number string desc */ u8 sn_desc; /* Index of serial number string desc */
u8 num_conf; /* Number of possible configurations */ u8 num_conf; /* Number of possible configurations */
}; };
struct usb_conf_desc_header { struct usb_conf_desc_header {
struct usb_desc_head h; /* Size 0x09, Id 0x02 */ struct usb_desc_head h; /* Size 0x09, Id 0x02 */
u16 tot_leng; /* Total length of data */ u16 tot_leng; /* Total length of data */
u8 num_int; /* Number of interfaces */ u8 num_int; /* Number of interfaces */
u8 conf_val; /* Configuration selector */ u8 conf_val; /* Configuration selector */
u8 conf_desc; /* Index of conf string desc */ u8 conf_desc; /* Index of conf string desc */
u8 attr; /* Attribute bitmap: u8 attr; /* Attribute bitmap:
7 : Bus powered * 7 : Bus powered
6 : Self powered * 6 : Self powered
5 : Remote wakeup * 5 : Remote wakeup
4..0 : Reserved -> 0000 */ * 4..0 : Reserved -> 0000
u8 max_power; /* Maximum power consumption in 2mA steps */ */
u8 max_power; /* Maximum power consumption in 2mA steps */
}; };
struct usb_int_desc_header { struct usb_int_desc_header {
struct usb_desc_head h; /* Size 0x09, Id 0x04 */ struct usb_desc_head h; /* Size 0x09, Id 0x04 */
u8 iface_num; /* Interface id number */ u8 iface_num; /* Interface id number */
u8 alt_setting; /* Alternative setting selector */ u8 alt_setting; /* Alternative setting selector */
u8 num_endp; /* Endpoints used */ u8 num_endp; /* Endpoints used */
u8 class; /* Interface class */ u8 class; /* Interface class */
u8 sub_class; /* Subclass code */ u8 sub_class; /* Subclass code */
u8 protocol; /* Protocol code */ u8 protocol; /* Protocol code */
u8 iface_desc; /* Index of interface string desc */ u8 iface_desc; /* Index of interface string desc */
}; };
struct usb_ep_desc { struct usb_ep_desc {
struct usb_desc_head h; /* Size 0x07, Id 0x05 */ struct usb_desc_head h; /* Size 0x07, Id 0x05 */
u8 ep_addr; /* Endpoint address: u8 ep_addr; /* Endpoint address:
0..3 : Endpoint Number 0..3 : Endpoint Number
4..6 : Reserved -> 0 4..6 : Reserved -> 0
7 : Direction 0=out 1=in */ 7 : Direction 0=out 1=in */
u8 ep_attr; /* Endpoint attributes */ u8 ep_attr; /* Endpoint attributes */
u16 max_psize; /* Maximum packet size -> 64bytes */ u16 max_psize; /* Maximum packet size -> 64bytes */
u8 interval; /* Interval for polling endpoint u8 interval; /* Interval for polling endpoint
data. Ignored for bulk & control data. Ignored for bulk & control
endpoints. */ endpoints. */
}; };
struct usb_conf_desc { struct usb_conf_desc {
struct usb_conf_desc_header cdh; struct usb_conf_desc_header cdh;
struct usb_int_desc_header idh; struct usb_int_desc_header idh;
struct usb_ep_desc ep[]; struct usb_ep_desc ep[];
}; };
struct usb_string_desc { struct usb_string_desc {
struct usb_desc_head h; /* Size > 0x02, Id 0x03 */ struct usb_desc_head h; /* Size > 0x02, Id 0x03 */
u16 string[]; /* String UTF16 encoded */ u16 string[]; /* String UTF16 encoded */
}; };
#endif #endif

1
include/libopenstm32/wwdg.h
View File

@ -34,7 +34,6 @@
/* Status register (WWDG_SR) */ /* Status register (WWDG_SR) */
#define WWDG_SR MMIO32(WWDG_BASE + 0x08) #define WWDG_SR MMIO32(WWDG_BASE + 0x08)
/* --- WWDG_CR values ------------------------------------------------------ */ /* --- WWDG_CR values ------------------------------------------------------ */
/* WDGA: Activation bit */ /* WDGA: Activation bit */