stm32f4: rcc: doxygen updates
Uses doxygen groups instead of just ------ comments, so they now automatically get documented online.
This commit is contained in:
Karl Palsson
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db5f550611
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db7a8d71ca
@ -45,51 +45,81 @@
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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/* --- RCC registers ------------------------------------------------------- */
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/** @defgroup rcc_registers RCC Registers
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* @ingroup rcc_defines
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* @brief Reset / Clock Control Registers
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@{*/
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/** Clock control register */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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/** PLL Configuration register */
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#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04)
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/** Clock Configuration register */
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#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
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/** Clock interrupt register */
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#define RCC_CIR MMIO32(RCC_BASE + 0x0c)
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/** AHB1 peripheral reset register */
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#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10)
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/** AHB2 peripheral reset register */
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#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14)
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/** AHB3 peripheral reset register */
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#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18)
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/* RCC_BASE + 0x1c Reserved */
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/** APB1 peripheral reset register */
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#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20)
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/** APB2 peripheral reset register */
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#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24)
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/* RCC_BASE + 0x28 Reserved */
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/* RCC_BASE + 0x2c Reserved */
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/** AHB1 peripheral enable register */
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#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30)
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/** AHB2 peripheral enable register */
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#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34)
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/** AHB3 peripheral enable register */
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#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38)
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/* RCC_BASE + 0x3c Reserved */
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/** APB1 peripheral enable register */
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#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40)
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/** APB2 peripheral enable register */
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#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44)
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/* RCC_BASE + 0x48 Reserved */
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/* RCC_BASE + 0x4c Reserved */
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/** AHB1 peripheral enable in low power register */
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#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50)
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/** AHB2 peripheral enable in low power register */
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#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54)
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/** AHB3 peripheral enable in low power register */
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#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58)
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/* RCC_BASE + 0x5c Reserved */
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/** APB1 peripheral enable in low power register */
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#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60)
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/** APB2 peripheral enable in low power register */
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#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64)
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/* RCC_BASE + 0x68 Reserved */
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/* RCC_BASE + 0x6c Reserved */
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/** Backup Domain control register */
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#define RCC_BDCR MMIO32(RCC_BASE + 0x70)
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/** Clock control and status register */
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#define RCC_CSR MMIO32(RCC_BASE + 0x74)
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/* RCC_BASE + 0x78 Reserved */
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/* RCC_BASE + 0x7c Reserved */
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/** Spread spectrum clock generation register */
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#define RCC_SSCGR MMIO32(RCC_BASE + 0x80)
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/** PLLI2S configuration register */
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#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84)
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/** PLLSAI configuration register */
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#define RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88)
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/** Dedicated clocks configuration register */
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#define RCC_DCKCFGR MMIO32(RCC_BASE + 0x8C)
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/** RCC clocks gated enable register */
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#define RCC_CKGATENR MMIO32(RCC_BASE + 0x90)
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/** RCC Dedicated Clocks Configuration Register 2 */
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#define RCC_DCKCFGR2 MMIO32(RCC_BASE + 0x94)
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/*@}*/
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/* --- RCC_CR values ------------------------------------------------------- */
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/** @defgroup rcc_cr_values RCC_CR values
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* @ingroup rcc_registers
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* @brief Clock Control register values
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@{*/
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#define RCC_CR_PLLSAIRDY (1 << 29)
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#define RCC_CR_PLLSAION (1 << 28)
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#define RCC_CR_PLLI2SRDY (1 << 27)
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@ -106,9 +136,12 @@
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#define RCC_CR_HSITRIM_MASK 0x1f
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#define RCC_CR_HSIRDY (1 << 1)
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#define RCC_CR_HSION (1 << 0)
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/*@}*/
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/* --- RCC_PLLCFGR values -------------------------------------------------- */
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/** @defgroup rcc_pllcfgr_values RCC_PLLCFGR values
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* @ingroup rcc_registers
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* @brief PLL Configuration register values
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@{*/
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/* PLLR: [30:28] */
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#define RCC_PLLCFGR_PLLR_SHIFT 28
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#define RCC_PLLCFGR_PLLR_MASK 0x7
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@ -125,9 +158,12 @@
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/* PLLM: [5:0] */
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#define RCC_PLLCFGR_PLLM_SHIFT 0
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#define RCC_PLLCFGR_PLLM_MASK 0x3f
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/*@}*/
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/* --- RCC_CFGR values ----------------------------------------------------- */
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/** @defgroup rcc_cfgr_values RCC_CFGR values
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* @ingroup rcc_registers
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* @brief Clock Configuration register values
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@{*/
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/* MCO2: Microcontroller clock output 2 */
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#define RCC_CFGR_MCO2_SHIFT 30
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#define RCC_CFGR_MC02_MASK 0x3
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@ -200,9 +236,12 @@
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#define RCC_CFGR_SW_HSI 0x0
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#define RCC_CFGR_SW_HSE 0x1
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#define RCC_CFGR_SW_PLL 0x2
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/*@}*/
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/* --- RCC_CIR values ------------------------------------------------------ */
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/** @defgroup rcc_cir_values RCC_CIR values
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* @ingroup rcc_registers
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* @brief Clock Interrupt register values
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@{*/
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/* Clock security system interrupt clear bit */
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#define RCC_CIR_CSSC (1 << 23)
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@ -235,7 +274,12 @@
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#define RCC_CIR_HSIRDYF (1 << 2)
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#define RCC_CIR_LSERDYF (1 << 1)
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#define RCC_CIR_LSIRDYF (1 << 0)
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/*@}*/
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/** @defgroup rcc_AxBY_reset_values AHB/APB reset bits
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* @ingroup rcc_registers
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* @brief Reset bits for the AHB/APB peripherals
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@{*/
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/* --- RCC_AHB1RSTR values ------------------------------------------------- */
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#define RCC_AHB1RSTR_OTGHSRST (1 << 29)
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@ -316,7 +360,12 @@
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#define RCC_APB2RSTR_USART1RST (1 << 4)
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#define RCC_APB2RSTR_TIM8RST (1 << 1)
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#define RCC_APB2RSTR_TIM1RST (1 << 0)
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/*@}*/
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/** @defgroup rcc_AxBY_reset_values AHB/APB enable bits
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* @ingroup rcc_registers
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* @brief Enable bits for the AHB/APB peripherals
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@{*/
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/* --- RCC_AHB1ENR values ------------------------------------------------- */
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#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30)
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@ -499,9 +548,12 @@
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#define RCC_APB2LPENR_USART1LPEN (1 << 4)
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#define RCC_APB2LPENR_TIM8LPEN (1 << 1)
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#define RCC_APB2LPENR_TIM1LPEN (1 << 0)
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/*@}*/
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/* --- RCC_BDCR values ----------------------------------------------------- */
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/** @defgroup rcc_bdcr_values RCC_BDCR values
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* @ingroup rcc_registers
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* @brief Backup Domain control register values
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@{*/
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#define RCC_BDCR_BDRST (1 << 16)
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#define RCC_BDCR_RTCEN (1 << 15)
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/* RCC_BDCR[9:8]: RTCSEL */
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@ -515,9 +567,12 @@
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#define RCC_BDCR_LSEBYP (1 << 2)
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#define RCC_BDCR_LSERDY (1 << 1)
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#define RCC_BDCR_LSEON (1 << 0)
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/*@}*/
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/* --- RCC_CSR values ------------------------------------------------------ */
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/** @defgroup rcc_csr_values RCC_CSR values
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* @ingroup rcc_registers
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* @brief Clock control and status register values
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@{*/
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#define RCC_CSR_LPWRRSTF (1 << 31)
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#define RCC_CSR_WWDGRSTF (1 << 30)
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#define RCC_CSR_IWDGRSTF (1 << 29)
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@ -531,9 +586,12 @@
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RCC_CSR_PINRSTF | RCC_CSR_BORRSTF)
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#define RCC_CSR_LSIRDY (1 << 1)
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#define RCC_CSR_LSION (1 << 0)
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/*@}*/
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/* --- RCC_SSCGR values ---------------------------------------------------- */
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/** @defgroup rcc_sscgr_values RCC_SSCGR values
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* @ingroup rcc_registers
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* @brief Spread spectrum clock generation register values
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@{*/
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/* PLL spread spectrum clock generation documented in Datasheet. */
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#define RCC_SSCGR_SSCGEN (1 << 31)
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@ -544,7 +602,12 @@
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/* RCC_SSCGR[15:0]: MODPER */
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#define RCC_SSCGR_MODPER_SHIFT 0
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#define RCC_SSCGR_MODPER_MASK 0x1fff
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/*@}*/
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/** @defgroup rcc_pllded_values RCC_PLLxxx/DCKy values
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* @ingroup rcc_registers
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* @brief PLL and other dedicated clock register values
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@{*/
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/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */
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/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */
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@ -614,9 +677,10 @@
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#define RCC_DCKCFGR_PLLI2SDIVQ_SHIFT 0
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#define RCC_DCKCFGR_PLLI2SDIVQ_MASK 0x1f
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/*@}*/
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/** @defgroup rcc_ckgatenr_values RCC_CKGATENR bits
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* @ingroup rcc_defines
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* @ingroup rcc_registers
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* @brief Allows to enable or disable the clock gating for the specified IPs.
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@{*/
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#define RCC_CKGATENR_EVTCL_CKEN (1<<7)
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