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Added support for STM32F0.

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This commit is contained in:
Vegard Storheil Eriksen 2012-10-24 18:07:38 +02:00
parent 1ce2af4819
commit dddb51ca1c
2 changed files with 21 additions and 7 deletions
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3
flashstub/stm32.s
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@ -8,7 +8,8 @@ _start:
ldr r3, _size ldr r3, _size
mov r5, #1 mov r5, #1
_next: _next:
cbz r3, _done cmp r3, #0
beq _done
@ Write PG command to FLASH_CR @ Write PG command to FLASH_CR
str r5, [r0, #0x10] str r5, [r0, #0x10]
@ Write data to flash (half-word) @ Write data to flash (half-word)

23
src/stm32f1.c
View File

@ -58,6 +58,7 @@ static int stm32f1_flash_write(struct target_s *target, uint32_t dest,
static const char stm32f1_driver_str[] = "STM32, Medium density."; static const char stm32f1_driver_str[] = "STM32, Medium density.";
static const char stm32hd_driver_str[] = "STM32, High density."; static const char stm32hd_driver_str[] = "STM32, High density.";
static const char stm32f3_driver_str[] = "STM32F3xx"; static const char stm32f3_driver_str[] = "STM32F3xx";
static const char stm32f0_driver_str[] = "STM32F0xx";
static const char stm32f1_xml_memory_map[] = "<?xml version=\"1.0\"?>" static const char stm32f1_xml_memory_map[] = "<?xml version=\"1.0\"?>"
/* "<!DOCTYPE memory-map " /* "<!DOCTYPE memory-map "
@ -111,6 +112,7 @@ static const char stm32hd_xml_memory_map[] = "<?xml version=\"1.0\"?>"
#define SR_EOP 0x20 #define SR_EOP 0x20
#define DBGMCU_IDCODE 0xE0042000 #define DBGMCU_IDCODE 0xE0042000
#define DBGMCU_IDCODE_F0 0x40015800
uint16_t stm32f1_flash_write_stub[] = { uint16_t stm32f1_flash_write_stub[] = {
// _start: // _start:
@ -121,7 +123,8 @@ uint16_t stm32f1_flash_write_stub[] = {
0x4b09, // ldr r3, [pc, #36] // _size 0x4b09, // ldr r3, [pc, #36] // _size
0x2501, // movs r5, #1 0x2501, // movs r5, #1
// _next: // _next:
0xb153, // cbz r3, _done 0x2b00, // cmp r3, #0
0xd00a, // beq _done
0x6105, // str r5, [r0, #16] 0x6105, // str r5, [r0, #16]
0x8814, // ldrh r4, [r2] 0x8814, // ldrh r4, [r2]
0x800c, // strh r4, [r1] 0x800c, // strh r4, [r1]
@ -134,10 +137,9 @@ uint16_t stm32f1_flash_write_stub[] = {
0x3b02, // subs r3, #2 0x3b02, // subs r3, #2
0x3102, // adds r1, #2 0x3102, // adds r1, #2
0x3202, // adds r2, #2 0x3202, // adds r2, #2
0xe7f3, // b _next 0xe7f2, // b _next
// _done: // _done:
0xbe00, // bkpt 0xbe00, // bkpt
0x0000,
// .org 0x28 // .org 0x28
// _flashbase: // _flashbase:
0x2000, 0x4002, // .word 0x40022000 (FPEC_BASE) 0x2000, 0x4002, // .word 0x40022000 (FPEC_BASE)
@ -180,9 +182,20 @@ int stm32f1_probe(struct target_s *target)
target->flash_write = stm32f1_flash_write; target->flash_write = stm32f1_flash_write;
target_add_commands(target, stm32f1_cmd_list, "STM32"); target_add_commands(target, stm32f1_cmd_list, "STM32");
return 0; return 0;
default:
return -1;
} }
idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE_F0);
switch(idcode & 0xFFF) {
case 0x440: /* STM32F0 */
target->driver = stm32f0_driver_str;
target->xml_mem_map = stm32f1_xml_memory_map;
target->flash_erase = stm32md_flash_erase;
target->flash_write = stm32f1_flash_write;
target_add_commands(target, stm32f1_cmd_list, "STM32");
return 0;
}
return -1;
} }
static void stm32f1_flash_unlock(ADIv5_AP_t *ap) static void stm32f1_flash_unlock(ADIv5_AP_t *ap)