From df5e3e5ff115af6c145d0d7ccd23631dffaeebd9 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 22 Jan 2013 22:27:38 +0000 Subject: [PATCH] [l1] PWR: fix style for common code Code added for L1 to support the PWR Control block didn't properly follow the HACKING_COMMON_DOC guidelines. The naming was wrong, and some headers were missing. This commit has no functional changes, it only addresses the style and structure problems. --- .../libopencm3/stm32/common/pwr_common_all.h | 119 ++++++++++ include/libopencm3/stm32/f1/pwr.h | 40 ++++ include/libopencm3/stm32/f4/pwr.h | 19 +- include/libopencm3/stm32/l1/pwr.h | 53 +++-- include/libopencm3/stm32/l1/rcc.h | 2 +- include/libopencm3/stm32/pwr.h | 122 +--------- lib/stm32/common/pwr_common_all.c | 217 ++++++++++++++++++ lib/stm32/f1/Makefile | 2 +- lib/stm32/f4/Makefile | 1 + lib/stm32/l1/Makefile | 2 +- lib/stm32/l1/{pwr_chipset.c => pwr.c} | 2 +- lib/stm32/l1/rcc.c | 2 +- 12 files changed, 446 insertions(+), 135 deletions(-) create mode 100644 include/libopencm3/stm32/common/pwr_common_all.h create mode 100644 include/libopencm3/stm32/f1/pwr.h create mode 100644 lib/stm32/common/pwr_common_all.c rename lib/stm32/l1/{pwr_chipset.c => pwr.c} (96%) diff --git a/include/libopencm3/stm32/common/pwr_common_all.h b/include/libopencm3/stm32/common/pwr_common_all.h new file mode 100644 index 00000000..cc9fd229 --- /dev/null +++ b/include/libopencm3/stm32/common/pwr_common_all.h @@ -0,0 +1,119 @@ +/** @addtogroup pwr_defines */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H */ + +#ifndef LIBOPENCM3_PWR_COMMON_ALL_H +#define LIBOPENCM3_PWR_COMMON_ALL_H + +/**@{*/ + +#include + +/* --- PWR registers ------------------------------------------------------- */ + +/* Power control register (PWR_CR) */ +#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) + +/* Power control/status register (PWR_CSR) */ +#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:9]: Reserved, must be kept at reset value. */ + +/* DBP: Disable backup domain write protection */ +#define PWR_CR_DBP (1 << 8) + +/* PLS[7:5]: PVD level selection */ +#define PWR_CR_PLS_LSB 5 +/** @defgroup pwr_pls PVD level selection +@ingroup STM32F_pwr_defines + +@{*/ +#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB) +/**@}*/ +#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB) + +/* PVDE: Power voltage detector enable */ +#define PWR_CR_PVDE (1 << 4) + +/* CSBF: Clear standby flag */ +#define PWR_CR_CSBF (1 << 3) + +/* CWUF: Clear wakeup flag */ +#define PWR_CR_CWUF (1 << 2) + +/* PDDS: Power down deepsleep */ +#define PWR_CR_PDDS (1 << 1) + +/* LPDS: Low-power deepsleep */ +#define PWR_CR_LPDS (1 << 0) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* Bits [31:9]: Reserved, must be kept at reset value. */ + +/* EWUP: Enable WKUP pin */ +#define PWR_CSR_EWUP (1 << 8) + +/* Bits [7:3]: Reserved, must be kept at reset value. */ + +/* PVDO: PVD output */ +#define PWR_CSR_PVDO (1 << 2) + +/* SBF: Standby flag */ +#define PWR_CSR_SBF (1 << 1) + +/* WUF: Wakeup flag */ +#define PWR_CSR_WUF (1 << 0) + +/* --- PWR function prototypes ------------------------------------------- */ + +BEGIN_DECLS + +void pwr_disable_backup_domain_write_protect(void); +void pwr_enable_backup_domain_write_protect(void); +void pwr_enable_power_voltage_detect(u32 pvd_level); +void pwr_disable_power_voltage_detect(void); +void pwr_clear_standby_flag(void); +void pwr_clear_wakeup_flag(void); +void pwr_set_standby_mode(void); +void pwr_set_stop_mode(void); +void pwr_voltage_regulator_on_in_stop(void); +void pwr_voltage_regulator_low_power_in_stop(void); +void pwr_enable_wakeup_pin(void); +void pwr_disable_wakeup_pin(void); +bool pwr_voltage_high(void); +bool pwr_get_standby_flag(void); +bool pwr_get_wakeup_flag(void); + +END_DECLS + +/**@}*/ +#endif diff --git a/include/libopencm3/stm32/f1/pwr.h b/include/libopencm3/stm32/f1/pwr.h new file mode 100644 index 00000000..2875492f --- /dev/null +++ b/include/libopencm3/stm32/f1/pwr.h @@ -0,0 +1,40 @@ +/** @defgroup pwr_defines PWR Defines + +@brief Defined Constants and Types for the STM32F1xx PWR Control + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +#include +#include + +#endif + diff --git a/include/libopencm3/stm32/f4/pwr.h b/include/libopencm3/stm32/f4/pwr.h index 25fb163c..c9b27fd5 100644 --- a/include/libopencm3/stm32/f4/pwr.h +++ b/include/libopencm3/stm32/f4/pwr.h @@ -1,3 +1,15 @@ +/** @defgroup pwr_defines PWR Defines + +@brief Defined Constants and Types for the STM32F4xx Power Control + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2011 Stephen Caudle + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,10 +29,11 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_PWR_F4_H -#define LIBOPENCM3_PWR_F4_H +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H -#include +#include +#include /* * This file extends the common STM32 version with definitions only diff --git a/include/libopencm3/stm32/l1/pwr.h b/include/libopencm3/stm32/l1/pwr.h index 41992d78..e976d464 100644 --- a/include/libopencm3/stm32/l1/pwr.h +++ b/include/libopencm3/stm32/l1/pwr.h @@ -1,3 +1,18 @@ +/** @defgroup pwr_defines PWR Defines + +@brief Defined Constants and Types for the STM32L1xx Power Control + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2011 Stephen Caudle +@author @htmlonly © @endhtmlonly 2012 Karl Palsson + +@date 1 July 2012 + +LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -18,10 +33,11 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_PWR_L1_H -#define LIBOPENCM3_PWR_L1_H +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H -#include +#include +#include /* * This file extends the common STM32 version with definitions only @@ -33,47 +49,52 @@ /* Bits [31:15]: Reserved */ /* LPRUN: Low power run mode */ -#define PWR_CR_LPRUN (1 << 14) +#define PWR_CR_LPRUN (1 << 14) /* VOS[12:11]: Regulator voltage scaling output selection */ -#define PWR_CR_VOS_LSB 11 +#define PWR_CR_VOS_LSB 11 /** @defgroup pwr_vos Voltage Scaling Output level selection @ingroup STM32F_pwr_defines @{*/ -#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB) -#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB) -#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB) /**@}*/ -#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB) /* FWU: Fast wakeup */ -#define PWR_CR_FWU (1 << 10) +#define PWR_CR_FWU (1 << 10) /* ULP: Ultralow power mode */ -#define PWR_CR_ULP (1 << 9) +#define PWR_CR_ULP (1 << 9) + +/* LPSDSR: Low-power deepsleep/sleep/low power run */ +#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */ /* --- PWR_CSR values ------------------------------------------------------- */ /* Bits [31:11]: Reserved */ /* EWUP3: Enable WKUP3 pin */ -#define PWR_CSR_EWUP3 (1 << 10) +#define PWR_CSR_EWUP3 (1 << 10) /* EWUP2: Enable WKUP2 pin */ -#define PWR_CSR_EWUP2 (1 << 9) +#define PWR_CSR_EWUP2 (1 << 9) /* EWUP1: Enable WKUP1 pin */ -#define PWR_CSR_EWUP1 PWR_CSR_EWUP +#define PWR_CSR_EWUP1 PWR_CSR_EWUP /* REGLPF : Regulator LP flag */ -#define PWR_CSR_REGLPF (1 << 5) +#define PWR_CSR_REGLPF (1 << 5) /* VOSF: Voltage Scaling select flag */ -#define PWR_CSR_VOSF (1 << 4) +#define PWR_CSR_VOSF (1 << 4) /* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */ #define PWR_CSR_VREFINTRDYF (1 << 3) + + /* --- Function prototypes ------------------------------------------------- */ typedef enum { diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index 21b073b8..f301ce3d 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -46,7 +46,7 @@ LGPL License Terms @ref lgpl_license #include #include -#include +#include /* --- RCC registers ------------------------------------------------------- */ diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h index 34b24078..1d907a9c 100644 --- a/include/libopencm3/stm32/pwr.h +++ b/include/libopencm3/stm32/pwr.h @@ -1,22 +1,8 @@ -/** @defgroup STM32F_pwr_defines PWR Defines +/* This provides unification of code over STM32F subfamilies */ -@ingroup STM32F_defines - -@brief libopencm3 STM32F Power Control - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 17 August 2012 - -LGPL License Terms @ref lgpl_license - */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2010 Thomas Otto - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -31,101 +17,15 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see . */ -/**@{*/ - -#ifndef LIBOPENCM3_PWR_H -#define LIBOPENCM3_PWR_H - -#include -#include - -/* --- PWR registers ------------------------------------------------------- */ - -/* Power control register (PWR_CR) */ -#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) - -/* Power control/status register (PWR_CSR) */ -#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) - -/* --- PWR_CR values ------------------------------------------------------- */ - -/* Bits [31:9]: Reserved, must be kept at reset value. */ - -/* DBP: Disable backup domain write protection */ -#define PWR_CR_DBP (1 << 8) - -/* PLS[7:5]: PVD level selection */ -#define PWR_CR_PLS_LSB 5 -/** @defgroup pwr_pls PVD level selection -@ingroup STM32F_pwr_defines - -@{*/ -#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB) -#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB) -/**@}*/ -#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB) - -/* PVDE: Power voltage detector enable */ -#define PWR_CR_PVDE (1 << 4) - -/* CSBF: Clear standby flag */ -#define PWR_CR_CSBF (1 << 3) - -/* CWUF: Clear wakeup flag */ -#define PWR_CR_CWUF (1 << 2) - -/* PDDS: Power down deepsleep */ -#define PWR_CR_PDDS (1 << 1) - -/* LPDS: Low-power deepsleep */ -#define PWR_CR_LPDS (1 << 0) - -/* --- PWR_CSR values ------------------------------------------------------ */ - -/* Bits [31:9]: Reserved, must be kept at reset value. */ - -/* EWUP: Enable WKUP pin */ -#define PWR_CSR_EWUP (1 << 8) - -/* Bits [7:3]: Reserved, must be kept at reset value. */ - -/* PVDO: PVD output */ -#define PWR_CSR_PVDO (1 << 2) - -/* SBF: Standby flag */ -#define PWR_CSR_SBF (1 << 1) - -/* WUF: Wakeup flag */ -#define PWR_CSR_WUF (1 << 0) - -/* --- PWR function prototypes ------------------------------------------- */ - -BEGIN_DECLS - -void pwr_disable_backup_domain_write_protect(void); -void pwr_enable_backup_domain_write_protect(void); -void pwr_enable_power_voltage_detect(u32 pvd_level); -void pwr_disable_power_voltage_detect(void); -void pwr_clear_standby_flag(void); -void pwr_clear_wakeup_flag(void); -void pwr_set_standby_mode(void); -void pwr_set_stop_mode(void); -void pwr_voltage_regulator_on_in_stop(void); -void pwr_voltage_regulator_low_power_in_stop(void); -void pwr_enable_wakeup_pin(void); -void pwr_disable_wakeup_pin(void); -bool pwr_voltage_high(void); -bool pwr_get_standby_flag(void); -bool pwr_get_wakeup_flag(void); - -END_DECLS - +#if defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." #endif -/**@}*/ diff --git a/lib/stm32/common/pwr_common_all.c b/lib/stm32/common/pwr_common_all.c new file mode 100644 index 00000000..451ed1cf --- /dev/null +++ b/lib/stm32/common/pwr_common_all.c @@ -0,0 +1,217 @@ +/** @defgroup STM32F1xx-pwr-file PWR + +@ingroup STM32F1xx + +@brief libopencm3 STM32F1xx Power Control + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies + +@date 18 August 2012 + +This library supports the power control system for the +STM32F1 series of ARM Cortex Microcontrollers by ST Microelectronics. + +LGPL License Terms @ref lgpl_license +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +/*---------------------------------------------------------------------------*/ +/** @brief Disable Backup Domain Write Protection. + +This allows backup domain registers to be changed. These registers are write +protected after a reset. +*/ + +void pwr_disable_backup_domain_write_protect(void) +{ + PWR_CR |= PWR_CR_DBP; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Re-enable Backup Domain Write Protection. + +This protects backup domain registers from inadvertent change. +*/ + +void pwr_enable_backup_domain_write_protect(void) +{ + PWR_CR &= ~PWR_CR_DBP; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable Power Voltage Detector. + +This provides voltage level threshold detection. The result of detection is +provided in the power voltage detector output flag (see @ref pwr_voltage_high) +or by setting the EXTI16 interrupt (see datasheet for configuration details). + +@param[in] pvd_level u32. Taken from @ref pwr_pls. +*/ + +void pwr_enable_power_voltage_detect(u32 pvd_level) +{ + PWR_CR &= ~PWR_CR_PLS_MASK; + PWR_CR |= (PWR_CR_PVDE | pvd_level); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Disable Power Voltage Detector. + +*/ + +void pwr_disable_power_voltage_detect(void) +{ + PWR_CR &= ~PWR_CR_PVDE; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Clear the Standby Flag. + +This is set when the processor returns from a standby mode. +*/ + +void pwr_clear_standby_flag(void) +{ + PWR_CR |= PWR_CR_CSBF; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Clear the Wakeup Flag. + +This is set when the processor receives a wakeup signal. +*/ + +void pwr_clear_wakeup_flag(void) +{ + PWR_CR |= PWR_CR_CWUF; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set Standby Mode in Deep Sleep. + +*/ + +void pwr_set_standby_mode(void) +{ + PWR_CR |= PWR_CR_PDDS; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set Stop Mode in Deep Sleep. + +*/ + +void pwr_set_stop_mode(void) +{ + PWR_CR &= ~PWR_CR_PDDS; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Voltage Regulator On in Stop Mode. + +*/ + +void pwr_voltage_regulator_on_in_stop(void) +{ + PWR_CR &= ~PWR_CR_LPDS; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Voltage Regulator Low Power in Stop Mode. + +*/ + +void pwr_voltage_regulator_low_power_in_stop(void) +{ + PWR_CR |= PWR_CR_LPDS; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable Wakeup Pin. + +The wakeup pin is used for waking the processor from standby mode. +*/ + +void pwr_enable_wakeup_pin(void) +{ + PWR_CSR |= PWR_CSR_EWUP; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Release Wakeup Pin. + +The wakeup pin is used for general purpose I/O. +*/ + +void pwr_disable_wakeup_pin(void) +{ + PWR_CSR &= ~PWR_CSR_EWUP; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Get Voltage Detector Output. + +The voltage detector threshold must be set when the power voltage detector is +enabled, see @ref pwr_enable_power_voltage_detect. + +@returns boolean: TRUE if the power voltage is above the preset voltage +threshold. +*/ + +bool pwr_voltage_high(void) +{ + return (PWR_CSR & PWR_CSR_PVDO); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Get Standby Flag. + +The standby flag is set when the processor returns from a standby state. It is +cleared by software (see @ref pwr_clear_standby_flag). + +@returns boolean: TRUE if the processor was in standby state. +*/ + +bool pwr_get_standby_flag(void) +{ + return (PWR_CSR & PWR_CSR_SBF); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Get Wakeup Flag. + +The wakeup flag is set when a wakeup event has been received. It is +cleared by software (see @ref pwr_clear_wakeup_flag). + +@returns boolean: TRUE if a wakeup event was received. +*/ + +bool pwr_get_wakeup_flag(void) +{ + return (PWR_CSR & PWR_CSR_WUF); +} +/**@}*/ + diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index 6bc21f75..ba0d4b8f 100644 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -30,7 +30,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \ ARFLAGS = rcs OBJS = rcc.o gpio.o adc.o flash.o rtc.o dma.o exti.o ethernet.o \ usb_f103.o usb.o usb_control.o usb_standard.o can.o \ - timer.o usb_f107.o desig.o pwr.o \ + timer.o usb_f107.o desig.o pwr_common_all.o \ usb_fx07_common.o \ gpio_common_all.o dma_common_f13.o spi_common_all.o \ dac_common_all.o usart_common_all.o iwdg_common_all.o \ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 2b02281d..ee7f953b 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -32,6 +32,7 @@ ARFLAGS = rcs OBJS = rcc.o gpio.o flash.o exti2.o pwr.o timer.o \ usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \ usb_f207.o adc.o dma.o \ + pwr_common_all.o \ gpio_common_all.o gpio_common_f24.o dma_common_f24.o spi_common_all.o \ dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o \ crc_common_all.o diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index 32c8fd3d..c4e767f0 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -31,7 +31,7 @@ ARFLAGS = rcs OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o crc_common_all.o OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o -OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o +OBJS += pwr_common_all.o pwr.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/l1/pwr_chipset.c b/lib/stm32/l1/pwr.c similarity index 96% rename from lib/stm32/l1/pwr_chipset.c rename to lib/stm32/l1/pwr.c index 9f4f5996..85418515 100644 --- a/lib/stm32/l1/pwr_chipset.c +++ b/lib/stm32/l1/pwr.c @@ -17,7 +17,7 @@ * along with this library. If not, see . */ -#include +#include void pwr_set_vos_scale(vos_scale_t scale) { diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c index 4864731f..b2fce8c2 100644 --- a/lib/stm32/l1/rcc.c +++ b/lib/stm32/l1/rcc.c @@ -23,7 +23,7 @@ #include #include -#include +#include /* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */ u32 rcc_ppre1_frequency = 2097000;