stm32: dma: cselr: factorize register definition.
F09x and L4 share the same cselr register, as well as some L0s, factorize definitions in a new shared header and add helpers. fyi, that register allows to redefine dma channel peripheral mapping - see device datasheet for mapping tables.
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include/libopencm3/stm32/common/dma_common_csel.h
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include/libopencm3/stm32/common/dma_common_csel.h
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/** @addtogroup dma_defines
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H
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The order of header inclusion is important. dma.h includes the device
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specific memorymap.h header before including this header file.*/
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/**@{*/
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/** @cond */
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#ifdef LIBOPENCM3_DMA_H
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/** @endcond */
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#pragma once
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/* DMA channel selection register (DMAx_CSELR) */
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#define DMA_CSELR(dma_base) MMIO32((dma_base) + 0xA8)
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#define DMA1_CSELR DMA_CSELR(DMA1)
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#define DMA2_CSELR DMA_CSELR(DMA2)
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/* --- DMA_CSELR values -------------------------------------------- */
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#define DMA_CSELR_CxS_SHIFT(channel) (4 * ((channel) - 1))
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#define DMA_CSELR_CxS_MASK (0x0f)
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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END_DECLS
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/** @cond */
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#else
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#warning "dma_common_csel.h should not be included explicitly, only via dma.h"
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#endif
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/** @endcond */
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/**@}*/
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#define LIBOPENCM3_DMA_H
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#include <libopencm3/stm32/common/dma_common_l1f013.h>
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/* DMA channel selection register (DMAx_CSELR) */
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#define DMA_CSELR(dma_base) MMIO32((dma_base) + 0xA8)
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#define DMA1_CSELR DMA_CSELR(DMA1)
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#define DMA2_CSELR DMA_CSELR(DMA2)
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#include <libopencm3/stm32/common/dma_common_csel.h>
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#endif
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@ -33,10 +33,6 @@
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#define LIBOPENCM3_DMA_H
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#include <libopencm3/stm32/common/dma_common_l1f013.h>
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/* DMA channel selection register (DMAx_CSELR) */
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#define DMA_CSELR(dma_base) MMIO32((dma_base) + 0xA8)
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#define DMA1_CSELR DMA_CSELR(DMA1)
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#define DMA2_CSELR DMA_CSELR(DMA2)
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#include <libopencm3/stm32/common/dma_common_csel.h>
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#endif
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