From e1ebcc9da832e19ea5a6a5a59353b18c0b938894 Mon Sep 17 00:00:00 2001 From: BuFran Date: Mon, 22 Jul 2013 18:43:16 +0200 Subject: [PATCH] [Cortex] Add preliminary support for core-dependent defines ARMv6m / ARMv7m, ARMv7em --- include/libopencm3/cm3/fpb.h | 5 + include/libopencm3/cm3/itm.h | 5 + include/libopencm3/cm3/memorymap.h | 39 ++++++- include/libopencm3/cm3/mpu.h | 110 ++++++++++++++++++ include/libopencm3/cm3/nvic.h | 64 ++++++++--- include/libopencm3/cm3/scb.h | 99 ++++++++++++---- include/libopencm3/cm3/sync.h | 8 +- include/libopencm3/cm3/systick.h | 61 +++++++--- include/libopencm3/cm3/tpiu.h | 5 + include/libopencm3/cm3/vector.h | 8 +- lib/cm3/nvic.c | 176 ++++++++++++++++------------- lib/cm3/scb.c | 6 + lib/cm3/sync.c | 16 +-- lib/cm3/systick.c | 126 ++++++++++----------- lib/cm3/vector.c | 16 ++- 15 files changed, 526 insertions(+), 218 deletions(-) create mode 100644 include/libopencm3/cm3/mpu.h diff --git a/include/libopencm3/cm3/fpb.h b/include/libopencm3/cm3/fpb.h index 8829f81d..3c1d22b7 100644 --- a/include/libopencm3/cm3/fpb.h +++ b/include/libopencm3/cm3/fpb.h @@ -22,6 +22,11 @@ /* Cortex-M3 Flash Patch and Breakpoint (FPB) unit */ +/* Those defined only on ARMv7 and above */ +#if !defined(__ARM_ARCH_7M__) || !defined(__ARM_ARCH_7EM__) +#error "Flash Patch and Breakpoint not available in CM0" +#endif + /* Note: We always use "FPB" as abbreviation, docs sometimes use only "FP". */ /* --- FPB registers ------------------------------------------------------- */ diff --git a/include/libopencm3/cm3/itm.h b/include/libopencm3/cm3/itm.h index a05b904f..3d907ed8 100644 --- a/include/libopencm3/cm3/itm.h +++ b/include/libopencm3/cm3/itm.h @@ -22,6 +22,11 @@ /* Cortex-M3 Instrumentation Trace Macrocell (ITM) */ +/* Those defined only on ARMv7 and above */ +#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) +#error "Instrumentation Trace Macrocell not available in CM0" +#endif + /* --- ITM registers ------------------------------------------------------- */ /* Stimulus Port x (ITM_STIM[x]) */ diff --git a/include/libopencm3/cm3/memorymap.h b/include/libopencm3/cm3/memorymap.h index c8974f3d..7339fdbf 100644 --- a/include/libopencm3/cm3/memorymap.h +++ b/include/libopencm3/cm3/memorymap.h @@ -20,17 +20,33 @@ #ifndef LIBOPENCM3_CM3_MEMORYMAP_H #define LIBOPENCM3_CM3_MEMORYMAP_H -/* --- ARM Cortex-M3 specific definitions ---------------------------------- */ +/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */ /* Private peripheral bus - Internal */ #define PPBI_BASE 0xE0000000 + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +/* ITM: Instrumentation Trace Macrocell */ #define ITM_BASE (PPBI_BASE + 0x0000) + +/* DWT: Data Watchpoint and Trace unit */ #define DWT_BASE (PPBI_BASE + 0x1000) + +/* FPB: Flash Patch and Breakpoint unit */ #define FPB_BASE (PPBI_BASE + 0x2000) +#endif + /* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */ + #define SCS_BASE (PPBI_BASE + 0xE000) + /* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */ + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) #define TPIU_BASE (PPBI_BASE + 0x40000) +#endif /* --- ITM: Instrumentation Trace Macrocell --- */ /* TODO */ @@ -43,17 +59,38 @@ /* --- SCS: System Control Space --- */ +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* ITR: Interrupt Type Register */ #define ITR_BASE (SCS_BASE + 0x0000) +#endif + /* SYS_TICK: System Timer */ #define SYS_TICK_BASE (SCS_BASE + 0x0010) + /* NVIC: Nested Vector Interrupt Controller */ #define NVIC_BASE (SCS_BASE + 0x0100) + /* SCB: System Control Block */ #define SCB_BASE (SCS_BASE + 0x0D00) + +#ifdef CM0_PLUS +/* MPU: Memory protection unit */ +#define MPU_BASE (SCS_BASE + 0x0D90) +#endif + +/* Those defined only on CM0*/ +#if defined(__ARM_ARCH_6M__) +/* DEBUG: Debug control and configuration */ +#define DEBUG_BASE (SCS_BASE + 0x0DF0) +#endif + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* STE: Software Trigger Interrupt Register */ #define STIR_BASE (SCS_BASE + 0x0F00) /* ID: ID space */ #define ID_BASE (SCS_BASE + 0x0FD0) +#endif #endif diff --git a/include/libopencm3/cm3/mpu.h b/include/libopencm3/cm3/mpu.h new file mode 100644 index 00000000..9efa83ed --- /dev/null +++ b/include/libopencm3/cm3/mpu.h @@ -0,0 +1,110 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM0_MPU_H +#define LIBOPENCM3_CM0_MPU_H + +#ifndef CM0_PLUS +#error "mpu is supported only on CM0+ architecture" +#else + +#include +#include + +/* --- SCB: Registers ------------------------------------------------------ */ + +#define MPU_TYPE MMIO32(MPU_BASE + 0x00) +#define MPU_CTRL MMIO32(MPU_BASE + 0x04) +#define MPU_RNR MMIO32(MPU_BASE + 0x08) +#define MPU_RBAR MMIO32(MPU_BASE + 0x0C) +#define MPU_RASR MMIO32(MPU_BASE + 0x10) + +/* --- MPU values ---------------------------------------------------------- */ + +/* --- MPU_TYPE values ----------------------------------------------------- */ + +#define MPU_TYPE_IREGION_LSB 16 +#define MPU_TYPE_IREGION (0xFF << MPU_TYPE_IREGION_LSB) +#define MPU_TYPE_DREGION_LSB 8 +#define MPU_TYPE_DREGION (0xFF << MPU_TYPE_DREGION_LSB) +#define MPU_TYPE_SEPARATE (1<<0) + +/* --- MPU_CTRL values ----------------------------------------------------- */ + +#define MPU_CTRL_PRIVDEFENA (1<<2) +#define MPU_CTRL_HFNMIENA (1<<1) +#define MPU_CTRL_ENABLE (1<<0) + +/* --- MPU_RNR values ------------------------------------------------------ */ + +#define MPU_RNR_REGION_LSB 0 +#define MPU_RNR_REGION (0xFF << MPU_RNR_REGION_LSB) + +/* --- MPU_RBAR values ----------------------------------------------------- */ + +#define MPU_RBAR_ADDR_LSB 8 +#define MPU_RBAR_ADDR (0x00FFFFFF << MPU_RBAR_REGION_LSB) +#define MPU_RBAR_VALID (1<<4) +#define MPU_RBAR_REGION_LSB 0 +#define MPU_RBAR_REGION (0xF << MPU_RBAR_REGION_LSB) + +/* --- MPU_RASR values ----------------------------------------------------- */ + +#define MPU_RASR_ATTRS_LSB 16 +#define MPU_RASR_ATTRS (0xFFFF << MPU_RASR_ATTRS_LSB) +#define MPU_RASR_SRD_LSB 8 +#define MPU_RASR_SRD (0xFF << MPU_RASR_SRD_LSB) +#define MPU_RASR_SIZE_LSB 1 +#define MPU_RASR_SIZE (0x1F << MPU_RASR_SIZE_LSB) +#define MPU_RASR_ENABLE (1 << 0) + + +#define MPU_RASR_ATTR_XN (1 << 28) +#define MPU_RASR_ATTR_AP (7 << 24) +#define MPU_RASR_ATTR_AP_PNO_UNO (0 << 24) +#define MPU_RASR_ATTR_AP_PRW_UNO (1 << 24) +#define MPU_RASR_ATTR_AP_PRW_URO (2 << 24) +#define MPU_RASR_ATTR_AP_PRW_URW (3 << 24) +#define MPU_RASR_ATTR_AP_PRO_UNO (5 << 24) +#define MPU_RASR_ATTR_AP_PRO_URO (6 << 24) +#define MPU_RASR_ATTR_AP_PRO_URO (7 << 24) +#define MPU_RASR_ATTR_TEX (7 << 19) +#define MPU_RASR_ATTR_S (1 << 18) +#define MPU_RASR_ATTR_C (1 << 17) +#define MPU_RASR_ATTR_B (1 << 16) +#define MPU_RASR_ATTR_SCB (7 << 16) +#define MPU_RASR_ATTR_SCB_SH_STRONG (0 << 16) +#define MPU_RASR_ATTR_SCB_SH_DEVICE (1 << 16) +#define MPU_RASR_ATTR_SCB_NSH_WT (2 << 16) +#define MPU_RASR_ATTR_SCB_NSH_WB (3 << 16) +#define MPU_RASR_ATTR_SCB_SH_STRONG (4 << 16) +#define MPU_RASR_ATTR_SCB_SH_DEVICE (5 << 16) +#define MPU_RASR_ATTR_SCB_SH_WT (6 << 16) +#define MPU_RASR_ATTR_SCB_SH_WB (7 << 16) + +/* --- MPU functions ------------------------------------------------------- */ + +BEGIN_DECLS + + +END_DECLS + +#endif /* CM0_PLUS */ + +#endif diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h index b8f2a29a..56261beb 100644 --- a/include/libopencm3/cm3/nvic.h +++ b/include/libopencm3/cm3/nvic.h @@ -19,18 +19,18 @@ * along with this library. If not, see . */ /** @defgroup CM3_nvic_defines NVIC Defines - -@brief libopencm3 Cortex Nested Vectored Interrupt Controller - -@ingroup CM3_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license + * + * @brief libopencm3 Cortex Nested Vectored Interrupt Controller + * + * @ingroup CM3_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license */ /**@{*/ @@ -44,6 +44,7 @@ LGPL License Terms @ref lgpl_license /* ISER: Interrupt Set Enable Registers */ /* Note: 8 32bit Registers */ +/* Note: Single register on CM0 */ #define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \ (iser_id * 4)) @@ -51,6 +52,7 @@ LGPL License Terms @ref lgpl_license /* ICER: Interrupt Clear Enable Registers */ /* Note: 8 32bit Registers */ +/* Note: Single register on CM0 */ #define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \ (icer_id * 4)) @@ -58,6 +60,7 @@ LGPL License Terms @ref lgpl_license /* ISPR: Interrupt Set Pending Registers */ /* Note: 8 32bit Registers */ +/* Note: Single register on CM0 */ #define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \ (ispr_id * 4)) @@ -65,42 +68,59 @@ LGPL License Terms @ref lgpl_license /* ICPR: Interrupt Clear Pending Registers */ /* Note: 8 32bit Registers */ +/* Note: Single register on CM0 */ #define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \ (icpr_id * 4)) /* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* IABR: Interrupt Active Bit Register */ /* Note: 8 32bit Registers */ #define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \ (iabr_id * 4)) +#endif /* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ /* IPR: Interrupt Priority Registers */ /* Note: 240 8bit Registers */ +/* Note: 32 8bit Registers on CM0 */ #define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \ ipr_id) +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* STIR: Software Trigger Interrupt Register */ #define NVIC_STIR MMIO32(STIR_BASE) +#endif /* --- IRQ channel numbers-------------------------------------------------- */ -/* Cortex M3 and M4 System Interrupts */ -/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts +/* Cortex M0, M3 and M4 System Interrupts */ +/** @defgroup nvic_sysint Cortex M0/M3/M4 System Interrupts @ingroup CM3_nvic_defines IRQ numbers -3 and -6 to -9 are reserved @{*/ #define NVIC_NMI_IRQ -14 #define NVIC_HARD_FAULT_IRQ -13 + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) #define NVIC_MEM_MANAGE_IRQ -12 #define NVIC_BUS_FAULT_IRQ -11 #define NVIC_USAGE_FAULT_IRQ -10 +#endif + /* irq numbers -6 to -9 are reserved */ #define NVIC_SV_CALL_IRQ -5 + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) #define DEBUG_MONITOR_IRQ -4 +#endif + /* irq number -3 reserved */ #define NVIC_PENDSV_IRQ -2 #define NVIC_SYSTICK_IRQ -1 @@ -123,21 +143,29 @@ void nvic_disable_irq(uint8_t irqn); uint8_t nvic_get_pending_irq(uint8_t irqn); void nvic_set_pending_irq(uint8_t irqn); void nvic_clear_pending_irq(uint8_t irqn); -uint8_t nvic_get_active_irq(uint8_t irqn); uint8_t nvic_get_irq_enabled(uint8_t irqn); void nvic_set_priority(uint8_t irqn, uint8_t priority); + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +uint8_t nvic_get_active_irq(uint8_t irqn); void nvic_generate_software_interrupt(uint16_t irqn); +#endif void WEAK reset_handler(void); void WEAK nmi_handler(void); void WEAK hard_fault_handler(void); +void WEAK sv_call_handler(void); +void WEAK pend_sv_handler(void); +void WEAK sys_tick_handler(void); + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) void WEAK mem_manage_handler(void); void WEAK bus_fault_handler(void); void WEAK usage_fault_handler(void); -void WEAK sv_call_handler(void); void WEAK debug_monitor_handler(void); -void WEAK pend_sv_handler(void); -void WEAK sys_tick_handler(void); +#endif END_DECLS diff --git a/include/libopencm3/cm3/scb.h b/include/libopencm3/cm3/scb.h index 9f043c3d..c6e9d1b6 100644 --- a/include/libopencm3/cm3/scb.h +++ b/include/libopencm3/cm3/scb.h @@ -51,6 +51,8 @@ #define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2) #define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3) +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* SHCSR: System Handler Control and State Register */ #define SCB_SHCSR MMIO32(SCB_BASE + 0x24) @@ -128,61 +130,96 @@ /* MVFR1: Media and Floating-Point Feature Register 1 */ #define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) +#endif /* --- SCB values ---------------------------------------------------------- */ /* --- SCB_CPUID values ---------------------------------------------------- */ /* Implementer[31:24]: Implementer code */ -#define SCP_CPUID_IMPLEMENTER_LSB 24 +#define SCB_CPUID_IMPLEMENTER_LSB 24 +#define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB) /* Variant[23:20]: Variant number */ -#define SCP_CPUID_VARIANT_LSB 20 -/* Constant[19:16]: Reads as 0xF */ -#define SCP_CPUID_CONSTANT_LSB 16 +#define SCB_CPUID_VARIANT_LSB 20 +#define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB) +/* Constant[19:16]: Reads as 0xF (ARMv7-M) M3, M4 */ +/* Constant[19:16]: Reads as 0xC (ARMv6-M) M0, M0+ */ +#define SCB_CPUID_CONSTANT_LSB 16 +#define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB) +#define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB) +#define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB) + /* PartNo[15:4]: Part number of the processor */ -#define SCP_CPUID_PARTNO_LSB 4 +#define SCB_CPUID_PARTNO_LSB 4 +#define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB) /* Revision[3:0]: Revision number */ -#define SCP_CPUID_REVISION_LSB 0 +#define SCB_CPUID_REVISION_LSB 0 +#define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB) /* --- SCB_ICSR values ----------------------------------------------------- */ /* NMIPENDSET: NMI set-pending bit */ -#define SCB_ICSR_NMIPENDSET (1 << 31) +#define SCB_ICSR_NMIPENDSET (1 << 31) /* Bits [30:29]: reserved - must be kept cleared */ /* PENDSVSET: PendSV set-pending bit */ -#define SCB_ICSR_PENDSVSET (1 << 28) +#define SCB_ICSR_PENDSVSET (1 << 28) /* PENDSVCLR: PendSV clear-pending bit */ -#define SCB_ICSR_PENDSVCLR (1 << 27) +#define SCB_ICSR_PENDSVCLR (1 << 27) /* PENDSTSET: SysTick exception set-pending bit */ -#define SCB_ICSR_PENDSTSET (1 << 26) +#define SCB_ICSR_PENDSTSET (1 << 26) /* PENDSTCLR: SysTick exception clear-pending bit */ -#define SCB_ICSR_PENDSTCLR (1 << 25) +#define SCB_ICSR_PENDSTCLR (1 << 25) /* Bit 24: reserved - must be kept cleared */ /* Bit 23: reserved for debug - reads as 0 when not in debug mode */ +#define SCB_ICSR_ISRPREEMPT (1 << 23) /* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ -#define SCB_ICSR_ISRPENDING (1 << 22) +#define SCB_ICSR_ISRPENDING (1 << 22) /* VECTPENDING[21:12] Pending vector */ -#define SCB_ICSR_VECTPENDING_LSB 12 +#define SCB_ICSR_VECTPENDING_LSB 12 +#define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB) /* RETOBASE: Return to base level */ -#define SCB_ICSR_RETOBASE (1 << 11) +#define SCB_ICSR_RETOBASE (1 << 11) /* Bits [10:9]: reserved - must be kept cleared */ /* VECTACTIVE[8:0] Active vector */ -#define SCB_ICSR_VECTACTIVE_LSB 0 +#define SCB_ICSR_VECTACTIVE_LSB 0 +#define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB) + /* --- SCB_VTOR values ----------------------------------------------------- */ +/* IMPLEMENTATION DEFINED */ + +#if defined(__ARM_ARCH_6M__) + +#define SCB_VTOR_TBLOFF_LSB 7 +#define SCB_VTOR_TBLOFF (0x1FFFFFF << SCB_VTOR_TBLOFF_LSB) + +#elif defined(CM1) +/* VTOR not defined there */ + +#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + /* Bits [31:30]: reserved - must be kept cleared */ /* TBLOFF[29:9]: Vector table base offset field */ /* inconsistent datasheet - LSB could be 11 */ -#define SCB_VTOR_TBLOFF_LSB 9 +/* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */ +#define SCB_VTOR_TBLOFF_LSB 9 +#define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB) + +#endif /* --- SCB_AIRCR values ---------------------------------------------------- */ /* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ -#define SCB_AIRCR_VECTKEYSTAT_LSB 16 -#define SCB_AIRCR_VECTKEY 0x05FA0000 +#define SCB_AIRCR_VECTKEYSTAT_LSB 16 +#define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB) +#define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB) + /* ENDIANESS Data endianness bit */ #define SCB_AIRCR_ENDIANESS (1 << 15) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* Bits [14:11]: reserved - must be kept cleared */ /* PRIGROUP[10:8]: Interrupt priority grouping field */ #define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) @@ -193,12 +230,18 @@ #define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) #define SCB_AIRCR_PRIGROUP_SHIFT 8 /* Bits [7:3]: reserved - must be kept cleared */ +#endif + /* SYSRESETREQ System reset request */ #define SCB_AIRCR_SYSRESETREQ (1 << 2) /* VECTCLRACTIVE */ #define SCB_AIRCR_VECTCLRACTIVE (1 << 1) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* VECTRESET */ #define SCB_AIRCR_VECTRESET (1 << 0) +#endif /* --- SCB_SCR values ------------------------------------------------------ */ @@ -217,18 +260,27 @@ /* Bits [31:10]: reserved - must be kept cleared */ /* STKALIGN */ #define SCB_CCR_STKALIGN (1 << 9) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* BFHFNMIGN */ #define SCB_CCR_BFHFNMIGN (1 << 8) /* Bits [7:5]: reserved - must be kept cleared */ /* DIV_0_TRP */ #define SCB_CCR_DIV_0_TRP (1 << 4) +#endif + /* UNALIGN_TRP */ #define SCB_CCR_UNALIGN_TRP (1 << 3) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* Bit 2: reserved - must be kept cleared */ /* USERSETMPEND */ #define SCB_CCR_USERSETMPEND (1 << 1) /* NONBASETHRDENA */ #define SCB_CCR_NONBASETHRDENA (1 << 0) +#endif /* --- SCB_SHPR1 values ---------------------------------------------------- */ @@ -254,6 +306,8 @@ #define SCB_SHPR3_PRI_14_LSB 16 /* Bits [15:0]: reserved - must be kept cleared */ +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* --- SCB_SHCSR values ---------------------------------------------------- */ /* Bits [31:19]: reserved - must be kept cleared */ @@ -361,6 +415,7 @@ #define SCB_CPACR_CP10 (1 << 20) /* CPACR [22:23]: Access privileges for coprocessor 11 */ #define SCB_CPACR_CP11 (1 << 22) +#endif /* --- SCB functions ------------------------------------------------------- */ @@ -383,11 +438,13 @@ struct scb_exception_stack_frame { : [frameptr]"=r" (f)); \ } while (0) -void scb_reset_core(void) __attribute__((noreturn, naked)); void scb_reset_system(void) __attribute__((noreturn, naked)); -void scb_set_priority_grouping(uint32_t prigroup); -/* TODO: */ +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +void scb_reset_core(void) __attribute__((noreturn, naked)); +void scb_set_priority_grouping(uint32_t prigroup); +#endif END_DECLS diff --git a/include/libopencm3/cm3/sync.h b/include/libopencm3/cm3/sync.h index d4832568..3ee96f97 100644 --- a/include/libopencm3/cm3/sync.h +++ b/include/libopencm3/cm3/sync.h @@ -22,6 +22,8 @@ #include "common.h" +void __dmb(void); + /* Implements synchronisation primitives as discussed in the ARM document * DHT0008A (ID081709) "ARM Synchronization Primitives" and the ARM v7-M * Architecture Reference Manual. @@ -29,9 +31,11 @@ /* --- Exclusive load and store instructions ------------------------------- */ +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) + uint32_t __ldrex(volatile uint32_t *addr); uint32_t __strex(uint32_t val, volatile uint32_t *addr); -void __dmb(void); /* --- Convenience functions ----------------------------------------------- */ @@ -46,3 +50,5 @@ void mutex_lock(mutex_t *m); void mutex_unlock(mutex_t *m); #endif + +#endif diff --git a/include/libopencm3/cm3/systick.h b/include/libopencm3/cm3/systick.h index 22e8cbe9..bbd2ff27 100644 --- a/include/libopencm3/cm3/systick.h +++ b/include/libopencm3/cm3/systick.h @@ -18,18 +18,24 @@ * along with this library. If not, see . */ /** @defgroup CM3_systick_defines SysTick Defines + * + * @brief libopencm3 Defined Constants and Types for the Cortex SysTick + * + * @ingroup CM3_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2010 Thomas Otto + * + * @date 19 August 2012 + * + * LGPL License Terms @ref lgpl_license + */ -@brief libopencm3 Defined Constants and Types for the Cortex SysTick - -@ingroup CM3_defines - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 19 August 2012 - -LGPL License Terms @ref lgpl_license +/** + * @note this file has been not following the register naming scheme, the + * correct names defined, and the old ones stay there for compatibility with + * old software (will be deprecated in the future) */ /**@{*/ @@ -44,44 +50,64 @@ LGPL License Terms @ref lgpl_license /* Control and status register (STK_CTRL) */ #define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00) +#define STK_CSR MMIO32(SYS_TICK_BASE + 0x00) /* reload value register (STK_LOAD) */ #define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04) +#define STK_RVR MMIO32(SYS_TICK_BASE + 0x04) /* current value register (STK_VAL) */ #define STK_VAL MMIO32(SYS_TICK_BASE + 0x08) +#define STK_CVR MMIO32(SYS_TICK_BASE + 0x08) /* calibration value register (STK_CALIB) */ #define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) -/* --- STK_CTRL values ----------------------------------------------------- */ +/* --- STK_CSR values ------------------------------------------------------ */ /* Bits [31:17] Reserved, must be kept cleared. */ /* COUNTFLAG: */ #define STK_CTRL_COUNTFLAG (1 << 16) +#define STK_CSR_COUNTFLAG (1 << 16) + /* Bits [15:3] Reserved, must be kept cleared. */ /* CLKSOURCE: Clock source selection */ -#define STK_CTRL_CLKSOURCE (1 << 2) #define STK_CTRL_CLKSOURCE_LSB 2 +#define STK_CTRL_CLKSOURCE (1 << STK_CTRL_CLKSOURCE_LSB) + +#define STK_CSR_CLKSOURCE_LSB 2 +#define STK_CSR_CLKSOURCE (1 << STK_CSR_CLKSOURCE_LSB) + /** @defgroup systick_clksource Clock source selection @ingroup CM3_systick_defines @{*/ -#define STK_CTRL_CLKSOURCE_AHB_DIV8 0 -#define STK_CTRL_CLKSOURCE_AHB 1 +#if defined(__ARM_ARCH_6M__) +#define STK_CSR_CLKSOURCE_EXT (0 << STK_CSR_CLKSOURCE_LSB) +#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB) +#else +#define STK_CTRL_CLKSOURCE_AHB_DIV8 (0 << STK_CTRL_CLKSOURCE_LSB) +#define STK_CTRL_CLKSOURCE_AHB (1 << STK_CTRL_CLKSOURCE_LSB) +#endif /**@}*/ /* TICKINT: SysTick exception request enable */ #define STK_CTRL_TICKINT (1 << 1) +#define STK_CSR_TICKINT (1 << 1) /* ENABLE: Counter enable */ #define STK_CTRL_ENABLE (1 << 0) +#define STK_CSR_ENABLE (1 << 0) -/* --- STK_LOAD values ----------------------------------------------------- */ +/* --- STK_RVR values ------------------------------------------------------ */ /* Bits [31:24] Reserved, must be kept cleared. */ /* RELOAD[23:0]: RELOAD value */ +#define STK_RVR_RELOAD 0x00FFFFFF -/* --- STK_VAL values ------------------------------------------------------ */ + +/* --- STK_CVR values ------------------------------------------------------ */ /* Bits [31:24] Reserved, must be kept cleared. */ /* CURRENT[23:0]: Current counter value */ +#define STK_CVR_CURRENT 0x00FFFFFF + /* --- STK_CALIB values ---------------------------------------------------- */ /* NOREF: NOREF flag */ @@ -90,6 +116,7 @@ LGPL License Terms @ref lgpl_license #define STK_CALIB_SKEW (1 << 30) /* Bits [29:24] Reserved, must be kept cleared. */ /* TENMS[23:0]: Calibration value */ +#define STK_CALIB_TENMS 0x00FFFFFF /* --- Function Prototypes ------------------------------------------------- */ diff --git a/include/libopencm3/cm3/tpiu.h b/include/libopencm3/cm3/tpiu.h index 63522eb2..d14cc02b 100644 --- a/include/libopencm3/cm3/tpiu.h +++ b/include/libopencm3/cm3/tpiu.h @@ -22,6 +22,11 @@ /* Cortex-M3 Trace Port Interface Unit (TPIU) */ +/* Those defined only on ARMv7 and above */ +#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) +#error "Trace Port Interface Unit not available in CM0" +#endif + /* --- TPIU registers ------------------------------------------------------ */ /* Supported Synchronous Port Size (TPIU_SSPSR) */ diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h index abbfb0cc..17ebb152 100644 --- a/include/libopencm3/cm3/vector.h +++ b/include/libopencm3/cm3/vector.h @@ -49,12 +49,12 @@ typedef struct { vector_table_entry_t reset; vector_table_entry_t nmi; vector_table_entry_t hard_fault; - vector_table_entry_t memory_manage_fault; - vector_table_entry_t bus_fault; - vector_table_entry_t usage_fault; + vector_table_entry_t memory_manage_fault; /* not in CM0 */ + vector_table_entry_t bus_fault; /* not in CM0 */ + vector_table_entry_t usage_fault; /* not in CM0 */ vector_table_entry_t reserved_x001c[4]; vector_table_entry_t sv_call; - vector_table_entry_t debug_monitor; + vector_table_entry_t debug_monitor; /* not in CM0 */ vector_table_entry_t reserved_x0034; vector_table_entry_t pend_sv; vector_table_entry_t systick; diff --git a/lib/cm3/nvic.c b/lib/cm3/nvic.c index aefbfca7..1a8f563a 100644 --- a/lib/cm3/nvic.c +++ b/lib/cm3/nvic.c @@ -19,26 +19,27 @@ * along with this library. If not, see . */ /** @defgroup CM3_nvic_file NVIC - -@ingroup CM3_files - -@brief libopencm3 Cortex Nested Vectored Interrupt Controller - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto -@author @htmlonly © @endhtmlonly 2012 Fergus Noble - -@date 18 August 2012 - -Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults, -systicks etc.) and varying numbers of implementation defined interrupts -(typically peripherial interrupts and DMA). - -@see Cortex-M3 Devices Generic User Guide -@see STM32F10xxx Cortex-M3 programming manual - -LGPL License Terms @ref lgpl_license + * + * @ingroup CM3_files + * + * @brief libopencm3 Cortex Nested Vectored Interrupt Controller + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2010 Thomas Otto + * @author @htmlonly © @endhtmlonly 2012 Fergus Noble + * + * + * @date 18 August 2012 + * + * Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults, + * systicks etc.) and varying numbers of implementation defined interrupts + * (typically peripherial interrupts and DMA). + * + * @see Cortex-M3 Devices Generic User Guide + * @see STM32F10xxx Cortex-M3 programming manual + * + * LGPL License Terms @ref lgpl_license */ /**@{*/ @@ -47,11 +48,11 @@ LGPL License Terms @ref lgpl_license /*---------------------------------------------------------------------------*/ /** @brief NVIC Enable Interrupt - -Enables a user interrupt. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -*/ + * + * Enables a user interrupt. + * + * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + */ void nvic_enable_irq(uint8_t irqn) { @@ -60,11 +61,11 @@ void nvic_enable_irq(uint8_t irqn) /*---------------------------------------------------------------------------*/ /** @brief NVIC Disable Interrupt - -Disables a user interrupt. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -*/ + * + * Disables a user interrupt. + * + * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + */ void nvic_disable_irq(uint8_t irqn) { @@ -73,12 +74,12 @@ void nvic_disable_irq(uint8_t irqn) /*---------------------------------------------------------------------------*/ /** @brief NVIC Return Pending Interrupt - -True if the interrupt has occurred and is waiting for service. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -@return Boolean. Interrupt pending. -*/ + * + * True if the interrupt has occurred and is waiting for service. + * + * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @return Boolean. Interrupt pending. + */ uint8_t nvic_get_pending_irq(uint8_t irqn) { @@ -87,12 +88,12 @@ uint8_t nvic_get_pending_irq(uint8_t irqn) /*---------------------------------------------------------------------------*/ /** @brief NVIC Set Pending Interrupt - -Force a user interrupt to a pending state. This has no effect if the interrupt -is already pending. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -*/ + * + * Force a user interrupt to a pending state. This has no effect if the + * interrupt is already pending. + * + * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + */ void nvic_set_pending_irq(uint8_t irqn) { @@ -101,38 +102,26 @@ void nvic_set_pending_irq(uint8_t irqn) /*---------------------------------------------------------------------------*/ /** @brief NVIC Clear Pending Interrupt - -Force remove a user interrupt from a pending state. This has no effect if the -interrupt is actively being serviced. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -*/ + * + * Force remove a user interrupt from a pending state. This has no effect if + * the interrupt is actively being serviced. + * + * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + */ void nvic_clear_pending_irq(uint8_t irqn) { NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); } -/*---------------------------------------------------------------------------*/ -/** @brief NVIC Return Active Interrupt -Interrupt has occurred and is currently being serviced. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -@return Boolean. Interrupt active. -*/ - -uint8_t nvic_get_active_irq(uint8_t irqn) -{ - return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; -} /*---------------------------------------------------------------------------*/ /** @brief NVIC Return Enabled Interrupt - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -@return Boolean. Interrupt enabled. -*/ + * + * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @return Boolean. Interrupt enabled. + */ uint8_t nvic_get_irq_enabled(uint8_t irqn) { @@ -141,16 +130,24 @@ uint8_t nvic_get_irq_enabled(uint8_t irqn) /*---------------------------------------------------------------------------*/ /** @brief NVIC Set Interrupt Priority - -There are 16 priority levels only, given by the upper four bits of the priority -byte, as required by ARM standards. The priority levels are interpreted -according to the pre-emptive priority grouping set in the SCB Application -Interrupt and Reset Control Register (SCB_AIRCR), as done in @ref -scb_set_priority_grouping. - -@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint -@param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of 16) -*/ + * + * CM3, CM4: + * + * There are 16 priority levels only, given by the upper four bits of the + * priority byte, as required by ARM standards. The priority levels are + * interpreted according to the pre-emptive priority grouping set in the + * SCB Application Interrupt and Reset Control Register (SCB_AIRCR), as done + * in @ref scb_set_priority_grouping. + * + * CM0: + * + * There are 4 priority levels only, given by the upper two bits of the + * priority byte, as required by ARM standards. No grouping available. + * + * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of + * 16) + */ void nvic_set_priority(uint8_t irqn, uint8_t priority) { @@ -166,15 +163,31 @@ void nvic_set_priority(uint8_t irqn, uint8_t priority) } } +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) +/*---------------------------------------------------------------------------*/ +/** @brief NVIC Return Active Interrupt + * + * Interrupt has occurred and is currently being serviced. + * + * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @return Boolean. Interrupt active. + */ + +uint8_t nvic_get_active_irq(uint8_t irqn) +{ + return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; +} + /*---------------------------------------------------------------------------*/ /** @brief NVIC Software Trigger Interrupt - -Generate an interrupt from software. This has no effect for unprivileged access -unless the privilege level has been elevated through the System Control -Registers. - -@param[in] irqn Unsigned int16. Interrupt number (0 ... 239) -*/ + * + * Generate an interrupt from software. This has no effect for unprivileged + * access unless the privilege level has been elevated through the System + * Control Registers. + * + * @param[in] irqn Unsigned int16. Interrupt number (0 ... 239) + */ void nvic_generate_software_interrupt(uint16_t irqn) { @@ -182,4 +195,5 @@ void nvic_generate_software_interrupt(uint16_t irqn) NVIC_STIR |= irqn; } } +#endif /**@}*/ diff --git a/lib/cm3/scb.c b/lib/cm3/scb.c index 107e35b6..e51e1450 100644 --- a/lib/cm3/scb.c +++ b/lib/cm3/scb.c @@ -21,12 +21,15 @@ #include +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) void scb_reset_core(void) { SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; while (1); } +#endif void scb_reset_system(void) { @@ -35,7 +38,10 @@ void scb_reset_system(void) while (1); } +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) void scb_set_priority_grouping(uint32_t prigroup) { SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; } +#endif diff --git a/lib/cm3/sync.c b/lib/cm3/sync.c index 88fe1114..7ddd24db 100644 --- a/lib/cm3/sync.c +++ b/lib/cm3/sync.c @@ -19,8 +19,15 @@ #include -#if defined(LPC43XX_M0) -#warning "Currently sync is not supported on Cortex-M0" +/* DMB is supported on CM0 */ +void __dmb() +{ + __asm__ volatile ("dmb"); +} + +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_6M__) +#warning "sync not supported on ARMv6-M arch" #else uint32_t __ldrex(volatile uint32_t *addr) @@ -38,11 +45,6 @@ uint32_t __strex(uint32_t val, volatile uint32_t *addr) return res; } -void __dmb() -{ - __asm__ volatile ("dmb"); -} - void mutex_lock(mutex_t *m) { uint32_t status = 0; diff --git a/lib/cm3/systick.c b/lib/cm3/systick.c index 1f6f4062..d2bcb7a5 100644 --- a/lib/cm3/systick.c +++ b/lib/cm3/systick.c @@ -18,23 +18,23 @@ * along with this library. If not, see . */ /** @defgroup CM3_systick_file SysTick - -@ingroup CM3_files - -@brief libopencm3 Cortex System Tick Timer - -@version 1.0.0 - -@author @htmlonly © @endhtmlonly 2010 Thomas Otto - -@date 19 August 2012 - -This library supports the System Tick timer in ARM Cortex Microcontrollers. - -The System Tick timer is part of the ARM Cortex core. It is a 24 bit -down counter that can be configured with an automatical reload value. - -LGPL License Terms @ref lgpl_license + * + * @ingroup CM3_files + * + * @brief libopencm3 Cortex System Tick Timer + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2010 Thomas Otto + * + * @date 19 August 2012 + * + * This library supports the System Tick timer in ARM Cortex Microcontrollers. + * + * The System Tick timer is part of the ARM Cortex core. It is a 24 bit + * down counter that can be configured with an automatical reload value. + * + * LGPL License Terms @ref lgpl_license */ /**@{*/ @@ -42,121 +42,117 @@ LGPL License Terms @ref lgpl_license /*---------------------------------------------------------------------------*/ /** @brief SysTick Set the Automatic Reload Value. - -The counter is set to the reload value when the counter starts and after it -reaches zero. - -@param[in] value uint32_t. 24 bit reload value. -*/ + * + * The counter is set to the reload value when the counter starts and after it + * reaches zero. + * + * @param[in] value uint32_t. 24 bit reload value. + */ void systick_set_reload(uint32_t value) { - STK_LOAD = (value & 0x00FFFFFF); + STK_RVR = (value & STK_RVR_RELOAD); } /*---------------------------------------------------------------------------*/ /** @brief SysTick Read the Automatic Reload Value. - -@returns 24 bit reload value as uint32_t. -*/ + * + * @returns 24 bit reload value as uint32_t. + */ uint32_t systick_get_reload(void) { - return STK_LOAD & 0x00FFFFFF; + return STK_RVR & STK_RVR_RELOAD; } /*---------------------------------------------------------------------------*/ /** @brief Get the current SysTick counter value. - -@returns 24 bit current value as uint32_t. -*/ + * + * @returns 24 bit current value as uint32_t. + */ uint32_t systick_get_value(void) { - return STK_VAL & 0x00FFFFFF; + return STK_CVR & STK_CVR_CURRENT; } /*---------------------------------------------------------------------------*/ /** @brief Set the SysTick Clock Source. - -The clock source can be either the AHB clock or the same clock divided by 8. - -@param[in] clocksource uint8_t. Clock source from @ref systick_clksource. -*/ + * + * The clock source can be either the AHB clock or the same clock divided by 8. + * + * @param[in] clocksource uint8_t. Clock source from @ref systick_clksource. + */ void systick_set_clocksource(uint8_t clocksource) { if (clocksource < 2) { - STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); + STK_CSR |= clocksource; } } /*---------------------------------------------------------------------------*/ /** @brief Enable SysTick Interrupt. - -*/ + * + */ void systick_interrupt_enable(void) { - STK_CTRL |= STK_CTRL_TICKINT; + STK_CSR |= STK_CSR_TICKINT; } /*---------------------------------------------------------------------------*/ /** @brief Disable SysTick Interrupt. - -*/ + * + */ void systick_interrupt_disable(void) { - STK_CTRL &= ~STK_CTRL_TICKINT; + STK_CSR &= ~STK_CSR_TICKINT; } /*---------------------------------------------------------------------------*/ /** @brief Enable SysTick Counter. - -*/ + * + */ void systick_counter_enable(void) { - STK_CTRL |= STK_CTRL_ENABLE; + STK_CSR |= STK_CSR_ENABLE; } /*---------------------------------------------------------------------------*/ /** @brief Disable SysTick Counter. - -*/ + * + */ void systick_counter_disable(void) { - STK_CTRL &= ~STK_CTRL_ENABLE; + STK_CSR &= ~STK_CSR_ENABLE; } /*---------------------------------------------------------------------------*/ /** @brief SysTick Read the Counter Flag. - -The count flag is set when the timer count becomes zero, and is cleared when -the flag is read. - -@returns Boolean if flag set. -*/ + * + * The count flag is set when the timer count becomes zero, and is cleared when + * the flag is read. + * + * @returns Boolean if flag set. + */ uint8_t systick_get_countflag(void) { - if (STK_CTRL & STK_CTRL_COUNTFLAG) { - return 1; - } else { - return 0; - } + return (STK_CSR & STK_CSR_COUNTFLAG) ? 1 : 0; } /*---------------------------------------------------------------------------*/ /** @brief SysTick Get Calibration Value - -@returns Current calibration value -*/ + * + * @returns Current calibration value + */ uint32_t systick_get_calib(void) { - return STK_CALIB & 0x00FFFFFF; + return STK_CALIB & STK_CALIB_TENMS; } /**@}*/ diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index 3bc7f66b..f73402a9 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -42,10 +42,15 @@ vector_table_t vector_table = { .reset = reset_handler, .nmi = nmi_handler, .hard_fault = hard_fault_handler, + +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) .memory_manage_fault = mem_manage_handler, .bus_fault = bus_fault_handler, .usage_fault = usage_fault_handler, .debug_monitor = debug_monitor_handler, +#endif + .sv_call = sv_call_handler, .pend_sv = pend_sv_handler, .systick = sys_tick_handler, @@ -102,10 +107,15 @@ void null_handler(void) #pragma weak nmi_handler = null_handler #pragma weak hard_fault_handler = blocking_handler +#pragma weak sv_call_handler = null_handler +#pragma weak pend_sv_handler = null_handler +#pragma weak sys_tick_handler = null_handler + +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) #pragma weak mem_manage_handler = blocking_handler #pragma weak bus_fault_handler = blocking_handler #pragma weak usage_fault_handler = blocking_handler -#pragma weak sv_call_handler = null_handler #pragma weak debug_monitor_handler = null_handler -#pragma weak pend_sv_handler = null_handler -#pragma weak sys_tick_handler = null_handler +#endif +