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Clean up whitespace in stm32f2 RCC

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Also make RCC IO defines consistent with stm32f1.
This commit is contained in:
Stephen Caudle 2011-10-28 16:21:43 -04:00
parent eb47f0cfc0
commit e2ed7824cf
1 changed files with 198 additions and 198 deletions
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68
include/libopencm3/stm32/f2/rcc.h
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@ -34,31 +34,31 @@
#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) #define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10)
#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) #define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14)
#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) #define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18)
/* RCC_BASE + 0x1C Reserved */ /* RCC_BASE + 0x1c Reserved */
#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) #define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20)
#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) #define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24)
/* RCC_BASE + 0x28 Reserved */ /* RCC_BASE + 0x28 Reserved */
/* RCC_BASE + 0x2C Reserved */ /* RCC_BASE + 0x2c Reserved */
#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) #define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30)
#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) #define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34)
#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) #define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38)
/* RCC_BASE + 0x3C Reserved */ /* RCC_BASE + 0x3c Reserved */
#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) #define RCC_APB1ENR MMIO32(RCC_BASE + 0x40)
#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) #define RCC_APB2ENR MMIO32(RCC_BASE + 0x44)
/* RCC_BASE + 0x48 Reserved */ /* RCC_BASE + 0x48 Reserved */
/* RCC_BASE + 0x4C Reserved */ /* RCC_BASE + 0x4c Reserved */
#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) #define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50)
#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) #define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54)
#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) #define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58)
/* RCC_BASE + 0x5C Reserved */ /* RCC_BASE + 0x5c Reserved */
#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) #define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60)
#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) #define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64)
/* RCC_BASE + 0x68 Reserved */ /* RCC_BASE + 0x68 Reserved */
/* RCC_BASE + 0x6C Reserved */ /* RCC_BASE + 0x6c Reserved */
#define RCC_BDCR MMIO32(RCC_BASE + 0x70) #define RCC_BDCR MMIO32(RCC_BASE + 0x70)
#define RCC_CSR MMIO32(RCC_BASE + 0x74) #define RCC_CSR MMIO32(RCC_BASE + 0x74)
/* RCC_BASE + 0x78 Reserved */ /* RCC_BASE + 0x78 Reserved */
/* RCC_BASE + 0x7C Reserved */ /* RCC_BASE + 0x7c Reserved */
#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) #define RCC_SSCGR MMIO32(RCC_BASE + 0x80)
#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) #define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84)
@ -192,15 +192,15 @@
#define RCC_AHB1RSTR_DMA2RST (1 << 22) #define RCC_AHB1RSTR_DMA2RST (1 << 22)
#define RCC_AHB1RSTR_DMA1RST (1 << 21) #define RCC_AHB1RSTR_DMA1RST (1 << 21)
#define RCC_AHB1RSTR_CRCRST (1 << 12) #define RCC_AHB1RSTR_CRCRST (1 << 12)
#define RCC_AHB1RSTR_GPIOIRST (1 << 8) #define RCC_AHB1RSTR_IOPIRST (1 << 8)
#define RCC_AHB1RSTR_GPIOHRST (1 << 7) #define RCC_AHB1RSTR_IOPHRST (1 << 7)
#define RCC_AHB1RSTR_GPIOGRST (1 << 6) #define RCC_AHB1RSTR_IOPGRST (1 << 6)
#define RCC_AHB1RSTR_GPIOFRST (1 << 5) #define RCC_AHB1RSTR_IOPFRST (1 << 5)
#define RCC_AHB1RSTR_GPIOERST (1 << 4) #define RCC_AHB1RSTR_IOPERST (1 << 4)
#define RCC_AHB1RSTR_GPIODRST (1 << 3) #define RCC_AHB1RSTR_IOPDRST (1 << 3)
#define RCC_AHB1RSTR_GPIOCRST (1 << 2) #define RCC_AHB1RSTR_IOPCRST (1 << 2)
#define RCC_AHB1RSTR_GPIOBRST (1 << 1) #define RCC_AHB1RSTR_IOPBRST (1 << 1)
#define RCC_AHB1RSTR_GPIOARST (1 << 0) #define RCC_AHB1RSTR_IOPARST (1 << 0)
/* --- RCC_AHB2RSTR values ------------------------------------------------- */ /* --- RCC_AHB2RSTR values ------------------------------------------------- */
@ -266,15 +266,15 @@
#define RCC_AHB1ENR_DMA1EN (1 << 21) #define RCC_AHB1ENR_DMA1EN (1 << 21)
#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) #define RCC_AHB1ENR_BKPSRAMEN (1 << 18)
#define RCC_AHB1ENR_CRCEN (1 << 12) #define RCC_AHB1ENR_CRCEN (1 << 12)
#define RCC_AHB1ENR_GPIOIEN (1 << 8) #define RCC_AHB1ENR_IOPIEN (1 << 8)
#define RCC_AHB1ENR_GPIOHEN (1 << 7) #define RCC_AHB1ENR_IOPHEN (1 << 7)
#define RCC_AHB1ENR_GPIOGEN (1 << 6) #define RCC_AHB1ENR_IOPGEN (1 << 6)
#define RCC_AHB1ENR_GPIOFEN (1 << 5) #define RCC_AHB1ENR_IOPFEN (1 << 5)
#define RCC_AHB1ENR_GPIOEEN (1 << 4) #define RCC_AHB1ENR_IOPEEN (1 << 4)
#define RCC_AHB1ENR_GPIODEN (1 << 3) #define RCC_AHB1ENR_IOPDEN (1 << 3)
#define RCC_AHB1ENR_GPIOCEN (1 << 2) #define RCC_AHB1ENR_IOPCEN (1 << 2)
#define RCC_AHB1ENR_GPIOBEN (1 << 1) #define RCC_AHB1ENR_IOPBEN (1 << 1)
#define RCC_AHB1ENR_GPIOAEN (1 << 0) #define RCC_AHB1ENR_IOPAEN (1 << 0)
/* --- RCC_AHB2ENR values ------------------------------------------------- */ /* --- RCC_AHB2ENR values ------------------------------------------------- */
@ -345,15 +345,15 @@
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) #define RCC_AHB1LPENR_SRAM1LPEN (1 << 16)
#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) #define RCC_AHB1LPENR_FLITFLPEN (1 << 15)
#define RCC_AHB1LPENR_CRCLPEN (1 << 12) #define RCC_AHB1LPENR_CRCLPEN (1 << 12)
#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) #define RCC_AHB1LPENR_IOPILPEN (1 << 8)
#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) #define RCC_AHB1LPENR_IOPHLPEN (1 << 7)
#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) #define RCC_AHB1LPENR_IOPGLPEN (1 << 6)
#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) #define RCC_AHB1LPENR_IOPFLPEN (1 << 5)
#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) #define RCC_AHB1LPENR_IOPELPEN (1 << 4)
#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) #define RCC_AHB1LPENR_IOPDLPEN (1 << 3)
#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) #define RCC_AHB1LPENR_IOPCLPEN (1 << 2)
#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) #define RCC_AHB1LPENR_IOPBLPEN (1 << 1)
#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) #define RCC_AHB1LPENR_IOPALPEN (1 << 0)
/* --- RCC_AHB2LPENR values ------------------------------------------------- */ /* --- RCC_AHB2LPENR values ------------------------------------------------- */