diff --git a/tests/gadget-zero/Makefile.stm32l053disco b/tests/gadget-zero/Makefile.stm32l053disco
new file mode 100644
index 00000000..8af7f139
--- /dev/null
+++ b/tests/gadget-zero/Makefile.stm32l053disco
@@ -0,0 +1,43 @@
+##
+## This file is part of the libopencm3 project.
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library.  If not, see <http://www.gnu.org/licenses/>.
+##
+
+BOARD = stm32l053disco
+PROJECT = usb-gadget0-$(BOARD)
+BUILD_DIR = bin-$(BOARD)
+
+SHARED_DIR = ../shared
+
+CFILES = main-$(BOARD).c
+CFILES += usb-gadget0.c
+
+VPATH += $(SHARED_DIR)
+
+INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR))
+
+OPENCM3_DIR=../..
+
+### This section can go to an arch shared rules eventually...
+LDSCRIPT = ../../lib/stm32/l0/stm32l0xx8.ld
+OPENCM3_LIB = opencm3_stm32l0
+OPENCM3_DEFS = -DSTM32L0
+#FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
+ARCH_FLAGS = -mthumb -mcpu=cortex-m0plus $(FP_FLAGS)
+#OOCD_INTERFACE = stlink-v2-1
+#OOCD_TARGET = stm32l0
+OOCD_FILE = openocd.stm32l053disco.cfg
+
+include ../rules.mk
diff --git a/tests/gadget-zero/main-stm32l053disco.c b/tests/gadget-zero/main-stm32l053disco.c
new file mode 100644
index 00000000..480775af
--- /dev/null
+++ b/tests/gadget-zero/main-stm32l053disco.c
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/cm3/nvic.h>
+#include <libopencm3/stm32/crs.h>
+#include <libopencm3/stm32/gpio.h>
+#include <libopencm3/stm32/rcc.h>
+#include <libopencm3/stm32/syscfg.h>
+
+#include <stdio.h>
+#include "usb-gadget0.h"
+
+// no trace on cm0 #define ER_DEBUG
+#ifdef ER_DEBUG
+#define ER_DPRINTF(fmt, ...) \
+    do { printf(fmt, ## __VA_ARGS__); } while (0)
+#else
+#define ER_DPRINTF(fmt, ...) \
+    do { } while (0)
+#endif
+
+#include "trace.h"
+void trace_send_blocking8(int stimulus_port, char c) {
+	(void)stimulus_port;
+	(void)c;
+}
+
+#if 0
+void rcc_clock_setup_in_hsi16_out_32mhz() {
+	rcc_osc_on(HSI16);
+
+	rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
+	rcc_set_ppre1(RCC_CFGR_PPRE1_NODIV);
+	rcc_set_ppre2(RCC_CFGR_PPRE2_NODIV);
+	rcc_wait_for_osc_ready(HSI16);
+
+	rcc_peripheral_enable_clock(RCC_PWR);
+	pwr_set_vos_scale(RANGE1);
+	
+	/* Flash wait states too.  */
+	
+/*
+ * 	rcc_set_pll_configuration(clock->pll_source, clock->pll_mul,
+				  clock->pll_div);
+*/
+	/* Enable PLL oscillator and wait for it to stabilize. */
+	rcc_osc_on(PLL);
+	rcc_wait_for_osc_ready(PLL);
+	
+	rcc_set_sysclk_source(PLL);
+	rcc_apb1_frequency = 32000000;
+	rcc_ahb_frequency = 32000000;
+	
+	
+	
+}
+#endif
+
+
+int main(void)
+{
+	/* LED for boot progress */
+        rcc_periph_clock_enable(RCC_GPIOA);
+        gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO5);
+	gpio_set(GPIOA, GPIO5);
+
+	/* jump up to 16mhz, leave PLL setup for later. */
+	rcc_osc_on(HSI16);
+	rcc_wait_for_osc_ready(HSI16);
+	rcc_set_sysclk_source(HSI16);
+
+	/* HSI48 needs the vrefint turned on */
+	rcc_periph_clock_enable(RCC_SYSCFG);
+	SYSCFG_CFGR3 |= SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT;
+	while(!(SYSCFG_CFGR3 & SYSCFG_CFGR3_REF_HSI48_RDYF));
+	
+	/* For USB, but can't use HSI48 as a sysclock on L0 */
+	crs_autotrim_usb_enable();
+	rcc_set_hsi48_source_rc48();
+
+	rcc_osc_on(HSI48);
+	rcc_wait_for_osc_ready(HSI48);
+
+	usbd_device *usbd_dev = gadget0_init(&st_usbfs_v2_usb_driver, "stm32l053disco");
+
+	ER_DPRINTF("bootup complete\n");
+	gpio_clear(GPIOA, GPIO5);
+	while (1) {
+		usbd_poll(usbd_dev);
+	}
+
+}
+
diff --git a/tests/gadget-zero/openocd.stm32l053disco.cfg b/tests/gadget-zero/openocd.stm32l053disco.cfg
new file mode 100644
index 00000000..80fc61c2
--- /dev/null
+++ b/tests/gadget-zero/openocd.stm32l053disco.cfg
@@ -0,0 +1,14 @@
+source [find interface/stlink-v2-1.cfg]
+set WORKAREASIZE 0x1000
+source [find target/stm32l0.cfg]
+
+# serial of my l053 disco board.
+hla_serial "0670FF484849785087085514"
+
+# no trace on cm0
+#tpiu config internal swodump.stm32f4disco.log uart off 168000000
+
+# Uncomment to reset on connect, for grabbing under WFI et al
+reset_config srst_only srst_nogate
+# reset_config srst_only srst_nogate connect_assert_srst
+
diff --git a/tests/gadget-zero/test_gadget0.py b/tests/gadget-zero/test_gadget0.py
index 1b579662..ddeff532 100644
--- a/tests/gadget-zero/test_gadget0.py
+++ b/tests/gadget-zero/test_gadget0.py
@@ -10,6 +10,7 @@ DUT_SERIAL = "stm32f4disco"
 #DUT_SERIAL = "stm32f103-generic"
 #DUT_SERIAL = "stm32l1-generic"
 #DUT_SERIAL = "stm32f072disco"
+#DUT_SERIAL = "stm32l053disco"
 
 class find_by_serial(object):
     def __init__(self, serial):