I2C to common area
F2/4 has now I2C3 included
This commit is contained in:
Ken Sarkies
parent
312d887825
commit
e831f4db51
383
include/libopencm3/stm32/common/i2c_common_all.h
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383
include/libopencm3/stm32/common/i2c_common_all.h
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/** @addtogroup i2c_defines */
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H */
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#ifndef LIBOPENCM3_I2C_COMMON_ALL_H
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#define LIBOPENCM3_I2C_COMMON_ALL_H
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#include <libopencm3/cm3/common.h>
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/**@{*/
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/* --- Convenience macros -------------------------------------------------- */
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/* I2C register base adresses (for convenience) */
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/****************************************************************************/
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/** @defgroup i2c_reg_base I2C register base address
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@ingroup i2c_defines
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@{*/
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#define I2C1 I2C1_BASE
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#define I2C2 I2C2_BASE
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/**@}*/
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/* --- I2C registers ------------------------------------------------------- */
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/* Control register 1 (I2Cx_CR1) */
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#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
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#define I2C1_CR1 I2C_CR1(I2C1)
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#define I2C2_CR1 I2C_CR1(I2C2)
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/* Control register 2 (I2Cx_CR2) */
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#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
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#define I2C1_CR2 I2C_CR2(I2C1)
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#define I2C2_CR2 I2C_CR2(I2C2)
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/* Own address register 1 (I2Cx_OAR1) */
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#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
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#define I2C1_OAR1 I2C_OAR1(I2C1)
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#define I2C2_OAR1 I2C_OAR1(I2C2)
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/* Own address register 2 (I2Cx_OAR2) */
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#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
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#define I2C1_OAR2 I2C_OAR2(I2C1)
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#define I2C2_OAR2 I2C_OAR2(I2C2)
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/* Data register (I2Cx_DR) */
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#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10)
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#define I2C1_DR I2C_DR(I2C1)
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#define I2C2_DR I2C_DR(I2C2)
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/* Status register 1 (I2Cx_SR1) */
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#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14)
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#define I2C1_SR1 I2C_SR1(I2C1)
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#define I2C2_SR1 I2C_SR1(I2C2)
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/* Status register 2 (I2Cx_SR2) */
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#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18)
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#define I2C1_SR2 I2C_SR2(I2C1)
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#define I2C2_SR2 I2C_SR2(I2C2)
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/* Clock control register (I2Cx_CCR) */
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#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c)
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#define I2C1_CCR I2C_CCR(I2C1)
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#define I2C2_CCR I2C_CCR(I2C2)
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/* TRISE register (I2Cx_CCR) */
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#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20)
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#define I2C1_TRISE I2C_TRISE(I2C1)
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#define I2C2_TRISE I2C_TRISE(I2C2)
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/* --- I2Cx_CR1 values ----------------------------------------------------- */
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/* SWRST: Software reset */
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#define I2C_CR1_SWRST (1 << 15)
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/* Note: Bit 14 is reserved, and forced to 0 by hardware. */
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/* ALERT: SMBus alert */
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#define I2C_CR1_ALERT (1 << 13)
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/* PEC: Packet error checking */
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#define I2C_CR1_PEC (1 << 12)
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/* POS: Acknowledge / PEC postition */
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#define I2C_CR1_POS (1 << 11)
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/* ACK: Acknowledge enable */
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#define I2C_CR1_ACK (1 << 10)
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/* STOP: STOP generation */
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#define I2C_CR1_STOP (1 << 9)
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/* START: START generation */
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#define I2C_CR1_START (1 << 8)
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/* NOSTRETCH: Clock stretching disable (slave mode) */
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#define I2C_CR1_NOSTRETCH (1 << 7)
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/* ENGC: General call enable */
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#define I2C_CR1_ENGC (1 << 6)
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/* ENPEC: Enable PEC */
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#define I2C_CR1_ENPEC (1 << 5)
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/* ENARP: ARP enable */
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#define I2C_CR1_ENARP (1 << 4)
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/* SMBTYPE: SMBus type */
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#define I2C_CR1_SMBTYPE (1 << 3)
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/* Note: Bit 2 is reserved, and forced to 0 by hardware. */
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/* SMBUS: SMBus mode */
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#define I2C_CR1_SMBUS (1 << 1)
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/* PE: Peripheral enable */
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#define I2C_CR1_PE (1 << 0)
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/* --- I2Cx_CR2 values ----------------------------------------------------- */
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/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */
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/* LAST: DMA last transfer */
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#define I2C_CR2_LAST (1 << 12)
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/* DMAEN: DMA requests enable */
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#define I2C_CR2_DMAEN (1 << 11)
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/* ITBUFEN: Buffer interrupt enable */
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#define I2C_CR2_ITBUFEN (1 << 10)
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/* ITEVTEN: Event interrupt enable */
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#define I2C_CR2_ITEVTEN (1 << 9)
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/* ITERREN: Error interrupt enable */
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#define I2C_CR2_ITERREN (1 << 8)
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/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
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/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
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/****************************************************************************/
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/** @defgroup i2c_clock I2C clock frequency settings
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@ingroup i2c_defines
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@{*/
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#define I2C_CR2_FREQ_2MHZ 0x02
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#define I2C_CR2_FREQ_3MHZ 0x03
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#define I2C_CR2_FREQ_4MHZ 0x04
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#define I2C_CR2_FREQ_5MHZ 0x05
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#define I2C_CR2_FREQ_6MHZ 0x06
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#define I2C_CR2_FREQ_7MHZ 0x07
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#define I2C_CR2_FREQ_8MHZ 0x08
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#define I2C_CR2_FREQ_9MHZ 0x09
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#define I2C_CR2_FREQ_10MHZ 0x0a
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#define I2C_CR2_FREQ_11MHZ 0x0b
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#define I2C_CR2_FREQ_12MHZ 0x0c
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#define I2C_CR2_FREQ_13MHZ 0x0d
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#define I2C_CR2_FREQ_14MHZ 0x0e
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#define I2C_CR2_FREQ_15MHZ 0x0f
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#define I2C_CR2_FREQ_16MHZ 0x10
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#define I2C_CR2_FREQ_17MHZ 0x11
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#define I2C_CR2_FREQ_18MHZ 0x12
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#define I2C_CR2_FREQ_19MHZ 0x13
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#define I2C_CR2_FREQ_20MHZ 0x14
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#define I2C_CR2_FREQ_21MHZ 0x15
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#define I2C_CR2_FREQ_22MHZ 0x16
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#define I2C_CR2_FREQ_23MHZ 0x17
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#define I2C_CR2_FREQ_24MHZ 0x18
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#define I2C_CR2_FREQ_25MHZ 0x19
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#define I2C_CR2_FREQ_26MHZ 0x1a
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#define I2C_CR2_FREQ_27MHZ 0x1b
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#define I2C_CR2_FREQ_28MHZ 0x1c
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#define I2C_CR2_FREQ_29MHZ 0x1d
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#define I2C_CR2_FREQ_30MHZ 0x1e
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#define I2C_CR2_FREQ_31MHZ 0x1f
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#define I2C_CR2_FREQ_32MHZ 0x20
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#define I2C_CR2_FREQ_33MHZ 0x21
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#define I2C_CR2_FREQ_34MHZ 0x22
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#define I2C_CR2_FREQ_35MHZ 0x23
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#define I2C_CR2_FREQ_36MHZ 0x24
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/**@}*/
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/* --- I2Cx_OAR1 values ---------------------------------------------------- */
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/* ADDMODE: Addressing mode (slave mode) */
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#define I2C_OAR1_ADDMODE (1 << 15)
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#define I2C_OAR1_ADDMODE_7BIT 0
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#define I2C_OAR1_ADDMODE_10BIT 1
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/* Note: Bit 14 should always be kept at 1 by software! */
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/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */
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/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */
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/* --- I2Cx_OAR2 values ---------------------------------------------------- */
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/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
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/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */
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/* ENDUAL: Dual addressing mode enable */
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#define I2C_OAR2_ENDUAL (1 << 0)
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/* --- I2Cx_DR values ------------------------------------------------------ */
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/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
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/* DR[7:0] 8-bit data register */
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/* --- I2Cx_SR1 values ----------------------------------------------------- */
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/* SMBALERT: SMBus alert */
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#define I2C_SR1_SMBALERT (1 << 15)
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/* TIMEOUT: Timeout or Tlow Error */
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#define I2C_SR1_TIMEOUT (1 << 14)
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/* Note: Bit 13 is reserved, and forced to 0 by hardware. */
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/* PECERR: PEC Error in reception */
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#define I2C_SR1_PECERR (1 << 12)
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/* OVR: Overrun/Underrun */
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#define I2C_SR1_OVR (1 << 11)
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/* AF: Acknowledge failure */
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#define I2C_SR1_AF (1 << 10)
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/* ARLO: Arbitration lost (master mode) */
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#define I2C_SR1_ARLO (1 << 9)
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/* BERR: Bus error */
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#define I2C_SR1_BERR (1 << 8)
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/* TxE: Data register empty (transmitters) */
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#define I2C_SR1_TxE (1 << 7)
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/* RxNE: Data register not empty (receivers) */
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#define I2C_SR1_RxNE (1 << 6)
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/* Note: Bit 5 is reserved, and forced to 0 by hardware. */
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/* STOPF: STOP detection (slave mode) */
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#define I2C_SR1_STOPF (1 << 4)
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/* ADD10: 10-bit header sent (master mode) */
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#define I2C_SR1_ADD10 (1 << 3)
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/* BTF: Byte transfer finished */
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#define I2C_SR1_BTF (1 << 2)
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/* ADDR: Address sent (master mode) / address matched (slave mode) */
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#define I2C_SR1_ADDR (1 << 1)
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/* SB: Start bit (master mode) */
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#define I2C_SR1_SB (1 << 0)
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/* --- I2Cx_SR2 values ----------------------------------------------------- */
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/* Bits [15:8]: PEC[7:0]: Packet error checking register */
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/* DUALF: Dual flag (slave mode) */
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#define I2C_SR2_DUALF (1 << 7)
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/* SMBHOST: SMBus host header (slave mode) */
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#define I2C_SR2_SMBHOST (1 << 6)
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/* SMBDEFAULT: SMBus device default address (slave mode) */
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#define I2C_SR2_SMBDEFAULT (1 << 5)
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/* GENCALL: General call address (slave mode) */
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#define I2C_SR2_GENCALL (1 << 4)
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/* Note: Bit 3 is reserved, and forced to 0 by hardware. */
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/* TRA: Transmitter / receiver */
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#define I2C_SR2_TRA (1 << 2)
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/* BUSY: Bus busy */
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#define I2C_SR2_BUSY (1 << 1)
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/* MSL: Master / slave */
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#define I2C_SR2_MSL (1 << 0)
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/* --- I2Cx_CCR values ----------------------------------------------------- */
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/* F/S: I2C Master mode selection (fast / standard) */
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#define I2C_CCR_FS (1 << 15)
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/* DUTY: Fast Mode Duty Cycle */
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/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles
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@ingroup i2c_defines
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@{*/
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#define I2C_CCR_DUTY (1 << 14)
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#define I2C_CCR_DUTY_DIV2 0
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#define I2C_CCR_DUTY_16_DIV_9 1
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/**@}*/
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/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
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/*
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* Bits [11:0]:
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* CCR[11:0]: Clock control register in Fast/Standard mode (master mode)
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*/
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/* --- I2Cx_TRISE values --------------------------------------------------- */
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/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
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/*
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* Bits [5:0]:
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* TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
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*/
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/* --- I2C const definitions ----------------------------------------------- */
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/****************************************************************************/
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/** @defgroup i2c_rw I2C Read/Write bit
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@ingroup i2c_defines
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@{*/
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#define I2C_WRITE 0
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#define I2C_READ 1
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/**@}*/
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/* --- I2C funtion prototypes----------------------------------------------- */
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BEGIN_DECLS
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void i2c_reset(u32 i2c);
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void i2c_peripheral_enable(u32 i2c);
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void i2c_peripheral_disable(u32 i2c);
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void i2c_send_start(u32 i2c);
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void i2c_send_stop(u32 i2c);
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void i2c_clear_stop(u32 i2c);
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void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
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void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
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void i2c_set_fast_mode(u32 i2c);
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void i2c_set_standard_mode(u32 i2c);
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void i2c_set_clock_frequency(u32 i2c, u8 freq);
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void i2c_set_ccr(u32 i2c, u16 freq);
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void i2c_set_trise(u32 i2c, u16 trise);
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void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
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void i2c_send_data(u32 i2c, u8 data);
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uint8_t i2c_get_data(u32 i2c);
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void i2c_enable_interrupt(u32 i2c, u32 interrupt);
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void i2c_disable_interrupt(u32 i2c, u32 interrupt);
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void i2c_enable_ack(u32 i2c);
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void i2c_disable_ack(u32 i2c);
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void i2c_nack_next(u32 i2c);
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void i2c_nack_current(u32 i2c);
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void i2c_set_dutycycle(u32 i2c, u32 dutycycle);
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void i2c_enable_dma(u32 i2c);
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void i2c_disable_dma(u32 i2c);
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void i2c_set_dma_last_transfer(u32 i2c);
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void i2c_clear_dma_last_transfer(u32 i2c);
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END_DECLS
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#endif
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/**@}*/
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35
include/libopencm3/stm32/common/i2c_common_f24.h
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35
include/libopencm3/stm32/common/i2c_common_f24.h
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/** @addtogroup i2c_defines */
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
|
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* the Free Software Foundation, either version 3 of the License, or
|
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
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*
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* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H */
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#ifndef LIBOPENCM3_I2C_COMMON_F24_H
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#define LIBOPENCM3_I2C_COMMON_F24_H
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#include <libopencm3/stm32/common/i2c_common_all.h>
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/**@{*/
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#define I2C3 I2C3_BASE
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||||
/**@}*/
|
||||
|
||||
#endif
|
||||
41
include/libopencm3/stm32/f1/i2c.h
Normal file
41
include/libopencm3/stm32/f1/i2c.h
Normal file
@ -0,0 +1,41 @@
|
||||
/** @defgroup i2c_defines I2C Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32F1xx I2C </b>
|
||||
|
||||
@ingroup STM32F1xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 12 October 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_I2C_H
|
||||
#define LIBOPENCM3_I2C_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/stm32/common/i2c_common_all.h>
|
||||
|
||||
#endif
|
||||
|
||||
41
include/libopencm3/stm32/f2/i2c.h
Normal file
41
include/libopencm3/stm32/f2/i2c.h
Normal file
@ -0,0 +1,41 @@
|
||||
/** @defgroup i2c_defines I2C Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32F2xx I2C </b>
|
||||
|
||||
@ingroup STM32F2xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 12 October 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_I2C_H
|
||||
#define LIBOPENCM3_I2C_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/stm32/common/i2c_common_f24.h>
|
||||
|
||||
#endif
|
||||
|
||||
41
include/libopencm3/stm32/f4/i2c.h
Normal file
41
include/libopencm3/stm32/f4/i2c.h
Normal file
@ -0,0 +1,41 @@
|
||||
/** @defgroup i2c_defines I2C Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32F4xx I2C </b>
|
||||
|
||||
@ingroup STM32F4xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 12 October 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_I2C_H
|
||||
#define LIBOPENCM3_I2C_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/stm32/common/i2c_common_f24.h>
|
||||
|
||||
#endif
|
||||
|
||||
@ -1,24 +1,8 @@
|
||||
/** @defgroup i2c_defines I2C Defines
|
||||
|
||||
@ingroup STM32F_defines
|
||||
|
||||
@brief <b>libopencm3 Defined Constants and Types for the STM32 I2C </b>
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 12 October 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/* This provides unification of code over STM32F subfamilies */
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
@ -33,364 +17,15 @@ LGPL License Terms @ref lgpl_license
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_I2C_H
|
||||
#define LIBOPENCM3_I2C_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/cm3/common.h>
|
||||
|
||||
/**@{*/
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* I2C register base adresses (for convenience) */
|
||||
/****************************************************************************/
|
||||
/** @defgroup i2c_reg_base I2C register base address
|
||||
@ingroup i2c_defines
|
||||
|
||||
@{*/
|
||||
#define I2C1 I2C1_BASE
|
||||
#define I2C2 I2C2_BASE
|
||||
/**@}*/
|
||||
|
||||
/* --- I2C registers ------------------------------------------------------- */
|
||||
|
||||
/* Control register 1 (I2Cx_CR1) */
|
||||
#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00)
|
||||
#define I2C1_CR1 I2C_CR1(I2C1)
|
||||
#define I2C2_CR1 I2C_CR1(I2C2)
|
||||
|
||||
/* Control register 2 (I2Cx_CR2) */
|
||||
#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04)
|
||||
#define I2C1_CR2 I2C_CR2(I2C1)
|
||||
#define I2C2_CR2 I2C_CR2(I2C2)
|
||||
|
||||
/* Own address register 1 (I2Cx_OAR1) */
|
||||
#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08)
|
||||
#define I2C1_OAR1 I2C_OAR1(I2C1)
|
||||
#define I2C2_OAR1 I2C_OAR1(I2C2)
|
||||
|
||||
/* Own address register 2 (I2Cx_OAR2) */
|
||||
#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c)
|
||||
#define I2C1_OAR2 I2C_OAR2(I2C1)
|
||||
#define I2C2_OAR2 I2C_OAR2(I2C2)
|
||||
|
||||
/* Data register (I2Cx_DR) */
|
||||
#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10)
|
||||
#define I2C1_DR I2C_DR(I2C1)
|
||||
#define I2C2_DR I2C_DR(I2C2)
|
||||
|
||||
/* Status register 1 (I2Cx_SR1) */
|
||||
#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14)
|
||||
#define I2C1_SR1 I2C_SR1(I2C1)
|
||||
#define I2C2_SR1 I2C_SR1(I2C2)
|
||||
|
||||
/* Status register 2 (I2Cx_SR2) */
|
||||
#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18)
|
||||
#define I2C1_SR2 I2C_SR2(I2C1)
|
||||
#define I2C2_SR2 I2C_SR2(I2C2)
|
||||
|
||||
/* Clock control register (I2Cx_CCR) */
|
||||
#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c)
|
||||
#define I2C1_CCR I2C_CCR(I2C1)
|
||||
#define I2C2_CCR I2C_CCR(I2C2)
|
||||
|
||||
/* TRISE register (I2Cx_CCR) */
|
||||
#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20)
|
||||
#define I2C1_TRISE I2C_TRISE(I2C1)
|
||||
#define I2C2_TRISE I2C_TRISE(I2C2)
|
||||
|
||||
/* --- I2Cx_CR1 values ----------------------------------------------------- */
|
||||
|
||||
/* SWRST: Software reset */
|
||||
#define I2C_CR1_SWRST (1 << 15)
|
||||
|
||||
/* Note: Bit 14 is reserved, and forced to 0 by hardware. */
|
||||
|
||||
/* ALERT: SMBus alert */
|
||||
#define I2C_CR1_ALERT (1 << 13)
|
||||
|
||||
/* PEC: Packet error checking */
|
||||
#define I2C_CR1_PEC (1 << 12)
|
||||
|
||||
/* POS: Acknowledge / PEC postition */
|
||||
#define I2C_CR1_POS (1 << 11)
|
||||
|
||||
/* ACK: Acknowledge enable */
|
||||
#define I2C_CR1_ACK (1 << 10)
|
||||
|
||||
/* STOP: STOP generation */
|
||||
#define I2C_CR1_STOP (1 << 9)
|
||||
|
||||
/* START: START generation */
|
||||
#define I2C_CR1_START (1 << 8)
|
||||
|
||||
/* NOSTRETCH: Clock stretching disable (slave mode) */
|
||||
#define I2C_CR1_NOSTRETCH (1 << 7)
|
||||
|
||||
/* ENGC: General call enable */
|
||||
#define I2C_CR1_ENGC (1 << 6)
|
||||
|
||||
/* ENPEC: Enable PEC */
|
||||
#define I2C_CR1_ENPEC (1 << 5)
|
||||
|
||||
/* ENARP: ARP enable */
|
||||
#define I2C_CR1_ENARP (1 << 4)
|
||||
|
||||
/* SMBTYPE: SMBus type */
|
||||
#define I2C_CR1_SMBTYPE (1 << 3)
|
||||
|
||||
/* Note: Bit 2 is reserved, and forced to 0 by hardware. */
|
||||
|
||||
/* SMBUS: SMBus mode */
|
||||
#define I2C_CR1_SMBUS (1 << 1)
|
||||
|
||||
/* PE: Peripheral enable */
|
||||
#define I2C_CR1_PE (1 << 0)
|
||||
|
||||
/* --- I2Cx_CR2 values ----------------------------------------------------- */
|
||||
|
||||
/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */
|
||||
|
||||
/* LAST: DMA last transfer */
|
||||
#define I2C_CR2_LAST (1 << 12)
|
||||
|
||||
/* DMAEN: DMA requests enable */
|
||||
#define I2C_CR2_DMAEN (1 << 11)
|
||||
|
||||
/* ITBUFEN: Buffer interrupt enable */
|
||||
#define I2C_CR2_ITBUFEN (1 << 10)
|
||||
|
||||
/* ITEVTEN: Event interrupt enable */
|
||||
#define I2C_CR2_ITEVTEN (1 << 9)
|
||||
|
||||
/* ITERREN: Error interrupt enable */
|
||||
#define I2C_CR2_ITERREN (1 << 8)
|
||||
|
||||
/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
|
||||
|
||||
/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
|
||||
/****************************************************************************/
|
||||
/** @defgroup i2c_clock I2C clock frequency settings
|
||||
@ingroup i2c_defines
|
||||
|
||||
@{*/
|
||||
#define I2C_CR2_FREQ_2MHZ 0x02
|
||||
#define I2C_CR2_FREQ_3MHZ 0x03
|
||||
#define I2C_CR2_FREQ_4MHZ 0x04
|
||||
#define I2C_CR2_FREQ_5MHZ 0x05
|
||||
#define I2C_CR2_FREQ_6MHZ 0x06
|
||||
#define I2C_CR2_FREQ_7MHZ 0x07
|
||||
#define I2C_CR2_FREQ_8MHZ 0x08
|
||||
#define I2C_CR2_FREQ_9MHZ 0x09
|
||||
#define I2C_CR2_FREQ_10MHZ 0x0a
|
||||
#define I2C_CR2_FREQ_11MHZ 0x0b
|
||||
#define I2C_CR2_FREQ_12MHZ 0x0c
|
||||
#define I2C_CR2_FREQ_13MHZ 0x0d
|
||||
#define I2C_CR2_FREQ_14MHZ 0x0e
|
||||
#define I2C_CR2_FREQ_15MHZ 0x0f
|
||||
#define I2C_CR2_FREQ_16MHZ 0x10
|
||||
#define I2C_CR2_FREQ_17MHZ 0x11
|
||||
#define I2C_CR2_FREQ_18MHZ 0x12
|
||||
#define I2C_CR2_FREQ_19MHZ 0x13
|
||||
#define I2C_CR2_FREQ_20MHZ 0x14
|
||||
#define I2C_CR2_FREQ_21MHZ 0x15
|
||||
#define I2C_CR2_FREQ_22MHZ 0x16
|
||||
#define I2C_CR2_FREQ_23MHZ 0x17
|
||||
#define I2C_CR2_FREQ_24MHZ 0x18
|
||||
#define I2C_CR2_FREQ_25MHZ 0x19
|
||||
#define I2C_CR2_FREQ_26MHZ 0x1a
|
||||
#define I2C_CR2_FREQ_27MHZ 0x1b
|
||||
#define I2C_CR2_FREQ_28MHZ 0x1c
|
||||
#define I2C_CR2_FREQ_29MHZ 0x1d
|
||||
#define I2C_CR2_FREQ_30MHZ 0x1e
|
||||
#define I2C_CR2_FREQ_31MHZ 0x1f
|
||||
#define I2C_CR2_FREQ_32MHZ 0x20
|
||||
#define I2C_CR2_FREQ_33MHZ 0x21
|
||||
#define I2C_CR2_FREQ_34MHZ 0x22
|
||||
#define I2C_CR2_FREQ_35MHZ 0x23
|
||||
#define I2C_CR2_FREQ_36MHZ 0x24
|
||||
/**@}*/
|
||||
|
||||
/* --- I2Cx_OAR1 values ---------------------------------------------------- */
|
||||
|
||||
/* ADDMODE: Addressing mode (slave mode) */
|
||||
#define I2C_OAR1_ADDMODE (1 << 15)
|
||||
#define I2C_OAR1_ADDMODE_7BIT 0
|
||||
#define I2C_OAR1_ADDMODE_10BIT 1
|
||||
|
||||
/* Note: Bit 14 should always be kept at 1 by software! */
|
||||
|
||||
/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */
|
||||
|
||||
/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */
|
||||
|
||||
/* --- I2Cx_OAR2 values ---------------------------------------------------- */
|
||||
|
||||
/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
|
||||
|
||||
/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */
|
||||
|
||||
/* ENDUAL: Dual addressing mode enable */
|
||||
#define I2C_OAR2_ENDUAL (1 << 0)
|
||||
|
||||
/* --- I2Cx_DR values ------------------------------------------------------ */
|
||||
|
||||
/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */
|
||||
|
||||
/* DR[7:0] 8-bit data register */
|
||||
|
||||
/* --- I2Cx_SR1 values ----------------------------------------------------- */
|
||||
|
||||
/* SMBALERT: SMBus alert */
|
||||
#define I2C_SR1_SMBALERT (1 << 15)
|
||||
|
||||
/* TIMEOUT: Timeout or Tlow Error */
|
||||
#define I2C_SR1_TIMEOUT (1 << 14)
|
||||
|
||||
/* Note: Bit 13 is reserved, and forced to 0 by hardware. */
|
||||
|
||||
/* PECERR: PEC Error in reception */
|
||||
#define I2C_SR1_PECERR (1 << 12)
|
||||
|
||||
/* OVR: Overrun/Underrun */
|
||||
#define I2C_SR1_OVR (1 << 11)
|
||||
|
||||
/* AF: Acknowledge failure */
|
||||
#define I2C_SR1_AF (1 << 10)
|
||||
|
||||
/* ARLO: Arbitration lost (master mode) */
|
||||
#define I2C_SR1_ARLO (1 << 9)
|
||||
|
||||
/* BERR: Bus error */
|
||||
#define I2C_SR1_BERR (1 << 8)
|
||||
|
||||
/* TxE: Data register empty (transmitters) */
|
||||
#define I2C_SR1_TxE (1 << 7)
|
||||
|
||||
/* RxNE: Data register not empty (receivers) */
|
||||
#define I2C_SR1_RxNE (1 << 6)
|
||||
|
||||
/* Note: Bit 5 is reserved, and forced to 0 by hardware. */
|
||||
|
||||
/* STOPF: STOP detection (slave mode) */
|
||||
#define I2C_SR1_STOPF (1 << 4)
|
||||
|
||||
/* ADD10: 10-bit header sent (master mode) */
|
||||
#define I2C_SR1_ADD10 (1 << 3)
|
||||
|
||||
/* BTF: Byte transfer finished */
|
||||
#define I2C_SR1_BTF (1 << 2)
|
||||
|
||||
/* ADDR: Address sent (master mode) / address matched (slave mode) */
|
||||
#define I2C_SR1_ADDR (1 << 1)
|
||||
|
||||
/* SB: Start bit (master mode) */
|
||||
#define I2C_SR1_SB (1 << 0)
|
||||
|
||||
/* --- I2Cx_SR2 values ----------------------------------------------------- */
|
||||
|
||||
/* Bits [15:8]: PEC[7:0]: Packet error checking register */
|
||||
|
||||
/* DUALF: Dual flag (slave mode) */
|
||||
#define I2C_SR2_DUALF (1 << 7)
|
||||
|
||||
/* SMBHOST: SMBus host header (slave mode) */
|
||||
#define I2C_SR2_SMBHOST (1 << 6)
|
||||
|
||||
/* SMBDEFAULT: SMBus device default address (slave mode) */
|
||||
#define I2C_SR2_SMBDEFAULT (1 << 5)
|
||||
|
||||
/* GENCALL: General call address (slave mode) */
|
||||
#define I2C_SR2_GENCALL (1 << 4)
|
||||
|
||||
/* Note: Bit 3 is reserved, and forced to 0 by hardware. */
|
||||
|
||||
/* TRA: Transmitter / receiver */
|
||||
#define I2C_SR2_TRA (1 << 2)
|
||||
|
||||
/* BUSY: Bus busy */
|
||||
#define I2C_SR2_BUSY (1 << 1)
|
||||
|
||||
/* MSL: Master / slave */
|
||||
#define I2C_SR2_MSL (1 << 0)
|
||||
|
||||
/* --- I2Cx_CCR values ----------------------------------------------------- */
|
||||
|
||||
/* F/S: I2C Master mode selection (fast / standard) */
|
||||
#define I2C_CCR_FS (1 << 15)
|
||||
|
||||
/* DUTY: Fast Mode Duty Cycle */
|
||||
/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles
|
||||
@ingroup i2c_defines
|
||||
|
||||
@{*/
|
||||
#define I2C_CCR_DUTY (1 << 14)
|
||||
#define I2C_CCR_DUTY_DIV2 0
|
||||
#define I2C_CCR_DUTY_16_DIV_9 1
|
||||
/**@}*/
|
||||
|
||||
/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */
|
||||
|
||||
/*
|
||||
* Bits [11:0]:
|
||||
* CCR[11:0]: Clock control register in Fast/Standard mode (master mode)
|
||||
*/
|
||||
|
||||
/* --- I2Cx_TRISE values --------------------------------------------------- */
|
||||
|
||||
/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */
|
||||
|
||||
/*
|
||||
* Bits [5:0]:
|
||||
* TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
|
||||
*/
|
||||
|
||||
/* --- I2C const definitions ----------------------------------------------- */
|
||||
|
||||
/****************************************************************************/
|
||||
/** @defgroup i2c_rw I2C Read/Write bit
|
||||
@ingroup i2c_defines
|
||||
|
||||
@{*/
|
||||
#define I2C_WRITE 0
|
||||
#define I2C_READ 1
|
||||
/**@}*/
|
||||
|
||||
/* --- I2C funtion prototypes----------------------------------------------- */
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void i2c_reset(u32 i2c);
|
||||
void i2c_peripheral_enable(u32 i2c);
|
||||
void i2c_peripheral_disable(u32 i2c);
|
||||
void i2c_send_start(u32 i2c);
|
||||
void i2c_send_stop(u32 i2c);
|
||||
void i2c_clear_stop(u32 i2c);
|
||||
void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
|
||||
void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
|
||||
void i2c_set_fast_mode(u32 i2c);
|
||||
void i2c_set_standard_mode(u32 i2c);
|
||||
void i2c_set_clock_frequency(u32 i2c, u8 freq);
|
||||
void i2c_set_ccr(u32 i2c, u16 freq);
|
||||
void i2c_set_trise(u32 i2c, u16 trise);
|
||||
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
|
||||
void i2c_send_data(u32 i2c, u8 data);
|
||||
uint8_t i2c_get_data(u32 i2c);
|
||||
void i2c_enable_interrupt(u32 i2c, u32 interrupt);
|
||||
void i2c_disable_interrupt(u32 i2c, u32 interrupt);
|
||||
void i2c_enable_ack(u32 i2c);
|
||||
void i2c_disable_ack(u32 i2c);
|
||||
void i2c_nack_next(u32 i2c);
|
||||
void i2c_nack_current(u32 i2c);
|
||||
void i2c_set_dutycycle(u32 i2c, u32 dutycycle);
|
||||
void i2c_enable_dma(u32 i2c);
|
||||
void i2c_disable_dma(u32 i2c);
|
||||
void i2c_set_dma_last_transfer(u32 i2c);
|
||||
void i2c_clear_dma_last_transfer(u32 i2c);
|
||||
|
||||
END_DECLS
|
||||
|
||||
#if defined(STM32F1)
|
||||
# include <libopencm3/stm32/f1/i2c.h>
|
||||
#elif defined(STM32F2)
|
||||
# include <libopencm3/stm32/f2/i2c.h>
|
||||
#elif defined(STM32F4)
|
||||
# include <libopencm3/stm32/f4/i2c.h>
|
||||
#elif defined(STM32L1)
|
||||
# include <libopencm3/stm32/l1/i2c.h>
|
||||
#else
|
||||
# error "stm32 family not defined."
|
||||
#endif
|
||||
/**@}*/
|
||||
|
||||
|
||||
41
include/libopencm3/stm32/l1/i2c.h
Normal file
41
include/libopencm3/stm32/l1/i2c.h
Normal file
@ -0,0 +1,41 @@
|
||||
/** @defgroup i2c_defines I2C Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32L1xx I2C </b>
|
||||
|
||||
@ingroup STM32L1xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 12 October 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_I2C_H
|
||||
#define LIBOPENCM3_I2C_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/stm32/common/i2c_common_all.h>
|
||||
|
||||
#endif
|
||||
|
||||
@ -17,354 +17,6 @@
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
<<<<<<< HEAD
|
||||
/**@{*/
|
||||
|
||||
#ifndef LIBOPENCM3_USART_H
|
||||
#define LIBOPENCM3_USART_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/cm3/common.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/****************************************************************************/
|
||||
/** @defgroup usart_reg_base USART register base addresses
|
||||
@ingroup STM32F_usart_defines
|
||||
|
||||
@{*/
|
||||
#define USART1 USART1_BASE
|
||||
#define USART2 USART2_BASE
|
||||
#define USART3 USART3_BASE
|
||||
/**@}*/
|
||||
#define UART4 UART4_BASE
|
||||
#define UART5 UART5_BASE
|
||||
|
||||
/* --- USART registers ----------------------------------------------------- */
|
||||
|
||||
/* Status register (USARTx_SR) */
|
||||
#define USART_SR(usart_base) MMIO32(usart_base + 0x00)
|
||||
#define USART1_SR USART_SR(USART1_BASE)
|
||||
#define USART2_SR USART_SR(USART2_BASE)
|
||||
#define USART3_SR USART_SR(USART3_BASE)
|
||||
#define UART4_SR USART_SR(UART4_BASE)
|
||||
#define UART5_SR USART_SR(UART5_BASE)
|
||||
|
||||
/* Data register (USARTx_DR) */
|
||||
#define USART_DR(usart_base) MMIO32(usart_base + 0x04)
|
||||
#define USART1_DR USART_DR(USART1_BASE)
|
||||
#define USART2_DR USART_DR(USART2_BASE)
|
||||
#define USART3_DR USART_DR(USART3_BASE)
|
||||
#define UART4_DR USART_DR(UART4_BASE)
|
||||
#define UART5_DR USART_DR(UART5_BASE)
|
||||
|
||||
/* Baud rate register (USARTx_BRR) */
|
||||
#define USART_BRR(usart_base) MMIO32(usart_base + 0x08)
|
||||
#define USART1_BRR USART_BRR(USART1_BASE)
|
||||
#define USART2_BRR USART_BRR(USART2_BASE)
|
||||
#define USART3_BRR USART_BRR(USART3_BASE)
|
||||
#define UART4_BRR USART_BRR(UART4_BASE)
|
||||
#define UART5_BRR USART_BRR(UART5_BASE)
|
||||
|
||||
/* Control register 1 (USARTx_CR1) */
|
||||
#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c)
|
||||
#define USART1_CR1 USART_CR1(USART1_BASE)
|
||||
#define USART2_CR1 USART_CR1(USART2_BASE)
|
||||
#define USART3_CR1 USART_CR1(USART3_BASE)
|
||||
#define UART4_CR1 USART_CR1(UART4_BASE)
|
||||
#define UART5_CR1 USART_CR1(UART5_BASE)
|
||||
|
||||
/* Control register 2 (USARTx_CR2) */
|
||||
#define USART_CR2(usart_base) MMIO32(usart_base + 0x10)
|
||||
#define USART1_CR2 USART_CR2(USART1_BASE)
|
||||
#define USART2_CR2 USART_CR2(USART2_BASE)
|
||||
#define USART3_CR2 USART_CR2(USART3_BASE)
|
||||
#define UART4_CR2 USART_CR2(UART4_BASE)
|
||||
#define UART5_CR2 USART_CR2(UART5_BASE)
|
||||
|
||||
/* Control register 3 (USARTx_CR3) */
|
||||
#define USART_CR3(usart_base) MMIO32(usart_base + 0x14)
|
||||
#define USART1_CR3 USART_CR3(USART1_BASE)
|
||||
#define USART2_CR3 USART_CR3(USART2_BASE)
|
||||
#define USART3_CR3 USART_CR3(USART3_BASE)
|
||||
#define UART4_CR3 USART_CR3(UART4_BASE)
|
||||
#define UART5_CR3 USART_CR3(UART5_BASE)
|
||||
|
||||
/* Guard time and prescaler register (USARTx_GTPR) */
|
||||
#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18)
|
||||
#define USART1_GTPR USART_GTPR(USART1_BASE)
|
||||
#define USART2_GTPR USART_GTPR(USART2_BASE)
|
||||
#define USART3_GTPR USART_GTPR(USART3_BASE)
|
||||
#define UART4_GTPR USART_GTPR(UART4_BASE)
|
||||
#define UART5_GTPR USART_GTPR(UART5_BASE)
|
||||
|
||||
/* --- USART_SR values ----------------------------------------------------- */
|
||||
/****************************************************************************/
|
||||
/** @defgroup usart_sr_flags USART Status register Flags
|
||||
@ingroup STM32F_usart_defines
|
||||
|
||||
@{*/
|
||||
|
||||
/** CTS: CTS flag */
|
||||
/** @note: undefined on UART4 and UART5 */
|
||||
#define USART_SR_CTS (1 << 9)
|
||||
|
||||
/** LBD: LIN break detection flag */
|
||||
#define USART_SR_LBD (1 << 8)
|
||||
|
||||
/** TXE: Transmit data buffer empty */
|
||||
#define USART_SR_TXE (1 << 7)
|
||||
|
||||
/** TC: Transmission complete */
|
||||
#define USART_SR_TC (1 << 6)
|
||||
|
||||
/** RXNE: Read data register not empty */
|
||||
#define USART_SR_RXNE (1 << 5)
|
||||
|
||||
/** IDLE: Idle line detected */
|
||||
#define USART_SR_IDLE (1 << 4)
|
||||
|
||||
/** ORE: Overrun error */
|
||||
#define USART_SR_ORE (1 << 3)
|
||||
|
||||
/** NE: Noise error flag */
|
||||
#define USART_SR_NE (1 << 2)
|
||||
|
||||
/** FE: Framing error */
|
||||
#define USART_SR_FE (1 << 1)
|
||||
|
||||
/** PE: Parity error */
|
||||
#define USART_SR_PE (1 << 0)
|
||||
/**@}*/
|
||||
|
||||
/* --- USART_DR values ----------------------------------------------------- */
|
||||
|
||||
/* USART_DR[8:0]: DR[8:0]: Data value */
|
||||
#define USART_DR_MASK 0x1FF
|
||||
|
||||
/* --- USART_BRR values ---------------------------------------------------- */
|
||||
|
||||
/* DIV_Mantissa[11:0]: mantissa of USARTDIV */
|
||||
#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4)
|
||||
/* DIV_Fraction[3:0]: fraction of USARTDIV */
|
||||
#define USART_BRR_DIV_FRACTION_MASK 0xF
|
||||
|
||||
/* --- USART_CR1 values ---------------------------------------------------- */
|
||||
|
||||
/* UE: USART enable */
|
||||
#define USART_CR1_UE (1 << 13)
|
||||
|
||||
/* M: Word length */
|
||||
#define USART_CR1_M (1 << 12)
|
||||
|
||||
/* WAKE: Wakeup method */
|
||||
#define USART_CR1_WAKE (1 << 11)
|
||||
|
||||
/* PCE: Parity control enable */
|
||||
#define USART_CR1_PCE (1 << 10)
|
||||
|
||||
/* PS: Parity selection */
|
||||
#define USART_CR1_PS (1 << 9)
|
||||
|
||||
/* PEIE: PE interrupt enable */
|
||||
#define USART_CR1_PEIE (1 << 8)
|
||||
|
||||
/* TXEIE: TXE interrupt enable */
|
||||
#define USART_CR1_TXEIE (1 << 7)
|
||||
|
||||
/* TCIE: Transmission complete interrupt enable */
|
||||
#define USART_CR1_TCIE (1 << 6)
|
||||
|
||||
/* RXNEIE: RXNE interrupt enable */
|
||||
#define USART_CR1_RXNEIE (1 << 5)
|
||||
|
||||
/* IDLEIE: IDLE interrupt enable */
|
||||
#define USART_CR1_IDLEIE (1 << 4)
|
||||
|
||||
/* TE: Transmitter enable */
|
||||
#define USART_CR1_TE (1 << 3)
|
||||
|
||||
/* RE: Receiver enable */
|
||||
#define USART_CR1_RE (1 << 2)
|
||||
|
||||
/* RWU: Receiver wakeup */
|
||||
#define USART_CR1_RWU (1 << 1)
|
||||
|
||||
/* SBK: Send break */
|
||||
#define USART_CR1_SBK (1 << 0)
|
||||
|
||||
/* --- USART_CR2 values ---------------------------------------------------- */
|
||||
|
||||
/* LINEN: LIN mode enable */
|
||||
#define USART_CR2_LINEN (1 << 14)
|
||||
|
||||
/* STOP[13:12]: STOP bits */
|
||||
#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */
|
||||
#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */
|
||||
#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */
|
||||
#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */
|
||||
#define USART_CR2_STOPBITS_MASK (0x03 << 12)
|
||||
#define USART_CR2_STOPBITS_SHIFT 12
|
||||
|
||||
/* CLKEN: Clock enable */
|
||||
#define USART_CR2_CLKEN (1 << 11)
|
||||
|
||||
/* CPOL: Clock polarity */
|
||||
#define USART_CR2_CPOL (1 << 10)
|
||||
|
||||
/* CPHA: Clock phase */
|
||||
#define USART_CR2_CPHA (1 << 9)
|
||||
|
||||
/* LBCL: Last bit clock pulse */
|
||||
#define USART_CR2_LBCL (1 << 8)
|
||||
|
||||
/* LBDIE: LIN break detection interrupt enable */
|
||||
#define USART_CR2_LBDIE (1 << 6)
|
||||
|
||||
/* LBDL: LIN break detection length */
|
||||
#define USART_CR2_LBDL (1 << 5)
|
||||
|
||||
/* ADD[3:0]: Addres of the usart node */
|
||||
#define USART_CR2_ADD_MASK 0xF
|
||||
|
||||
/* --- USART_CR3 values ---------------------------------------------------- */
|
||||
|
||||
/* CTSIE: CTS interrupt enable */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_CR3_CTSIE (1 << 10)
|
||||
|
||||
/* CTSE: CTS enable */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_CR3_CTSE (1 << 9)
|
||||
|
||||
/* RTSE: RTS enable */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_CR3_RTSE (1 << 8)
|
||||
|
||||
/* DMAT: DMA enable transmitter */
|
||||
/* Note: N/A on UART5 */
|
||||
#define USART_CR3_DMAT (1 << 7)
|
||||
|
||||
/* DMAR: DMA enable receiver */
|
||||
/* Note: N/A on UART5 */
|
||||
#define USART_CR3_DMAR (1 << 6)
|
||||
|
||||
/* SCEN: Smartcard mode enable */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_CR3_SCEN (1 << 5)
|
||||
|
||||
/* NACK: Smartcard NACK enable */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_CR3_NACK (1 << 4)
|
||||
|
||||
/* HDSEL: Half-duplex selection */
|
||||
#define USART_CR3_HDSEL (1 << 3)
|
||||
|
||||
/* IRLP: IrDA low-power */
|
||||
#define USART_CR3_IRLP (1 << 2)
|
||||
|
||||
/* IREN: IrDA mode enable */
|
||||
#define USART_CR3_IREN (1 << 1)
|
||||
|
||||
/* EIE: Error interrupt enable */
|
||||
#define USART_CR3_EIE (1 << 0)
|
||||
|
||||
/* --- USART_GTPR values --------------------------------------------------- */
|
||||
|
||||
/* GT[7:0]: Guard time value */
|
||||
/* Note: N/A on UART4 & UART5 */
|
||||
#define USART_GTPR_GT_MASK (0xFF << 8)
|
||||
|
||||
/* PSC[7:0]: Prescaler value */
|
||||
/* Note: N/A on UART4/5 */
|
||||
#define USART_GTPR_PSC_MASK 0xFF
|
||||
|
||||
/* TODO */ /* Note to Uwe: what needs to be done here? */
|
||||
|
||||
/* --- Convenience defines ------------------------------------------------- */
|
||||
|
||||
/* CR1_PCE / CR1_PS combined values */
|
||||
/****************************************************************************/
|
||||
/** @defgroup usart_cr1_parity USART Parity Selection
|
||||
@ingroup STM32F_usart_defines
|
||||
|
||||
@{*/
|
||||
#define USART_PARITY_NONE 0x00
|
||||
#define USART_PARITY_EVEN USART_CR1_PCE
|
||||
#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE)
|
||||
/**@}*/
|
||||
#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE)
|
||||
|
||||
/* CR1_TE/CR1_RE combined values */
|
||||
/****************************************************************************/
|
||||
/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection
|
||||
@ingroup STM32F_usart_defines
|
||||
|
||||
@{*/
|
||||
#define USART_MODE_RX USART_CR1_RE
|
||||
#define USART_MODE_TX USART_CR1_TE
|
||||
#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE)
|
||||
/**@}*/
|
||||
#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE)
|
||||
|
||||
/****************************************************************************/
|
||||
/** @defgroup usart_cr2_stopbits USART Stop Bit Selection
|
||||
@ingroup STM32F_usart_defines
|
||||
|
||||
@{*/
|
||||
#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */
|
||||
#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */
|
||||
#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */
|
||||
#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */
|
||||
/**@}*/
|
||||
|
||||
/* CR3_CTSE/CR3_RTSE combined values */
|
||||
/****************************************************************************/
|
||||
/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
|
||||
@ingroup STM32F_usart_defines
|
||||
|
||||
@{*/
|
||||
#define USART_FLOWCONTROL_NONE 0x00
|
||||
#define USART_FLOWCONTROL_RTS USART_CR3_RTSE
|
||||
#define USART_FLOWCONTROL_CTS USART_CR3_CTSE
|
||||
#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
|
||||
/**@}*/
|
||||
#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE)
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void usart_set_baudrate(u32 usart, u32 baud);
|
||||
void usart_set_databits(u32 usart, u32 bits);
|
||||
void usart_set_stopbits(u32 usart, u32 stopbits);
|
||||
void usart_set_parity(u32 usart, u32 parity);
|
||||
void usart_set_mode(u32 usart, u32 mode);
|
||||
void usart_set_flow_control(u32 usart, u32 flowcontrol);
|
||||
void usart_enable(u32 usart);
|
||||
void usart_disable(u32 usart);
|
||||
void usart_send(u32 usart, u16 data);
|
||||
u16 usart_recv(u32 usart);
|
||||
void usart_wait_send_ready(u32 usart);
|
||||
void usart_wait_recv_ready(u32 usart);
|
||||
void usart_send_blocking(u32 usart, u16 data);
|
||||
u16 usart_recv_blocking(u32 usart);
|
||||
void usart_enable_rx_dma(u32 usart);
|
||||
void usart_disable_rx_dma(u32 usart);
|
||||
void usart_enable_tx_dma(u32 usart);
|
||||
void usart_disable_tx_dma(u32 usart);
|
||||
void usart_enable_rx_interrupt(u32 usart);
|
||||
void usart_disable_rx_interrupt(u32 usart);
|
||||
void usart_enable_tx_interrupt(u32 usart);
|
||||
void usart_disable_tx_interrupt(u32 usart);
|
||||
void usart_enable_error_interrupt(u32 usart);
|
||||
void usart_disable_error_interrupt(u32 usart);
|
||||
bool usart_get_flag(u32 usart, u32 flag);
|
||||
bool usart_get_interrupt_source(u32 usart, u32 flag);
|
||||
|
||||
END_DECLS
|
||||
|
||||
=======
|
||||
#if defined(STM32F1)
|
||||
# include <libopencm3/stm32/f1/usart.h>
|
||||
#elif defined(STM32F2)
|
||||
@ -375,6 +27,5 @@ END_DECLS
|
||||
# include <libopencm3/stm32/l1/usart.h>
|
||||
#else
|
||||
# error "stm32 family not defined."
|
||||
>>>>>>> Move usart files to common area
|
||||
#endif
|
||||
|
||||
|
||||
@ -1,8 +1,4 @@
|
||||
/** @defgroup i2c_file I2C
|
||||
|
||||
@ingroup STM32F_files
|
||||
|
||||
@brief <b>libopencm3 STM32Fxxx I2C</b>
|
||||
/** @addtogroup i2c_file
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@ -43,7 +39,7 @@ LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/i2c.h>
|
||||
#include <libopencm3/stm32/f4/rcc.h>
|
||||
#include <libopencm3/stm32/rcc.h>
|
||||
|
||||
/**@{*/
|
||||
|
||||
@ -34,7 +34,7 @@ OBJS = rcc.o gpio.o usart.o adc.o flash.o \
|
||||
timer.o usb_f107.o desig.o crc.o pwr.o \
|
||||
usb_fx07_common.o \
|
||||
gpio_common_all.o spi_common_all.o dac_common_all.o \
|
||||
usart_common_all.o iwdg_common_all.o
|
||||
usart_common_all.o iwdg_common_all.o i2c_common_all.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
|
||||
|
||||
28
lib/stm32/f1/i2c.c
Normal file
28
lib/stm32/f1/i2c.c
Normal file
@ -0,0 +1,28 @@
|
||||
/** @defgroup i2c_file I2C
|
||||
|
||||
@ingroup STM32F1xx
|
||||
|
||||
@brief <b>libopencm3 STM32F1xx I2C</b>
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/i2c.h>
|
||||
#include <libopencm3/stm32/common/i2c_common_all.h>
|
||||
|
||||
@ -31,7 +31,7 @@ ARFLAGS = rcs
|
||||
OBJS = rcc.o gpio.o usart.o flash.o \
|
||||
i2c.o exti2.o timer.o \
|
||||
gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \
|
||||
usart_common_all.o iwdg_common_all.o
|
||||
usart_common_all.o iwdg_common_all.o i2c_common_all.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
|
||||
|
||||
28
lib/stm32/f2/i2c.c
Normal file
28
lib/stm32/f2/i2c.c
Normal file
@ -0,0 +1,28 @@
|
||||
/** @defgroup i2c_file I2C
|
||||
|
||||
@ingroup STM32F2xx
|
||||
|
||||
@brief <b>libopencm3 STM32F2xx I2C</b>
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/i2c.h>
|
||||
#include <libopencm3/stm32/common/spi_common_all.h>
|
||||
|
||||
@ -34,7 +34,7 @@ OBJS = rcc.o gpio.o usart.o flash.o \
|
||||
usb.o usb_standard.o usb_control.o usb_fx07_common.o usb_f107.o \
|
||||
usb_f207.o adc.o dma.o \
|
||||
gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o \
|
||||
usart_common_all.o iwdg_common_all.o
|
||||
usart_common_all.o iwdg_common_all.o i2c_common_all.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
|
||||
|
||||
28
lib/stm32/f4/i2c.c
Normal file
28
lib/stm32/f4/i2c.c
Normal file
@ -0,0 +1,28 @@
|
||||
/** @defgroup i2c_file I2C
|
||||
|
||||
@ingroup STM32F4xx
|
||||
|
||||
@brief <b>libopencm3 STM32F4xx I2C</b>
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/i2c.h>
|
||||
#include <libopencm3/stm32/common/spi_common_all.h>
|
||||
|
||||
@ -29,7 +29,8 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
|
||||
# ARFLAGS = rcsv
|
||||
ARFLAGS = rcs
|
||||
OBJS = rcc.o desig.o crc.o usart.o exti2.o flash.o timer.o
|
||||
OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o dac_common_all.o usart_common_all.o iwdg_common_all.o
|
||||
OBJS += gpio_common_all.o gpio_common_f24.o spi_common_all.o
|
||||
OBJS += dac_common_all.o usart_common_all.o iwdg_common_all.o i2c_common_all.o
|
||||
OBJS += pwr_chipset.o # TODO, get pwr.o to fix f2/f4 first... pwr.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
|
||||
28
lib/stm32/l1/i2c.c
Normal file
28
lib/stm32/l1/i2c.c
Normal file
@ -0,0 +1,28 @@
|
||||
/** @defgroup i2c_file I2C
|
||||
|
||||
@ingroup STM32L1xx
|
||||
|
||||
@brief <b>libopencm3 STM32L1xx I2C</b>
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/i2c.h>
|
||||
#include <libopencm3/stm32/common/spi_common_all.h>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user