[stm32f4-ltdc] initial commit
This commit is contained in:
Oliver Meier
Piotr Esden-Tempski
parent
4b8f6e01ab
commit
eaae7731e9
173
include/libopencm3/stm32/f4/ltdc.h
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173
include/libopencm3/stm32/f4/ltdc.h
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@ -0,0 +1,173 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Oliver Meier <h2obrain@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_STM32_F4_LTDC_H_
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#define LIBOPENCM3_STM32_F4_LTDC_H_
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#include <stdint.h>
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#include "memorymap.h"
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/**
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* LTDC
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*/
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#define LTDC_SSCR (MMIO32(LTDC_BASE + 0x08))
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#define LTDC_BPCR (MMIO32(LTDC_BASE + 0x0C))
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#define LTDC_AWCR (MMIO32(LTDC_BASE + 0x10))
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#define LTDC_TWCR (MMIO32(LTDC_BASE + 0x14))
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#define LTDC_GCR (MMIO32(LTDC_BASE + 0x18))
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#define LTDC_SRCR (MMIO32(LTDC_BASE + 0x24))
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#define LTDC_BCCR (MMIO32(LTDC_BASE + 0x2C))
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#define LTDC_IER (MMIO32(LTDC_BASE + 0x34))
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#define LTDC_ISR (MMIO32(LTDC_BASE + 0x38))
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#define LTDC_ICR (MMIO32(LTDC_BASE + 0x3C))
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#define LTDC_LIPCR (MMIO32(LTDC_BASE + 0x40))
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#define LTDC_CPSR (MMIO32(LTDC_BASE + 0x44))
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#define LTDC_CDSR (MMIO32(LTDC_BASE + 0x48))
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/* x == LTDC_LAYER_x */
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#define LTDC_LxCR(x) (MMIO32(LTDC_BASE + 0x84+0x80*(x-1)))
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#define LTDC_LxWHPCR(x) (MMIO32(LTDC_BASE + 0x88+0x80*(x-1)))
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#define LTDC_LxWVPCR(x) (MMIO32(LTDC_BASE + 0x8C+0x80*(x-1)))
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#define LTDC_LxCKCR(x) (MMIO32(LTDC_BASE + 0x90+0x80*(x-1)))
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#define LTDC_LxPFCR(x) (MMIO32(LTDC_BASE + 0x94+0x80*(x-1)))
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#define LTDC_LxCACR(x) (MMIO32(LTDC_BASE + 0x98+0x80*(x-1)))
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#define LTDC_LxDCCR(x) (MMIO32(LTDC_BASE + 0x9C+0x80*(x-1)))
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#define LTDC_LxBFCR(x) (MMIO32(LTDC_BASE + 0xA0+0x80*(x-1)))
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#define LTDC_LxCFBAR(x) (MMIO32(LTDC_BASE + 0xAC+0x80*(x-1)))
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#define LTDC_LxCFBLR(x) (MMIO32(LTDC_BASE + 0xB0+0x80*(x-1)))
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#define LTDC_LxCFBLNR(x) (MMIO32(LTDC_BASE + 0xB4+0x80*(x-1)))
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#define LTDC_LxCLUTWR(x) (MMIO32(LTDC_BASE + 0xC4+0x80*(x-1)))
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#define LTDC_LAYER_1 1
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#define LTDC_LAYER_2 2
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/* GCR - control register */
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#define LTDC_GCR_LTDC_ENABLE (1<<0)
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#define LTDC_GCR_DITHER_ENABLE (1<<16)
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#define LTDC_GCR_PCPOL_ACTIVE_LOW (0<<28)
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#define LTDC_GCR_PCPOL_ACTIVE_HIGH (1<<28)
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#define LTDC_GCR_DEPOL_ACTIVE_LOW (0<<29)
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#define LTDC_GCR_DEPOL_ACTIVE_HIGH (1<<29)
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#define LTDC_GCR_VSPOL_ACTIVE_LOW (0<<30)
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#define LTDC_GCR_VSPOL_ACTIVE_HIGH (1<<30)
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#define LTDC_GCR_HSPOL_ACTIVE_LOW (0<<31)
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#define LTDC_GCR_HSPOL_ACTIVE_HIGH (1<<31)
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/* LTDC_BCCR - reload control */
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#define LTDC_SRCR_RELOAD_IMR (1<<0)
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#define LTDC_SRCR_RELOAD_VBR (1<<1)
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/* LTDC_CDSR - display status register */
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#define LTDC_CDSR_VDES (1<<0)
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#define LTDC_CDSR_HDES (1<<1)
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#define LTDC_CDSR_VSYNCS (1<<2)
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#define LTDC_CDSR_HSYNCS (1<<3)
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/* LTDC_LxCR - layer control */
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#define LTDC_LxCR_LAYER_ENABLE (1<<0)
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#define LTDC_LxCR_COLKEY_ENABLE (1<<1)
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#define LTDC_LxCR_COLTAB_ENABLE (1<<4)
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/* LTDC_LxPFCR - Pixel formats */
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#define LTDC_LxPFCR_ARGB8888 (0b000)
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#define LTDC_LxPFCR_RGB888 (0b001)
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#define LTDC_LxPFCR_RGB565 (0b010)
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#define LTDC_LxPFCR_ARGB1555 (0b011)
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#define LTDC_LxPFCR_ARGB4444 (0b100)
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#define LTDC_LxPFCR_L8 (0b101)
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#define LTDC_LxPFCR_AL44 (0b110)
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#define LTDC_LxPFCR_AL88 (0b111)
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/* LTDC_LxBFCR - Blending factors - BF1 */
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#define LTDC_LxBFCR_BF1_CONST_ALPHA (0b100)
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#define LTDC_LxBFCR_BF1_PIXEL_ALPHA_x_CONST_ALPHA (0b110)
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/* LTDC_LxBFCR - Blending factors - BF2 */
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#define LTDC_LxBFCR_BF2_CONST_ALPHA (0b101)
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#define LTDC_LxBFCR_BF2_PIXEL_ALPHA_x_CONST_ALPHA (0b111)
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/**
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* simple helper macros
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*/
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/* global */
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#define ltdc_ctrl_enable(ctrl_flags) \
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LTDC_GCR |= ctrl_flags
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#define ltdc_ctrl_disable(ctrl_flags) \
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LTDC_GCR &= ~(ctrl_flags)
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#define ltdc_reload(reload_flags) \
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LTDC_SRCR = reload_flags
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#define ltdc_set_background_color(r,g,b) \
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LTDC_BCCR = (((r)&255)<<16) | (((g)&255)<<8) | (((b)&255)<<0);
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#define ltdc_get_current_position(x,y) \
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{ y=LTDC_CPSR; x=y>>16; y&=0xffff; }
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#define ltdc_get_current_position_x() \
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(LTDC_CPSR>>16)
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#define ltdc_get_current_position_y() \
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(LTDC_CPSR&0xffff)
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#define ltdc_get_display_status(status_flags) \
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(LTDC_CDSR&(status_flags))
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/* layers */
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#define ltdc_layer_ctrl_enable(layer,ctrl_flags) \
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LTDC_LxCR(layer) |= ctrl_flags
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#define ltdc_layer_ctrl_disable(layer,ctrl_flags) \
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LTDC_LxCR(layer) &= ~(ctrl_flags)
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#define ltdc_set_color_key(layer,r,g,b) \
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LTDC_LxCKCR(layer) = ((((r)&255)<<16) | (((g)&255)<<8) | (((b)&255)<<0))
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#define ltdc_set_pixel_format(layer,format) \
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LTDC_LxPFCR(layer) = format
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#define ltdc_set_constant_alpha(layer,alpha) \
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LTDC_LxCACR(layer) = ((alpha)&255)
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#define ltdc_set_default_colors(layer,a,r,g,b) \
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LTDC_LxDCCR(layer) = \
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((((a)&255)<<24) | (((r)&255)<<16) | (((g)&255)<<8) | (((b)&255)<<0))
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#define ltdc_set_blending_factors(layer,bf1,bf2) \
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LTDC_LxBFCR(layer) = ((bf1)<<8) | ((bf2)<<0)
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#define ltdc_set_fbuffer_address(layer,address) \
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LTDC_LxCFBAR(layer) = (uint32_t)address
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#define ltdc_set_fb_line_length(layer,len,pitch) \
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LTDC_LxCFBLR(layer) = ((((pitch)&0x1FFF)<<16) | (((len)&0x1FFF)<<0))
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#define ltdc_set_fb_line_count(layer, linecount) \
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LTDC_LxCFBLNR(layer) = (((linecount)&0x3FF)<<0)
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/**
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* more complicated helper functions
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*/
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void ltdc_set_tft_sync_timings(
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uint16_t sync_width, uint16_t sync_height,
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uint16_t h_back_porch, uint16_t v_back_porch,
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uint16_t active_width, uint16_t active_height,
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uint16_t h_front_porch, uint16_t v_front_porch
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);
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void ltdc_setup_windowing(
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uint8_t layer_number,
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uint16_t h_back_porch, uint16_t v_back_porch,
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uint16_t active_width, uint16_t active_height
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);
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#endif /* LIBOPENCM3_STM32_F4_LTDC_H_ */
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@ -96,6 +96,7 @@
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#define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400)
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#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800)
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#define LCD_TFT_BASE (PERIPH_BASE_APB2 + 0x6800)
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#define LTDC_BASE LCD_TFT_BASE
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/* PERIPH_BASE_APB2 + 0x6C00 (0x4001 6C00 - 0x4001 FFFF): Reserved */
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/* AHB1 */
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@ -81,9 +81,13 @@
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/* RCC_BASE + 0x7c Reserved */
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#define RCC_SSCGR MMIO32(RCC_BASE + 0x80)
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#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84)
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#define RCC_PLLSAICFGR MMIO32(RCC_BASE + 0x88)
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#define RCC_DCKCFGR MMIO32(RCC_BASE + 0x8C)
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/* --- RCC_CR values ------------------------------------------------------- */
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#define RCC_CR_PLLSAIRDY (1 << 29)
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#define RCC_CR_PLLSAION (1 << 28)
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#define RCC_CR_PLLI2SRDY (1 << 27)
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#define RCC_CR_PLLI2SON (1 << 26)
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#define RCC_CR_PLLRDY (1 << 25)
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@ -481,6 +485,22 @@
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/* RCC_PLLI2SCFGR[14:6]: PLLI2SN */
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#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6
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/* --- RCC_DCKCFGR values -------------------------------------------------- */
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#define RCC_DCKCFGR_PLLSAIDIVR_MSK (0x3<<16)
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#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_2 (0x0)
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#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_4 (0x1)
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#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_8 (0x2)
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#define RCC_DCKCFGR_PLLSAIDIVR_DIVR_16 (0x3)
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/* PLLSAI1 helper macros */
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#define rcc_pllsai_enable() RCC_CR |= RCC_CR_PLLSAION
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#define rcc_pllsai_ready() (RCC_CR & RCC_CR_PLLSAIRDY)
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/* pllsain=49..432, pllsaiq=2..15, pllsair=2..7 */
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#define rcc_pllsai_config(pllsain,pllsaiq,pllsair) \
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RCC_PLLSAICFGR = (((pllsain&0x1ff)<<6) | ((pllsaiq&0xF)<<24) | ((pllsair&0x7)<<28))
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#define rcc_ltdc_set_clock_divr(pllsaidivr) \
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RCC_DCKCFGR = (((RCC_DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR_MSK)|((pllsaidivr&0x3)<<16)))
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/* --- Variable definitions ------------------------------------------------ */
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extern uint32_t rcc_ahb_frequency;
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extern uint32_t rcc_apb1_frequency;
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@ -597,6 +617,9 @@ enum rcc_periph_clken {
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RCC_TIM11 = _REG_BIT(0x44, 18),
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RCC_SPI5 = _REG_BIT(0x44, 20),/* F2xx, F3xx */
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RCC_SPI6 = _REG_BIT(0x44, 21),/* F2xx, F3xx */
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RCC_SAI1EN = _REG_BIT(0x44, 22),/* F42x, F43x */
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RCC_LTDC = _REG_BIT(0x44, 26),/* F42x, F43x */
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/* BDCR */
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RCC_RTC = _REG_BIT(0x70, 15),
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@ -751,6 +774,8 @@ enum rcc_periph_rst {
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RST_TIM11 = _REG_BIT(0x24, 18),
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RST_SPI5 = _REG_BIT(0x24, 20),/* F2xx, F3xx */
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RST_SPI6 = _REG_BIT(0x24, 21),/* F2xx, F3xx */
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RST_SAI1RST = _REG_BIT(0x24, 22),/* F42x, F43x */
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RST_LTDC = _REG_BIT(0x24, 26),/* F42x, F43x */
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};
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#undef _REG_BIT
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90
lib/stm32/f4/ltdc.c
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90
lib/stm32/f4/ltdc.c
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@ -0,0 +1,90 @@
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/** @defgroup ltdc_file LTDC
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*
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* @ingroup STM32F4xx
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*
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* @brief <b>libopencm3 STM32F4xx LTDC</b>
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2014
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* Oliver Meier <h2obrain@gmail.com>
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*
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* @date 5 December 2014
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*
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* This library supports the LCD controller (LTDC) in the STM32F4
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* series of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* For the STM32F4xx, LTDC is described in LCD-TFT Controller (LTDC)
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* section 16 of the STM32F4xx Reference Manual (RM0090,Rev8).
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*
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Oliver Meier <h2obrain@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/f4/ltdc.h>
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void ltdc_set_tft_sync_timings(
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uint16_t sync_width, uint16_t sync_height,
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uint16_t h_back_porch, uint16_t v_back_porch,
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uint16_t active_width, uint16_t active_height,
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uint16_t h_front_porch, uint16_t v_front_porch
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) {
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assert((active_width <= 0x400) && (active_height <= 0x300));
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uint16_t w,h;
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w=sync_width -1;
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h=sync_height -1;
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assert((w&0xfff == w) && (h&0x7ff == h));
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LTDC_SSCR = (w<<16) | (h<<0);
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w+=h_back_porch;
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h+=v_back_porch;
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assert((w&0xfff == w) && (h&0x7ff == h));
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LTDC_BPCR = (w<<16) | (h<<0);
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w+=active_width;
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h+=active_height;
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assert((w&0xfff == w) && (h&0x7ff == h));
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LTDC_AWCR = (w<<16) | (h<<0);
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w+=h_front_porch;
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h+=v_front_porch;
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assert((w&0xfff == w) && (h&0x7ff == h));
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LTDC_TWCR = (w<<16) | (h<<0);
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}
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void ltdc_setup_windowing(
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uint8_t layer_number,
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uint16_t h_back_porch, uint16_t v_back_porch,
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uint16_t active_width, uint16_t active_height
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) {
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active_width += h_back_porch-1;
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active_height += v_back_porch-1;
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assert(
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(h_back_porch&0xfff == h_back_porch) && (v_back_porch &0xfff == v_back_porch) &&
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(active_width&0xfff == active_width) && (active_height&0xfff == active_height)
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);
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LTDC_LxWHPCR(layer_number) = (active_width <<16) | (h_back_porch<<0);
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LTDC_LxWVPCR(layer_number) = (active_height<<16) | (v_back_porch<<0);
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}
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