Completed scb.h definitions.
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@ -47,6 +47,9 @@
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/* SHP: System Handler Priority Registers */
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/* Note: 12 8bit registers */
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#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
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#define SCB_SHPR1 MMIO8(SCB_BASE + 0x18 + 1)
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#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
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#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
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/* SHCSR: System Handler Control and State Register */
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#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
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@ -161,7 +164,119 @@
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/* NONBASETHRDENA */
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#define SCB_CCR_NONBASETHRDENA (1 << 0)
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/* --- SCB_SHPR1 values ---------------------------------------------------- */
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/* Bits [31:24]: reserved - must be kept cleared */
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/* PRI_6[23:16]: Priority of system handler 6, usage fault */
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#define SCB_SHPR1_PRI_6_LSB 16
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/* PRI_5[15:8]: Priority of system handler 5, bus fault */
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#define SCB_SHPR1_PRI_5_LSB 8
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/* PRI_4[7:0]: Priority of system handler 4, memory management fault */
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#define SCB_SHPR1_PRI_4_LSB 0
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/* --- SCB_SHPR2 values ---------------------------------------------------- */
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/* PRI_11[31:24]: Priority of system handler 11, SVCall */
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#define SCB_SHPR2_PRI_11_LSB 24
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/* Bits [23:0]: reserved - must be kept cleared */
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/* --- SCB_SHPR3 values ---------------------------------------------------- */
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/* PRI_15[31:24]: Priority of system handler 15, SysTick exception */
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#define SCB_SHPR3_PRI_15_LSB 24
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/* PRI_14[23:16]: Priority of system handler 14, PendSV */
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#define SCB_SHPR3_PRI_14_LSB 16
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/* Bits [15:0]: reserved - must be kept cleared */
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/* --- SCB_SHCSR values ---------------------------------------------------- */
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/* Bits [31:19]: reserved - must be kept cleared */
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/* USGFAULTENA: Usage fault enable */
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#define SCB_SHCSR_USGFAULTENA (1 << 18)
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/* BUSFAULTENA: Bus fault enable */
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#define SCB_SHCSR_BUSFAULTENA (1 << 17)
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/* MEMFAULTENA: Memory management fault enable */
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#define SCB_SHCSR_MEMFAULTENA (1 << 16)
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/* SVCALLPENDED: SVC call pending */
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#define SCB_SHCSR_SVCALLPENDED (1 << 15)
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/* BUSFAULTPENDED: Bus fault exception pending */
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#define SCB_SHCSR_BUSFAULTPENDED (1 << 14)
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/* MEMFAULTPENDED: Memory management fault exception pending */
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#define SCB_SHCSR_MEMFAULTPENDED (1 << 13)
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/* USGFAULTPENDED: Usage fault exception pending */
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#define SCB_SHCSR_USGFAULTPENDED (1 << 12)
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/* SYSTICKACT: SysTick exception active */
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#define SCB_SHCSR_SYSTICKACT (1 << 11)
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/* PENDSVACT: PendSV exception active */
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#define SCB_SHCSR_PENDSVACT (1 << 10)
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/* Bit 9: reserved - must be kept cleared */
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/* MONITORACT: Debug monitor active */
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#define SCB_SHCSR_MONITORACT (1 << 8)
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/* SVCALLACT: SVC call active */
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#define SCB_SHCSR_SVCALLACT (1 << 7)
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/* Bits [6:4]: reserved - must be kept cleared */
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/* USGFAULTACT: Usage fault exception active */
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#define SCB_SHCSR_USGFAULTACT (1 << 3)
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/* Bit 2: reserved - must be kept cleared */
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/* BUSFAULTACT: Bus fault exception active */
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#define SCB_SHCSR_BUSFAULTACT (1 << 1)
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/* MEMFAULTACT: Memory management fault exception active */
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#define SCB_SHCSR_MEMFAULTACT (1 << 0)
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/* --- SCB_CFSR values ----------------------------------------------------- */
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/* Bits [31:26]: reserved - must be kept cleared */
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/* DIVBYZERO: Divide by zero usage fault */
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#define SCB_CFSR_DIVBYZERO (1 << 25)
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/* UNALIGNED: Unaligned access usage fault */
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#define SCB_CFSR_UNALIGNED (1 << 24)
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/* Bits [23:20]: reserved - must be kept cleared */
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/* NOCP: No coprocessor usage fault */
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#define SCB_CFSR_NOCP (1 << 19)
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/* INVPC: Invalid PC load usage fault */
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#define SCB_CFSR_INVPC (1 << 18)
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/* INVSTATE: Invalid state usage fault */
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#define SCB_CFSR_INVSTATE (1 << 17)
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/* UNDEFINSTR: Undefined instruction usage fault */
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#define SCB_CFSR_UNDEFINSTR (1 << 16)
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/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */
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#define SCB_CFSR_BFARVALID (1 << 15)
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/* Bits [14:13]: reserved - must be kept cleared */
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/* STKERR: Bus fault on stacking for exception entry */
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#define SCB_CFSR_STKERR (1 << 12)
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/* UNSTKERR: Bus fault on unstacking for a return from exception */
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#define SCB_CFSR_UNSTKERR (1 << 11)
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/* IMPRECISERR: Imprecise data bus error */
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#define SCB_CFSR_IMPRECISERR (1 << 10)
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/* PRECISERR: Precise data bus error */
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#define SCB_CFSR_PRECISERR (1 << 9)
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/* IBUSERR: Instruction bus error */
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#define SCB_CFSR_IBUSERR (1 << 8)
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/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */
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#define SCB_CFSR_MMARVALID (1 << 7)
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/* Bits [6:5]: reserved - must be kept cleared */
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/* MSTKERR: Memory manager fault on stacking for exception entry */
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#define SCB_CFSR_MSTKERR (1 << 4)
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/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */
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#define SCB_CFSR_MUNSTKERR (1 << 3)
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/* Bit 2: reserved - must be kept cleared */
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/* DACCVIOL: Data access violation flag */
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#define SCB_CFSR_DACCVIOL (1 << 1)
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/* IACCVIOL: Instruction access violation flag */
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#define SCB_CFSR_IACCVIOL (1 << 0)
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/* --- SCB_HFSR values ----------------------------------------------------- */
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/* DEBUG_VT: reserved for debug use */
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#define SCB_HFSR_DEBUG_VT (1 << 31)
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/* FORCED: Forced hard fault */
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#define SCB_HFSR_FORCED (1 << 30)
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/* Bits [29:2]: reserved - must be kept cleared */
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/* VECTTBL: Vector table hard fault */
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#define SCB_HFSR_VECTTBL (1 << 1)
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/* Bit 0: reserved - must be kept cleared */
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/* --- SCB_MMFAR values ---------------------------------------------------- */
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/* MMFAR [31:0]: Memory management fault address */
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/* --- SCB_BFAR values ----------------------------------------------------- */
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/* BFAR [31:0]: Bus fault address */
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/* --- SCB functions ------------------------------------------------------- */
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/* TODO: */
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#endif
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