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stm32l1: rcc: use better naming for flash wait states

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More compatible with developments in l0/l4/f7, and just a better choice
of names overall.
This commit is contained in:
Karl Palsson 2017-05-06 12:48:01 +00:00
parent 29c712326f
commit ec1d2855b0
2 changed files with 11 additions and 13 deletions
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2
include/libopencm3/stm32/l1/rcc.h
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@ -411,7 +411,7 @@ struct rcc_clock_scale {
uint8_t pll_mul;
uint16_t pll_div;
uint8_t pll_source;
uint32_t flash_config;
uint8_t flash_waitstates;
uint8_t hpre;
uint8_t ppre1;
uint8_t ppre2;

22
lib/stm32/l1/rcc.c
View File

@ -57,7 +57,7 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_LATENCY_1WS,
.flash_waitstates = 1,
.ahb_frequency = 24000000,
.apb1_frequency = 24000000,
.apb2_frequency = 24000000,
@ -70,7 +70,7 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_LATENCY_1WS,
.flash_waitstates = 1,
.ahb_frequency = 32000000,
.apb1_frequency = 32000000,
.apb2_frequency = 32000000,
@ -80,7 +80,7 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_LATENCY_0WS,
.flash_waitstates = 0,
.ahb_frequency = 16000000,
.apb1_frequency = 16000000,
.apb2_frequency = 16000000,
@ -90,7 +90,7 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_LATENCY_0WS,
.flash_waitstates = 0,
.ahb_frequency = 4000000,
.apb1_frequency = 4000000,
.apb2_frequency = 4000000,
@ -100,7 +100,7 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_LATENCY_0WS,
.flash_waitstates = 0,
.ahb_frequency = 4194000,
.apb1_frequency = 4194000,
.apb2_frequency = 4194000,
@ -111,7 +111,7 @@ const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = PWR_SCALE1,
.flash_config = FLASH_ACR_LATENCY_0WS,
.flash_waitstates = 0,
.ahb_frequency = 2097000,
.apb1_frequency = 2097000,
.apb2_frequency = 2097000,
@ -452,8 +452,7 @@ void rcc_clock_setup_msi(const struct rcc_clock_scale *clock)
/* I guess this should be in the settings? */
flash_64bit_enable();
flash_prefetch_enable();
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
flash_set_ws(clock->flash_waitstates);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
@ -487,13 +486,13 @@ void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock)
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
flash_set_ws(clock->flash_config);
flash_set_ws(clock->flash_waitstates);
} else {
/* going down, slow down before cutting power */
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
flash_set_ws(clock->flash_config);
flash_set_ws(clock->flash_waitstates);
pwr_set_vos_scale(clock->voltage_scale);
}
@ -534,8 +533,7 @@ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
/* I guess this should be in the settings? */
flash_64bit_enable();
flash_prefetch_enable();
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
flash_set_ws(clock->flash_waitstates);
rcc_set_pll_configuration(clock->pll_source, clock->pll_mul,
clock->pll_div);