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stm32f4: rcc: add plli2s config function

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Jonathan Halmen 2019-07-27 19:29:47 +02:00 committed by Karl Palsson
parent 203d0ca295
commit ec2d96433f
2 changed files with 13 additions and 0 deletions
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1
include/libopencm3/stm32/f4/rcc.h
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@ -1080,6 +1080,7 @@ void rcc_osc_on(enum rcc_osc osc);
void rcc_osc_off(enum rcc_osc osc); void rcc_osc_off(enum rcc_osc osc);
void rcc_css_enable(void); void rcc_css_enable(void);
void rcc_css_disable(void); void rcc_css_disable(void);
void rcc_plli2s_config(uint16_t n, uint8_t r);
void rcc_pllsai_config(uint16_t n, uint16_t p, uint16_t q, uint16_t r); void rcc_pllsai_config(uint16_t n, uint16_t p, uint16_t q, uint16_t r);
void rcc_pllsai_postscalers(uint8_t q, uint8_t r); void rcc_pllsai_postscalers(uint8_t q, uint8_t r);
void rcc_set_sysclk_source(uint32_t clk); void rcc_set_sysclk_source(uint32_t clk);

12
lib/stm32/f4/rcc.c
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@ -542,6 +542,18 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON; RCC_CR &= ~RCC_CR_CSSON;
} }
/**
* Set the dividers for the PLLI2S clock outputs
* @param n valid range depends on target device, check your RefManual.
* @param r valid range is 2..7
*/
void rcc_plli2s_config(uint16_t n, uint8_t r)
{
RCC_PLLI2SCFGR = (
((n & RCC_PLLI2SCFGR_PLLI2SN_MASK) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) |
((r & RCC_PLLI2SCFGR_PLLI2SR_MASK) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT));
}
/** /**
* Set the dividers for the PLLSAI clock outputs * Set the dividers for the PLLSAI clock outputs
* divider p is only available on F4x9 parts, pass 0 for other parts. * divider p is only available on F4x9 parts, pass 0 for other parts.